Philips 32PFL5606D, 40PFL3606D, 32PFL3606D Schematic

Published by ER/JY 1164 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 19130

2011-Apr-29

©

Copyright 2011 Koninklijke Philips Electronics N.V.

All rights reserved. No part of this publication may be reproduced, stored in a

retrieval system or transmitted, in any form or by any means, electronic, mechanical,

photocopying, or otherwise without the prior permission of Philips.

Colour Television Chassis

L11M1.1L

LA

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Contents Page

1. Revision List 2

2. Technical Specifications and Connections 2

3. Precautions, Notes, and Abbreviation List 4

4. Mechanical Instructions 8

5. Service Modes, Error Codes, and Fault Finding 12

6. Alignments 18

7. Circuit Descriptions 20

8. IC Data Sheets 26

9. Block Diagrams

Wiring Diagram 32" (Thriller) 35

Wiring Diagram 40" (Thriller) 36

Block Diagram Video 37

Block Diagram Audio 38

Block Diagram Control & Clock Signals 39

Block Diagram I2C 40

Supply Lines Overview 41

10. Circuit Diagrams and PWB Layouts

B01 393912365052 42

B02 393912365052 43

B03 393912365052 45

B04 393912365052 46

B05 393912365052 50

B06 393912365052 52

B07 393912365052 56

313912365052 SSB Layout 57

T01 393912365071 59

313912365071 TCON Layout 65

11. Styling Sheets

Styling Sheet Thriller 32" 66

Styling Sheet Thriller 40" 67

Revision List

EN 2 L11M1.1L LA1.

2011-Apr-29

1. Revision List

Manual xxxx xxx xxxx.0

• First release.

2. Technical Specifications and Connections

Index of this chapter:

2.1 Technical Specifications

2.2 Directions for Use

2.3 Connections

Notes:

• Figures can deviate due to the different set executions.

• Specifications are indicative (subject to change).

2.1 Technical Specifications

For on-line product support please use the links in Table 2-1.

Here is product information available, as well as getting started,

user manuals, frequently asked questions and software &

drivers.

Table 2-1 Described Model numbers

2.2 Directions for Use

You can download this information from the following websites:

http://www.philips.com/support

http://www.p4c.philips.com

2.3 Connections

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used

(according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green,

Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.

2.3.1 Side Connections

1 - USB2.0

Figure 2-2 USB (type A)

CTN Styling Published in:

32PFL3606D/78

Thriller 3122 785 19130

40PFL3606D/78

SROTCENNOC EDISSROTCENNOC RAER

DIGITAL

AUDIO OUT

AUDIO IN

DVI/VGA

SERV.U

R L Pr Pb Y

CVI 1

BOTTOM REAR CONNECTORS

VGA

HDMI 1

(ARC)

R L Pr Pb Y

CVI 2

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Technical Specifications and Connections

EN 3L11M1.1L LA 2.

2011-Apr-29

1 -+5V k

2 -Data (-) jk

3 -Data (+) jk

4 -Ground Gnd H

2 - AV IN: Cinch: Video CVBS - In, Audio - In

Ye -Video CVBS 1 V

PP

/ 75 ohm jq

Wh -Audio L 0.5 V

RMS

/ 10 kohm jq

Rd -Audio R 0.5 V

RMS

/ 10 kohm jq

3 - HDMI: Digital Video, Digital Audio - In

Figure 2-3 HDMI (type A) connector

1 -D2+ Data channel j

2-Shield Gnd H

3 -D2- Data channel j

4 -D1+ Data channel j

5-Shield Gnd H

6 -D1- Data channel j

7 -D0+ Data channel j

8-Shield Gnd H

9 -D0- Data channel j

10 - CLK+ Data channel j

11 - Shield Gnd H

12 - CLK- Data channel j

13 - Easylink Control channel/CEC jk

14 - n.c.

15 - DDC_SCL DDC clock j

16 - DDC_SDA DDC data jk

17 - Ground Gnd H

18 - +5V j

19 - HPD Hot Plug Detect j

20 - Ground Gnd H

2.3.2 Rear Connections

4 - CVI-1: Cinch: Video YPbPr - In, Audio - In

Wh -Audio - L 0.5 V

RMS

/ 10 kΩ jq

Rd -Audio - R 0.5 V

RMS

/ 10 kΩ jq

Rd -Video Pr 0.7 V

PP

/ 75 Ω jq

Bu - Video Pb 0.7 V

PP

/ 75 Ω jq

Gn - Video Y 1 V

PP

/ 75 Ω jq

5 - Cinch: Digital Audio - Out

Bk -Coaxial 0.4 - 0.6V

PP

/ 75 ohm kq

6 - Service Connector (UART)

1 -Ground Gnd H

2 -UART_TX Transmit k

3 -UART_RX Receive j

7 - Mini Jack: Audio - In DVI/VGA

Bk -Audio 0.5 V

RMS

/ 10 kΩ jo

2.3.3 Bottom Connections

8 - CVI-2: Cinch: Video YPbPr - In, Audio - In

Wh -Audio - L 0.5 V

RMS

/ 10 kΩ jq

Rd -Audio - R 0.5 V

RMS

/ 10 kΩ jq

Rd -Video Pr 0.7 V

PP

/ 75 Ω jq

Bu - Video Pb 0.7 V

PP

/ 75 Ω jq

Gn - Video Y 1 V

PP

/ 75 Ω jq

9 - HDMI1: Digital Video, Digital Audio - In

Figure 2-4 HDMI (type A) connector

1 -D2+ Data channel j

2 -Shield Gnd H

3 -D2- Data channel j

4 -D1+ Data channel j

5 -Shield Gnd H

6 -D1- Data channel j

7 -D0+ Data channel j

8 -Shield Gnd H

9 -D0- Data channel j

10 - CLK+ Data channel j

11 - Shield Gnd H

12 - CLK- Data channel j

13 - Easylink Control channel/CEC jk

14 - ARC Audio Return Channel j

15 - DDC_SCL DDC clock j

16 - DDC_SDA DDC data jk

17 - Ground Gnd H

18 - +5V j

19 - HPD Hot Plug Detect j

20 - Ground Gnd H

10 - Aerial - In

- -F-type Coax, 75 Ω D

11 - VGA: Video RGB - In

Figure 2-5 VGA Connector

1 -Video Red 0.7 V

PP

/ 75 Ω j

2 -Video Green 0.7 V

PP

/ 75 Ω j

3 -Video Blue 0.7 V

PP

/ 75 Ω j

4-n.c.

5 -Ground Gnd H

6 -Ground Red Gnd H

7 -Ground Green Gnd H

8 -Ground Blue Gnd H

9-+5V

DC

+5 V j

10 - Ground Sync Gnd H

11 - n.c.

12 - DDC_SDA DDC data j

13 - H-sync 0 - 5 V j

14 - V-sync 0 - 5 V j

15 - DDC_SCL DDC clock j

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Precautions, Notes, and Abbreviation List

EN 4 L11M1.1L LA3.

2011-Apr-29

3. Precautions, Notes, and Abbreviation List

Index of this chapter:

3.1 Safety Instructions

3.2 Warnings

3.3 Notes

3.4 Abbreviation List

3.1 Safety Instructions

Safety regulations require the following during a repair:

• Connect the set to the Mains/AC Power via an isolation

transformer (> 800 VA).

• Replace safety components, indicated by the symbol h,

only by components identical to the original ones. Any

other component substitution (other than original type) may

increase risk of fire or electrical shock hazard.

Safety regulations require that after a repair, the set must be

returned in its original condition. Pay in particular attention to

the following points:

• Route the wire trees correctly and fix them with the

mounted cable clamps.

• Check the insulation of the Mains/AC Power lead for

external damage.

• Check the strain relief of the Mains/AC Power cord for

proper function.

• Check the electrical DC resistance between the Mains/AC

Power plug and the secondary side (only for sets that have

a Mains/AC Power isolated power supply):

1. Unplug the Mains/AC Power cord and connect a wire

between the two pins of the Mains/AC Power plug.

2. Set the Mains/AC Power switch to the “on” position

(keep the Mains/AC Power cord unplugged!).

3. Measure the resistance value between the pins of the

Mains/AC Power plug and the metal shielding of the

tuner or the aerial connection on the set. The reading

should be between 4.5 MΩ and 12 MΩ.

4. Switch “off” the set, and remove the wire between the

two pins of the Mains/AC Power plug.

• Check the cabinet for defects, to prevent touching of any

inner parts by the customer.

3.2 Warnings

• All ICs and many other semiconductors are susceptible to

electrostatic discharges (ESD w). Careless handling

during repair can reduce life drastically. Make sure that,

during repair, you are connected with the same potential as

the mass of the set by a wristband with resistance. Keep

components and tools also at this same potential.

• Be careful during measurements in the high voltage

section.

• Never replace modules or other components while the unit

is switched “on”.

• When you align the set, use plastic rather than metal tools.

This will prevent any short circuits and the danger of a

circuit becoming unstable.

3.3 Notes

3.3.1 General

• Measure the voltages and waveforms with regard to the

chassis (= tuner) ground (H), or hot ground (I), depending

on the tested area of circuitry. The voltages and waveforms

shown in the diagrams are indicative. Measure them in the

Service Default Mode with a colour bar signal and stereo

sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and

picture carrier at 475.25 MHz for PAL, or 61.25 MHz for

NTSC (channel 3).

• Where necessary, measure the waveforms and voltages

with (D) and without (E) aerial signal. Measure the

voltages in the power supply section both in normal

operation (G) and in stand-by (F). These values are

indicated by means of the appropriate symbols.

3.3.2 Schematic Notes

• All resistor values are in ohms, and the value multiplier is

often used to indicate the decimal point location (e.g. 2K2

indicates 2.2 kΩ).

• Resistor values with no multiplier may be indicated with

either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).

• All capacitor values are given in micro-farads (μ=× 10

-6

),

nano-farads (n =× 10

-9

), or pico-farads (p =× 10

-12

).

• Capacitor values may also use the value multiplier as the

decimal point indication (e.g. 2p2 indicates 2.2 pF).

• An “asterisk” (*) indicates component usage varies. Refer

to the diversity tables for the correct values.

• The correct component values are listed on the Philips

Spare Parts Web Portal.

3.3.3 Spare Parts

For the latest spare part overview, consult your Philips Spare

Part web portal.

3.3.4 BGA (Ball Grid Array) ICs

Introduction

For more information on how to handle BGA devices, visit this

URL: http://www.atyourservice-magazine.com

. Select

“Magazine”, then go to “Repair downloads”. Here you will find

Information on how to deal with BGA-ICs.

BGA Temperature Profiles

For BGA-ICs, you must use the correct temperature-profile.

Where applicable and available, this profile is added to the IC

Data Sheet information section in this manual.

3.3.5 Lead-free Soldering

Due to lead-free technology some rules have to be respected

by the workshop during a repair:

• Use only lead-free soldering tin. If lead-free solder paste is

required, please contact the manufacturer of your soldering

equipment. In general, use of solder paste within

workshops should be avoided because paste is not easy to

store and to handle.

• Use only adequate solder tools applicable for lead-free

soldering tin. The solder tool must be able:

– To reach a solder-tip temperature of at least 400°C.

– To stabilize the adjusted temperature at the solder-tip.

– To exchange solder-tips for different applications.

• Adjust your solder tool so that a temperature of around

360°C - 380°C is reached and stabilized at the solder joint.

Heating time of the solder-joint should not exceed ~ 4 sec.

Avoid temperatures above 400°C, otherwise wear-out of

tips will increase drastically and flux-fluid will be destroyed.

To avoid wear-out of tips, switch “off” unused equipment or

reduce heat.

• Mix of lead-free soldering tin/parts with leaded soldering

tin/parts is possible but PHILIPS recommends strongly to

avoid mixed regimes. If this cannot be avoided, carefully

clear the solder-joint from old tin and re-solder with new tin.

3.3.6 Alternative BOM identification

It should be noted that on the European Service website,

“Alternative BOM” is referred to as “Design variant”.

Precautions, Notes, and Abbreviation List

EN 5L11M1.1L LA 3.

2011-Apr-29

The third digit in the serial number (example:

AG2B0335000001) indicates the number of the alternative

B.O.M. (Bill Of Materials) that has been used for producing the

specific TV set. In general, it is possible that the same TV

model on the market is produced with e.g. two different types

of displays, coming from two different suppliers. This will then

result in sets which have the same CTN (Commercial Type

Number; e.g. 28PW9515/12) but which have a different B.O.M.

number.

By looking at the third digit of the serial number, one can

identify which B.O.M. is used for the TV set he is working with.

If the third digit of the serial number contains the number “1”

(example: AG1B033500001), then the TV set has been

manufactured according to B.O.M. number 1. If the third digit is

a “2” (example: AG2B0335000001), then the set has been

produced according to B.O.M. no. 2. This is important for

ordering the correct spare parts!

For the third digit, the numbers 1...9 and the characters A...Z

can be used, so in total: 9 plus 26= 35 different B.O.M.s can be

indicated by the third digit of the serial number.

Identification: The bottom line of a type plate gives a 14-digit

serial number. Digits 1 and 2 refer to the production centre (e.g.

SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M.

code, digit 4 refers to the Service version change code, digits 5

and 6 refer to the production year, and digits 7 and 8 refer to

production week (in example below it is 2010 week 10 / 2010

week 17). The 6 last digits contain the serial number.

Figure 3-1 Serial number (example)

3.3.7 Board Level Repair (BLR) or Component Level Repair

(CLR)

If a board is defective, consult your repair procedure to decide

if the board has to be exchanged or if it should be repaired on

component level.

If your repair procedure says the board should be exchanged

completely, do not solder on the defective board. Otherwise, it

cannot be returned to the O.E.M. supplier for back charging!

3.3.8 Practical Service Precautions

• It makes sense to avoid exposure to electrical shock.

While some sources are expected to have a possible

dangerous impact, others of quite high potential are of

limited current and are sometimes held in less regard.

• Always respect voltages. While some may not be

dangerous in themselves, they can cause unexpected

reactions that are best avoided. Before reaching into a

powered TV set, it is best to test the high voltage insulation.

It is easy to do, and is a good service precaution.

3.4 Abbreviation List

0/6/12 SCART switch control signal on A/V

board. 0 = loop through (AUX to TV),

6 = play 16 : 9 format, 12 = play 4 : 3

format

AARA Automatic Aspect Ratio Adaptation:

algorithm that adapts aspect ratio to

remove horizontal black bars; keeps

the original aspect ratio

ACI Automatic Channel Installation:

algorithm that installs TV channels

directly from a cable network by

means of a predefined TXT page

ADC Analogue to Digital Converter

AFC Automatic Frequency Control: control

signal used to tune to the correct

frequency

AGC Automatic Gain Control: algorithm that

controls the video input of the feature

box

AM Amplitude Modulation

AP Asia Pacific

AR Aspect Ratio: 4 by 3 or 16 by 9

ASF Auto Screen Fit: algorithm that adapts

aspect ratio to remove horizontal black

bars without discarding video

information

ATSC Advanced Television Systems

Committee, the digital TV standard in

the USA

ATV See Auto TV

Auto TV A hardware and software control

system that measures picture content,

and adapts image parameters in a

dynamic way

AV External Audio Video

AVC Audio Video Controller

AVIP Audio Video Input Processor

B/G Monochrome TV system. Sound

carrier distance is 5.5 MHz

BDS Business Display Solutions (iTV)

BLR Board-Level Repair

BTSC Broadcast Television Standard

Committee. Multiplex FM stereo sound

system, originating from the USA and

used e.g. in LATAM and AP-NTSC

countries

B-TXT Blue TeleteXT

C Centre channel (audio)

CEC Consumer Electronics Control bus:

remote control bus on HDMI

connections

CL Constant Level: audio output to

connect with an external amplifier

CLR Component Level Repair

ComPair Computer aided rePair

CP Connected Planet / Copy Protection

CSM Customer Service Mode

CTI Color Transient Improvement:

manipulates steepness of chroma

transients

CVBS Composite Video Blanking and

Synchronization

DAC Digital to Analogue Converter

DBE Dynamic Bass Enhancement: extra

low frequency amplification

DCM Data Communication Module. Also

referred to as System Card or

Smartcard (for iTV).

DDC See “E-DDC”

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Precautions, Notes, and Abbreviation List

EN 6 L11M1.1L LA3.

2011-Apr-29

D/K Monochrome TV system. Sound

carrier distance is 6.5 MHz

DFI Dynamic Frame Insertion

DFU Directions For Use: owner's manual

DMR Digital Media Reader: card reader

DMSD Digital Multi Standard Decoding

DNM Digital Natural Motion

DNR Digital Noise Reduction: noise

reduction feature of the set

DRAM Dynamic RAM

DRM Digital Rights Management

DSP Digital Signal Processing

DST Dealer Service Tool: special remote

control designed for service

technicians

DTCP Digital Transmission Content

Protection; A protocol for protecting

digital audio/video content that is

traversing a high speed serial bus,

such as IEEE-1394

DVB-C Digital Video Broadcast - Cable

DVB-T Digital Video Broadcast - Terrestrial

DVD Digital Versatile Disc

DVI(-d) Digital Visual Interface (d= digital only)

E-DDC Enhanced Display Data Channel

(VESA standard for communication

channel and display). Using E-DDC,

the video source can read the EDID

information form the display.

EDID Extended Display Identification Data

(VESA standard)

EEPROM Electrically Erasable and

Programmable Read Only Memory

EMI Electro Magnetic Interference

EPG Electronic Program Guide

EPLD Erasable Programmable Logic Device

EU Europe

EXT EXTernal (source), entering the set by

SCART or by cinches (jacks)

FDS Full Dual Screen (same as FDW)

FDW Full Dual Window (same as FDS)

FLASH FLASH memory

FM Field Memory or Frequency

Modulation

FPGA Field-Programmable Gate Array

FTV Flat TeleVision

Gb/s Giga bits per second

G-TXT Green TeleteXT

H H_sync to the module

HD High Definition

HDD Hard Disk Drive

HDCP High-bandwidth Digital Content

Protection: A “key” encoded into the

HDMI/DVI signal that prevents video

data piracy. If a source is HDCP coded

and connected via HDMI/DVI without

the proper HDCP decoding, the

picture is put into a “snow vision” mode

or changed to a low resolution. For

normal content distribution the source

and the display device must be

enabled for HDCP “software key”

decoding.

HDMI High Definition Multimedia Interface

HP HeadPhone

I Monochrome TV system. Sound

carrier distance is 6.0 MHz

I

2

C Inter IC bus

I

2

D Inter IC Data bus

I

2

S Inter IC Sound bus

IF Intermediate Frequency

IR Infra Red

IRQ Interrupt Request

ITU-656 The ITU Radio communication Sector

(ITU-R) is a standards body

subcommittee of the International

Telecommunication Union relating to

radio communication. ITU-656 (a.k.a.

SDI), is a digitized video format used

for broadcast grade video.

Uncompressed digital component or

digital composite signals can be used.

The SDI signal is self-synchronizing,

uses 8 bit or 10 bit data words, and has

a maximum data rate of 270 Mbit/s,

with a minimum bandwidth of 135

MHz.

iTV Institutional TeleVision; TV sets for

hotels, hospitals etc.

LS Last Status; The settings last chosen

by the customer and read and stored

in RAM or in the NVM. They are called

at start-up of the set to configure it

according to the customer's

preferences

LATAM Latin America

LCD Liquid Crystal Display

LED Light Emitting Diode

L/L' Monochrome TV system. Sound

carrier distance is 6.5 MHz. L' is Band

I, L is all bands except for Band I

LPL LG.Philips LCD (supplier)

LS Loudspeaker

LVDS Low Voltage Differential Signalling

Mbps Mega bits per second

M/N Monochrome TV system. Sound

carrier distance is 4.5 MHz

MHEG Part of a set of international standards

related to the presentation of

multimedia information, standardised

by the Multimedia and Hypermedia

Experts Group. It is commonly used as

a language to describe interactive

television services

MIPS Microprocessor without Interlocked

Pipeline-Stages; A RISC-based

microprocessor

MOP Matrix Output Processor

MOSFET Metal Oxide Silicon Field Effect

Transistor, switching device

MPEG Motion Pictures Experts Group

MPIF Multi Platform InterFace

MUTE MUTE Line

MTV Mainstream TV: TV-mode with

Consumer TV features enabled (iTV)

NC Not Connected

NICAM Near Instantaneous Compounded

Audio Multiplexing. This is a digital

sound system, mainly used in Europe.

NTC Negative Temperature Coefficient,

non-linear resistor

NTSC National Television Standard

Committee. Color system mainly used

in North America and Japan. Color

carrier NTSC M/N= 3.579545 MHz,

NTSC 4.43= 4.433619 MHz (this is a

VCR norm, it is not transmitted off-air)

NVM Non-Volatile Memory: IC containing

TV related data such as alignments

O/C Open Circuit

OSD On Screen Display

OAD Over the Air Download. Method of

software upgrade via RF transmission.

Upgrade software is broadcasted in

TS with TV channels.

OTC On screen display Teletext and

Control; also called Artistic (SAA5800)

P50 Project 50: communication protocol

between TV and peripherals

Precautions, Notes, and Abbreviation List

EN 7L11M1.1L LA 3.

2011-Apr-29

PAL Phase Alternating Line. Color system

mainly used in West Europe (colour

carrier = 4.4336 19 MHz) and South

America (colour carrier

PAL M = 3.575612 MHz and

PAL N = 3.582056 MHz)

PCB Printed Circuit Board (same as “PWB”)

PCM Pulse Code Modulation

PDP Plasma Display Panel

PFC Power Factor Corrector (or Pre-

conditioner)

PIP Picture In Picture

PLL Phase Locked Loop. Used for e.g.

FST tuning systems. The customer

can give directly the desired frequency

POD Point Of Deployment: a removable

CAM module, implementing the CA

system for a host (e.g. a TV-set)

POR Power On Reset, signal to reset the uP

PSDL Power Supply for Direct view LED

backlight with 2D-dimming

PSL Power Supply with integrated LED

drivers

PSLS Power Supply with integrated LED

drivers with added Scanning

functionality

PTC Positive Temperature Coefficient,

non-linear resistor

PWB Printed Wiring Board (same as “PCB”)

PWM Pulse Width Modulation

QRC Quasi Resonant Converter

QTNR Quality Temporal Noise Reduction

QVCP Quality Video Composition Processor

RAM Random Access Memory

RGB Red, Green, and Blue. The primary

color signals for TV. By mixing levels

of R, G, and B, all colors (Y/C) are

reproduced.

RC Remote Control

RC5 / RC6 Signal protocol from the remote

control receiver

RESET RESET signal

ROM Read Only Memory

RSDS Reduced Swing Differential Signalling

data interface

R-TXT Red TeleteXT

SAM Service Alignment Mode

S/C Short Circuit

SCART Syndicat des Constructeurs

d'Appareils Radiorécepteurs et

Téléviseurs

SCL Serial Clock I

2

C

SCL-F CLock Signal on Fast I

2

C bus

SD Standard Definition

SDA Serial Data I

2

C

SDA-F DAta Signal on Fast I

2

C bus

SDI Serial Digital Interface, see “ITU-656”

SDRAM Synchronous DRAM

SECAM SEequence Couleur Avec Mémoire.

Colour system mainly used in France

and East Europe. Colour

carriers = 4.406 250 MHz and

4.250000 MHz

SIF Sound Intermediate Frequency

SMPS Switched Mode Power Supply

SoC System on Chip

SOG Sync On Green

SOPS Self Oscillating Power Supply

SPI Serial Peripheral Interface bus; a 4-

wire synchronous serial data link

standard

S/PDIF Sony Philips Digital InterFace

SRAM Static RAM

SRP Service Reference Protocol

SSB Small Signal Board

SSC Spread Spectrum Clocking, used to

reduce the effects of EMI

STB Set Top Box

STBY STand-BY

SVGA 800 × 600 (4:3)

SVHS Super Video Home System

SW Software

SWAN Spatial temporal Weighted Averaging

Noise reduction

SXGA 1280 × 1024

TFT Thin Film Transistor

THD Total Harmonic Distortion

TMDS Transmission Minimized Differential

Signalling

TS Transport Stream

TXT TeleteXT

TXT-DW Dual Window with TeleteXT

UI User Interface

uP Microprocessor

UXGA 1600 × 1200 (4:3)

V V-sync to the module

VESA Video Electronics Standards

Association

VGA 640 × 480 (4:3)

VL Variable Level out: processed audio

output toward external amplifier

VSB Vestigial Side Band; modulation

method

WYSIWYR What You See Is What You Record:

record selection that follows main

picture and sound

WXGA 1280 × 768 (15:9)

XTAL Quartz crystal

XGA 1024 × 768 (4:3)

Y Luminance signal

Y/C Luminance (Y) and Chrominance (C)

signal

YPbPr Component video. Luminance and

scaled color difference signals (B-Y

and R-Y)

YUV Component video

Mechanical Instructions

EN 8 L11M1.1L LA4.

2011-Apr-29

4. Mechanical Instructions

Index of this chapter:

4.1 Cable Dressing

4.2 Service Positions

4.3 Assy/Panel Removal

4.4 Set Re-assembly

Notes:

• Figures below can deviate slightly from the actual situation,

due to the different set executions.

4.1 Cable Dressing

Figure 4-1 Cable dressing 32"

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Mechanical Instructions

EN 9L11M1.1L LA 4.

2011-Apr-29

Figure 4-2 Cable dressing 40"

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11 mm saddle × 1

150 mm tape × 3

70 mm tape × 4

Foam × 2

Mechanical Instructions

EN 10 L11M1.1L LA4.

2011-Apr-29

4.2 Service Positions

For easy servicing of a TV set, the set should be put face down

on a soft flat surface, foam buffers or other specific workshop

tools. Ensure that a stable situation is created to perform

measurements and alignments. When using foam bars take

care that these always support the cabinet and never only the

display. Caution: Failure to follow these guidelines can

seriously damage the display!

Ensure that ESD safe measures are taken.

4.3 Assy/Panel Removal

Instructions below apply to the 40PFL3606D/78, but will be

similar for other models.

4.3.1 Rear Cover

Figure 4-3 Rear cover removal (40")

Warning: Disconnect the mains power cord before removing

the rear cover.

See Figure 4-3

.

1. Remove fixation screws [2] and [3] that secure the rear

cover. It is not necessary to remove the stand first [1].

2. Lift the rear cover from the TV. Make sure that wires and

flat foils are not damaged while lifting the rear cover from

the set.

3

2

1

19130_004_110426.eps

110426

3

3

2 2

3

2

2

3

3

3

3

2

1

1

2

32

32

1

1

3

Mechanical Instructions

EN 11L11M1.1L LA 4.

2011-Apr-29

4.3.2 LCD Panel

Refer to Figure 4-4

for details.

1. Remove the Stand [A].

2. Remove the Speakers/Subwoofer [B].

3. Remove the PSU [C], SSB [D] and TCON (E).

4. Remove the IR/LED board [F].

5. Remove the Local Control board [G].

6. Remove the clamps [1].

7. Remove all metal subframes [2] that do not belong to the

LCD display.

Figure 4-4 LCD Panel removal (based on 40" model)

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse

order.

Notes:

• While re-assembling, make sure that all cables are placed

and connected in their original position. See Figure 4-5

• Pay special attention not to damage the EMC foams in the

set. Ensure that EMC foams are mounted correctly.

Figure 4-5 Flat Foil Cable (FFC) precautions

19130_006_110426.eps

110426

1A

1B

1C

12 12

12

12

D

E

F

1

1

1111

G

Proper FFC insertion: Silver line is not

visible when connector lock is closed

Improper FFC insertion: Silver line is

visible when connector lock is closed

Panel

Thinner blue FFC supporting

tape belong to Panel side

Thicker blue FFC supporting

tape belong to SSB side

TCON

19130_007_110426.eps

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Service Modes, Error Codes, and Fault Finding

EN 12 L11M1.1L LA5.

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5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:

5.1 Test Points

5.2 Service Modes

5.3 Service Tools

5.4 Error Codes

5.5 The Blinking LED Procedure

5.6 Fault Finding and Repair Tips

5.7 Software Upgrading

5.1 Test Points

In the chassis schematics and layout overviews, the test points

are mentioned. In the schematics and layouts, test points are

indicated with “Fxxx” or “Ixxx”.

As most signals are digital, it will be difficult to measure

waveforms with a standard oscilloscope. Several key ICs are

capable of generating test patterns, which can be controlled via

ComPair. In this way it is possible to determine which part is

defective.

Perform measurements under the following conditions:

• Service Default Mode.

• Video: Colour bar signal.

• Audio: 3 kHz left, 1 kHz right.

5.2 Service Mode s

The Service Mode feature is split into four parts:

• Service Default Mode (SDM).

• Service Alignment Mode (SAM).

• Customer Service Mode (CSM).

• Computer Aided Repair Mode (ComPair).

SDM and SAM offer features, which can be used by the Service

engineer to repair/align a TV set. Some features are:

• A pre-defined situation to ensure measurements can be

made under uniform conditions (SDM).

• Activates the blinking LED procedure for error identification

when no picture is available (SDM).

• The possibility to overrule software protections when SDM

is entered via the Service pins.

• Make alignments (e.g. White Tone), (de)select options,

enter options codes, reset the error buffer (SAM).

• Display information (“SDM” or “SAM” indication in upper

right corner of screen, error buffer, software version,

operating hours, options and option codes, sub menus).

The CSM is a Service Mode that can be enabled by the

consumer. The CSM displays diagnosis information, which the

customer can forward to the dealer or call centre. In CSM

mode, “CSM”, is displayed in the top right corner of the screen.

The information provided in CSM and the purpose of CSM is to:

• Increase the home repair hit rate.

• Decrease the number of nuisance calls.

• Solved customers' problem without home visit.

ComPair Mode is used for communication between a computer

and a TV on I2C /UART level and can be used by a Service

engineer to quickly diagnose the TV set by reading out error

codes, read and write in NVMs, communicate with ICs and the

uP (PWM, registers, etc.), and by making use of a fault finding

database. It will also be possible to up and download the

software of the TV set via I2C with help of ComPair. To do this,

ComPair has to be connected to the TV set via the ComPair

connector, which will be accessible through the rear of the set

(without removing the rear cover).

5.2.1 General

Next items are applicable to all Service Modes or are general.

Life Timer

During the life time cycle of the TV set, a timer is kept (called

“Op. Hour”). It counts the normal operation hours (not the

Stand-by hours). The actual value of the timer is displayed in

SDM and SAM in a decimal value. Every two soft-resets

increase the hour by +1. Stand-by hours are not counted.

Software Identification, Version, and Cluster

The software ID, version, and cluster will be shown in the main

menu display of SDM, SAM, and CSM.

The screen will show: “AAAAAAB-XX.YY”, where:

• AAAAAA is the chassis name: L11M11.

• B is the region indication: E= Europe, A= AP/China, U=

NAFTA, L= LATAM.

• XX is the main version number: this is updated with a major

change of specification (incompatible with the previous

software version). Numbering will go from 01 - 99 and AA -

ZZ.

– If the main version number changes, the new version

number is written in the NVM.

– If the main version number changes, the default

settings are loaded.

• YY is the sub version number: this is updated with a minor

change (backwards compatible with the previous versions)

Numbering will go from 00 - 99.

– If the sub version number changes, the new version

number is written in the NVM.

– If the NVM is fresh, the software identification, version,

and cluster will be written to NVM.

Display Option Code Selection

When after an SSB or display exchange, the display option

code is not set properly, it will result in a TV with “no display”.

Therefore, it is required to set this display option code after

such a repair.

To do so, press the following key sequence on a standard RC

transmitter: “062598” directly followed by MENU/HOME and

“xxx”, where “xxx” is a 3 digit decimal va

lue of

the panel type,

see sticker on the side/bottom of the cabinet. When the value

is accepted and stored in NVM, the set will switch to Stand-by,

to indicate that the process has been completed.

Figure 5-1 Location of Display Option Code sticker

During this algorithm, the NVM-content must be filtered,

because several items in the NVM are TV-related and not SSB-

related (e.g. Model and Prod. S/N). Therefore, “Model” and

“Prod. S/N” data is changed into “See Type Plate”.

In case a call centre or consumer reads “See Type Plate” in

CSM mode, he needs to look to the side/bottom sticker to

identify the set, for further actions.

10000_038_090121.eps

090819

PHILIPS

MODEL:

32PF9968/10

PROD.SERIAL NO:

AG 1A0620 000001

040

39mm

27mm

(CTN Sticker)

Display Option

Code

Service Modes, Error Codes, and Fault Finding

EN 13L11M1.1L LA 5.

2011-Apr-29

5.2.2 Service Default Mode (SDM)

Purpose

Set the TV in SDM mode in order to be able to create a pre-

defined setting for measurements to be made. In this platform,

a simplified SDM is introduced (without protection override and

without tuning to a predefined frequency).

Specifications

• Set linear video and audio settings to 50%, but volume to

25%. Stored user settings are not affected.

• Set Smart Picture to “Game”.

• Set Smart Sound to “Standard”.

• Tune channel to:

- for analogue SDM: channel 3 (61.25 MHz)

- for digital SDM: channel 26 (545.143 MHz).

• For digital SDM: set PID default from the stream.

• All service-unfriendly modes (if present) are disabled, since

they interfere with diagnosing/repairing a set. These

service unfriendly modes are:

– (Sleep) timer.

– Blue mute/Wall paper.

– Auto switch “off” (when there is no “ident” signal).

– Hotel or hospital mode.

– Child lock or parental lock (manual or via V-chip).

– Skipping, blanking of “Not favourite”, “Skipped” or

“Locked” presets/channels.

– Automatic storing of Personal Preset or Last Status

settings.

– Automatic user menu time-out (menu switches back/

OFF automatically.

– Auto Volume levelling (AVL).

How to Activate

To activate analogue SDM, use one of the following methods:

• Press the following key sequence on the RC transmitter:

“062596” directly followed by the MENU button.

• Short one of the “Service” pads on the TV board during cold

start (see Figure 5-2

). Then press the mains button

(remove the short after start-up).

Caution: When doing this, the service-technician must

know exactly what he is doing, as it could damage the

television set.

To activate digital SDM:

• Press the following sequence on the RC transmitter:

“062593” directly followed by the MENU button.

Figure 5-2 Service pads (SSB component side)

On Screen Menu

After activating SDM, the following items are displayed, with

“SDM” in the upper right corner of the screen to indicate that the

television is in Service Default Mode.

Menu items and explanation:

• xxxxx: Operating hours (in decimal).

• AAAAAAB-XX.YY: See paragraph Software

Identification, Version, and Cluster for the SW name

definition.

• ERR: Shows all errors detected since the last time the

buffer was erased in format <xxx> <xxx> <xxx> <xxx>

<xxx> (five errors possible).

• OP: Used to read-out the option bytes. Ten codes (in two

rows) are possible.

How to Navigate

As this mode is read only, there is not much to navigate. To

switch to other modes, use one of the following methods:

• Command MENU from the user remote will enter the

normal user menu (brightness, contrast, color, etc...) with

“SDM” OSD remaining, and pressing MENU key again will

return to the last status of SDM again.

• To prevent the OSD from interfering with measurements in

SDM, command “OSD” or “i+” (“STATUS” or “INFO” for

NAFTA and LATAM) from the user remote will toggle the

OSD “on/off” with “SDM” OSD remaining always “on”.

• Press the following key sequence on the remote control

transmitter: “062596” directly followed by the INFO[i+]/OK

button to switch to SAM (do not allow the display to time out

between entries while keying the sequence).

How to Exit

Switch the set to Stand-by by

• pressing the standby button on the remote control

transmitter or on the television set, or

• via a standard RC-transmitter by keying the “00” sequence.

If you switch the television set “off” by removing the mains (i.e.,

unplugging the television), the television set will remain in SDM

when mains is re-applied, and the error buffer is not cleared.

The error buffer will only be cleared when the “clear” command

is used in the SAM menu.

Note:

• If the TV is switched “off” by a power interrupt while in SDM,

the TV will show up in the last status of SDM menu as soon

as the power is supplied again. The error buffer will not be

cleared.

• In case the set is accidentally in Factory mode (with an “F”

displayed on the screen), pressing and holding “VOL-“

button for 5 seconds and then followed by pressing and

holding the “CH-” button for another 5 seconds should exit

the Factory mode.

5.2.3 Service Alignment Mode (SAM)

Purpose

• To change option settings.

• To display / clear the error code buffer.

• To perform alignments.

Specifications

• Operation hours counter (maximum five digits displayed).

• Software version, error codes, and option settings display.

• Error buffer clearing.

• Option settings.

• Software alignments (White Tone).

• NVM Editor.

• Set screen mode to full screen (all content is visible).

• Set Smart Picture to “Game”.

How to Activate

To activate SAM, use one of the following methods:

• Press the following key sequence on the remote control

transmitter: “062596” directly followed by the INFO[i+] /OK

button. Do not allow the display to time out between entries

while keying the sequence.

• Or via ComPair.

After entering SAM, the following items are displayed, with

“SAM” in the upper right corner of the screen to indicate that the

television is in Service Alignment Mode.

19130_008_110426.eps

110426

SDM

Service Modes, Error Codes, and Fault Finding

EN 14 L11M1.1L LA5.

2011-Apr-29

Menu items and explanation:

1. System Information.

• Op Hour: This represents the life timer. The timer

counts normal operation hours, but does not count

Stand-by hours.

• MAIN SW ID: See paragraph Software Identification,

Version, and Cluster for the SW name definition.

• ERR: Shows all errors detected since the last time the

buffer was erased. Five errors possible.

• OP1/OP2: Used to read-out the option bytes. See

paragraph 6.6 Option Settings

in the Alignments

section for a detailed description. Ten codes are

possible.

2. Tuner.

• AGC Adjustment: See paragraph 6.3.1

for

instructions.

• Store: To store the data.

3. Clear. Erases the contents of the error buffer. Select this

menu item and press the MENU RIGHT key on the remote

control. The content of the error buffer is cleared.

4. Options. To set the option bits. See paragraph 6.6 Option

Settings in the “Alignments” chapter for a detailed

description.

5. RGB Align. To align the White Tone. See White Tone

Alignment: for a detailed description.

6. NVM Editor. To change the NVM data in the television set.

See also paragraph 5.6 Fault Finding and Repair Tips

.

7. Upload to USB.

8. Download from USB.

9. Initialise NVM. To initialize a (corrupted) NVM. Be careful,

this will erase all settings!

10. Auto ADC. Refer to chapter 6. Alignments

for detailed

information.

11. EDID Write Enable. Enables EDID writing (not applicable

to Berlinale sets).

12. Service Data. Virtual Key board for character input entry.

How to Navigate

• In the SAM menu, select menu items with the UP/DOWN

keys on the remote control transmitter. The selected item

will be indicated. When not all menu items fit on the screen,

use the UP/DOWN keys to display the next / previous

menu items.

• With the LEFT/RIGHT keys, it is possible to:

– Activate the selected menu item.

– Change the value of the selected menu item.

– Activate the selected sub menu.

• When you press the MENU button twice while in top level

SAM, the set will switch to the normal user menu (with the

SAM mode still active in the background). To return to the

SAM menu press the MENU button.

• The “INFO[i+]/OK” key from the user remote will toggle the

OSD “on/off” with “SAM” OSD remaining always “on”.

• Press the following key sequence on the remote control

transmitter: “062596” directly followed by the MENU button

to switch to SDM (do not allow the display to time out

between entries while keying the sequence).

How to Store SAM Settings

To store the settings changed in SAM mode (except the

OPTIONS and RGB ALIGN settings), leave the top level SAM

menu by using the POWER button on the remote control

transmitter or the television set. The mentioned exceptions

must be stored separately via the STORE button.

How to Exit

Switch the set to STANDBY by pressing the mains button on

the remote control transmitter or the television set, or by

keying-in the “00” sequence on a standard RC-transmitter.

Note:

• When the TV is switched “off” by a power interrupt while in

SAM, the TV will show up in “normal operation mode” as

soon as the power is supplied again. The error buffer will

not be cleared.

• In case the set is in Factory mode by accident (with “F”

displayed on screen), pressing and holding “VOL-“ button

for 5 seconds and then followed by pressing and holding

the “CH-” button for another 5 seconds should exit the

Factory mode.

5.2.4 Customer Service Mode (CSM)

Purpose

The Customer Service Mode shows error codes and

information on the TV’s operation settings. A call centre can

instruct the customer (by telephone) to enter CSM in order to

identify the status of the set. This helps them to diagnose

problems and failures in the TV before making a service call.

The CSM is a read-only mode; therefore, modifications are not

possible in this mode.

Specifications

• Ignore “Service unfriendly modes”.

• Set volume to 25%.

• Set Smart Picture to “Game”.

• Set Smart Sound to “Standard”.

• Line number for every line (to make CSM language

independent).

• Set the screen mode to full screen (all contents on screen

is visible).

• After leaving the Customer Service Mode, the original

settings are restored.

• Possibility to use “CH+” or “CH-” for channel surfing, or

enter the specific channel number on the RC.

How to Activate

To activate CSM, press the following key sequence on a

standard remote control transmitter: “123654” (do not allow the

display to time out between entries while keying the sequence).

After entering the Customer Service Mode, the following items

are displayed:

Menu Explanation CSM1

1. Set Type. Type number, e.g. 32PFL3605/78. (*)

2. Production code. Product serial no., e.g.

BZ1A1008123456 (*). BZ= Production centre, 1= BOM

code, A= Service version change code, 10= Production

year, 08= Production week, 123456= Serial number.

3. Installation date.

Indicates the date of the first initialization

of the

TV. Th

is date is acquired via time extraction.

4. a - Option Code 1. Option code information (group 1).

b - Option Code 2. Option code information (group 2).

5. SSB. Indication of the SSB factory ID (= 12nc). (*)

6.

Display. Indication of the display ID (=12 nc). (*)

7. PSU. Indication of the PSU factory ID (= 12nc).

(*) If an NVM IC is replaced or initialized, these items must be

re-written to it. ComPair will foresee in a possibility to do this.

Also the NVM editor in the SAM menu can be used.

Menu Explanation CSM2

1. Current Main SW. Shows the main software version.

2. Standby SW. Shows the Stand-by software version.

3. Panel Code. Shows the current display code.

4. Bootloader ID. Shows the Bootloader software ID.

5. NVM Version. The NVM software version no.

6. Flash ID. Shows the flash ID.

Menu Explanation CSM3

1. Signal Quality. Shows the signal quality (No Tuned/Poor/

Average/Good).

2. Child lock. This is a combined item for locks. If any lock

(Preset lock, child lock, lock after, or Parental lock) is

active, this item indicates “active”.

Service Modes, Error Codes, and Fault Finding

EN 15L11M1.1L LA 5.

2011-Apr-29

3. HDCP Keys. Indicates if the HDMI keys (or HDCP keys)

are valid or not. Not applicable to Berlinale series.

4. not used

5. not used

6. not used

7. not used.

Create a CSM dump on an USB stick

There will be CSM dump to a plugged in USB-stick upon

entering CSM-mode. An extended CSM dumpwill be created

when the “OK” button on RC is pressed in CSM while a USB

stick is plugged in. A direct CSM flash dump will be created

when the buttons “red + 2679” on the remote control are

pressed in CSM while a USB stick is plugged in.

How to Exit

To exit CSM, use one of the following methods:

• Press the MENU/HOME button on the remote control

transmitter.

• Press the POWER button on the remote control

transmitter.

• Press the POWER button on the television set.

5.3 Service Tools

5.3.1 ComPair

Introduction

ComPair (Computer Aided Repair) is a Service tool for Philips

Consumer Electronics products. and offers the following:

1. ComPair helps you to quickly get an understanding on how

to repair the chassis in a short and effective way.

2. ComPair allows very detailed diagnostics and is therefore

capable of accurately indicating problem areas. You do not

have to know anything about I2C or UART commands

yourself, because ComPair takes care of this.

3. ComPair speeds up the repair time since it can

automatically communicate with the chassis (when the uP

is working) and all repair information is directly available.

4. ComPair features TV software up possibilities.

Specifications

ComPair consists of a Windows based fault finding program

and an interface box between PC and the (defective) product.

The (new) ComPair II interface box is connected to the PC via

an USB cable. For the TV chassis, the ComPair interface box

and the TV communicate via a bi-directional cable via the

service connector(s).

How to Connect

This is described in the ComPair chassis fault finding database.

Figure 5-3 ComPair II interface connection

Caution: It is compulsory to connect the TV to the PC as

shown in the picture above (with the ComPair interface in

between), as the ComPair interface acts as a level shifter. If

one connects the TV directly to the PC (via UART), ICs will be

blown!

How to Order

ComPair II order codes:

• ComPair II interface: 3122 785 91020.

• ComPair UART interface cable: 3138 188 75051.

• Program software can be downloaded from the Philips

Service web portal.

Note: For this chassis, “Pgammar” and “T-con NVM”

programming (VCOM alignment) are added to ComPair.

Additional cables for VCOM Alignment

•ComPair/I

2

C interface cable: 3122 785 90004.

• ComPair/VGA adapter cable: 9965 100 09269.

5.4 Error Codes

5.4.1 Introduction

Error codes are required to indicate failures in the TV set. In

principle a unique error code is available for every:

• Activated (SW) protection.

• Failing I

2

C device.

• General I

2

C error.

The last five errors, stored in the NVM, are shown in the

Service menu’s. This is called the error buffer.

The error code buffer contains all errors detected since the last

time the buffer was erased. The buffer is written from left to

right. When an error occurs that is not yet in the error code

buffer, it is displayed at the left side and all other errors shift one

position to the right.

An error will be added to the buffer if this error differs from any

error in the buffer. The last found error is displayed on the left.

An error with a designated error code never leads to a

deadlock situation. It must always be diagnosable (e.g. error

buffer via OSD or blinking LED or via ComPair).

In case a failure identified by an error code automatically

results in other error codes (cause and effect), only the error

code of the MAIN failure is displayed.

10000_036_090121.eps

091118

TO

UART SERVICE

CONNECTOR

TO

UART SERVICE

CONNECTOR

TO

I

2

C SERVICE

CONNECTOR

TO TV

PC

HDMI

I

2

C only

Optional power

5V DC

ComPair II Developed by Philips Brugge

RC out

RC in

Optional

Switch

Power ModeLink/

Activity

I

2

C

ComPair II

Multi

function

RS232 /UART

Service Modes, Error Codes, and Fault Finding

EN 16 L11M1.1L LA5.

2011-Apr-29

5.4.2 How to Read the Error Buffer

You can read the error buffer in three ways:

• On screen via the SAM/SDM/CSM (if you have a picture).

Example:

– ERROR: 0 0 0 0 0 : No errors detected

– ERROR: 6 0 0 0 0 : Error code 6 is the last and only

detected error

– ERROR: 9 6 0 0 0 : Error code 6 was detected first and

error code 9 is the last detected (newest) error

• Via the blinking LED procedure (when you have no

picture). See paragraph 5.5 The Blinking LED Procedure

.

•Via ComPair.

5.4.3 Error codes

The “layer 1” error codes are pointing to the defective board.

They are triggered by LED blinking when CSM is activated. In

the LC10 platform, only two boards are present: the SSB and

the PSU/IPB, meaning only the following layer 1 errors are

defined:

• 2: SSB

• 3: IPB/PSU

•4: Display

Table 5-1 Error code table

5.4.4 How to Clear the Error Buffer

The error code buffer is cleared in the following cases:

• By using the CLEAR command in the SAM menu:

• By using the following key sequence on the remote control

transmitter: “062599” directly followed by the OK button.

• If the contents of the error buffer have not changed for 50

hours, the error buffer resets automatically.

Note: If you exit SAM by disconnecting the mains from the

television set, the error buffer is not reset.

5.5 The Blinking LED Proc edure

5.5.1 Introduction

The software is capable of identifying different kinds of errors.

Because it is possible that more than one error can occur over

time, an error buffer is available, which is capable of storing the

last five errors that occurred. This is useful if the OSD is not

working properly.

Errors can also be displayed by the blinking LED procedure.

The method is to repeatedly let the front LED pulse with as

many pulses as the error code number, followed by a period of

1.5 seconds in which the LED is “off”. Then this sequence is

repeated.

Example (1): error code 4 will result in four times the sequence

LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After

this sequence, the LED will be “off” for 1.5 seconds. Any RC

command terminates the sequence. Error code LED blinking is

in red color.

Example (2): the content of the error buffer is “129600”

After entering SDM, the following occurs:

• 1 long blink of 5 seconds to start the sequence,

• 12 short blinks followed by a pause of 1.5 seconds,

• 9 short blinks followed by a pause of 1.5 seconds,

• 6 short blinks followed by a pause of 1.5 seconds,

• 1 long blink of 1.5 seconds to finish the sequence,

• The sequence starts again with 12 short blinks.

5.5.2 Displaying the Entire Error Buffer

Additionally, the entire error buffer is displayed when Service

Mode “SDM” is entered.

5.6 Fault Finding and Repair Tips

Notes:

• It is assumed that the components are mounted correctly

with correct values and no bad solder joints.

• Before any fault finding actions, check if the correct

options are set.

5.6.1 NVM Editor

In some cases, it can be convenient if one directly can change

the NVM contents. This can be done with the “NVM Editor” in

SAM mode. With this option, single bytes can be changed.

Caution:

• Do not change these, without understanding the

function of each setting, because incorrect NVM

settings may seriously hamper the correct functioning

of the TV set!

• Always write down the existing NVM settings, before

changing the settings. This will enable you to return to the

original settings, if the new settings turn out to be incorrect.

5.6.2 Load Default NVM Values

It is possible to download default values automatically into the

NVM in case a blank NVM is placed or when the NVM first 20

address contents are “FF”. After the default values are

downloaded, it is possible to start-up and to start aligning the

TV set. To initiate a forced default download the following

action has to be performed:

1. Switch “off” the TV set with the mains cord disconnected

from the wall outlet (it does not matter if this is from “Stand-

by” or “Off” situation).

2. Short-circuit the SDM pads on the SSB (keep short

circuited, see Figure 5-2

).

3. Press “P+” or “CH+” on the local keyboard (and keep it

pressed).

4. Reconnect the mains supply to the wall outlet.

5. Release the “P+” or “CH+” when the set is started up and

has entered SDM.

When the downloading has completed successfully, the set will

perform a restart. After this, put the set to Stand-by and remove

the short-circuit on the SDM pads.

Alternative method:

It is also possible to upload the default values to the NVM with

ComPair in case the SW is changed, the NVM is replaced with

a new (empty) one, or when the NVM content is corrupted.

After replacing an EEPROM (or with a defective/no EEPROM),

default settings should be used to enable the set to start-up and

allow the Service Default Mode and Service Alignment Mode to

be accessed.

Layer-1

error code

Defective

board

Layer-2

error code Defective device

2 SSB 11 Speaker DC protection active on SSB

3 IPB/PSU 16 +12 missing/low, PSU defective

3 IPB/PSU 17 POK line defective

2 SSB 35 EEPROM I2C error on SSB, M24C16

2 SSB 34 Tuner I2C error on SSB

2 SSB 23 HDMI Mux IC I2C error on SSB - Berninale

models with Mux only

2 SSB 27 Channel decoder on SSB

4 Display

(Inverter)

18 LCD Panel inverter error. INV_STATUS

(for 32” sets only)

Service Modes, Error Codes, and Fault Finding

EN 17L11M1.1L LA 5.

2011-Apr-29

5.6.3 No Picture

When you have no picture, first make sure you have entered

the correct display code.

See Display Option Code Selection

for the instructions.

5.6.4 Unstable Picture via HDMI input

Check (via ComPair) if HDMI EDID data is properly

programmed.

5.6.5 No Picture via HDMI input

Check if HDCP key is valid. This can be done in CSM.

5.6.6 HDMI CEC Not Functioning

Go to Home/Menu ->Setup -> Installation -> Preference and

set the Easylink option to “on”. Also check if the connected

device is CEC enabled.

5.6.7 TV Will Not Start-up from Stand-by.

Possible Stand-by Controller failure. Reflash the SW.

5.7 Software Upgrading

5.7.1 I ntroduction

It is possible for the user to upgrade the main software via the

USB port. This allows replacement of a software image in a

stand alone set. A description on how to upgrade the main

software can be found in the DFU or on the Philips website.

5.7.2 Main Software Upgrade

Automatic Software Upgrade

In “normal” conditions, so when there is no major problem with

the TV, the main software and the default software upgrade

application can be upgraded with the “autorun.upg” (FUS part

in the one-zip file). This can also be done by the consumers

themselves, but they will have to get their software from the

commercial Philips website or via the Software Update

Assistant in the user menu (see DFU). The “autorun.upg” file

must be placed in the root of your USB stick.

How to upgrade:

1. Copy the “autorun.upg” file to the root of an USB stick.

2. Insert the USB stick in the side I/O while the set is “on”.

The TV will prompt an upgrade message. Press “Update”

to continue, after which the upgrading process will start. As

soon as the programming is finished, the set must be

restarted.

In the “Setup” menu you can check if the latest software is

running.

5.7.3 How to Copy NVM Data to/from USB

Write NVM Data to USB

1. Insert the USB stick into the USB slot while in SAM mode.

2. Execute the command "NVM Copy" > "NVM Copy to USB",

to copy the NVM data to the USB stick. The NVM filename

on the USB stick will be named

"L11M11L_NVM_T2U.BIN" (this takes a couple of

seconds).

Write NVM Data to TV

1. First, ensure (via a PC) that the filename on the USB stick

has the correct format: "L11M11L_NVM_U2T.BIN".

2. Insert the USB stick into the USB slot while in SAM mode.

3. Execute the command "NVM Copy" > "NVM Copy from

USB" to copy the USB data to NVM (this takes about a

minute to complete).

To write an NVM mask to the TV, ensure that the mask has the

correct format: "L11M11L_NVM_U2T.MAK" (0x00 to write

protect, 0xFF to overwrite).

Important: The file must be located in the "/Repair" directory

of the USB stick.

5.7.4 How to Copy EDID Data to/from USB

Write EDID Data to USB

1. Insert the USB stick into the USB slot while in SAM mode.

2. Execute the command "NVM Copy" > "EDID Copy to

USB", to copy the EDID data to the USB stick. The

filename on the USB stick will be named

"L11M11L_EDID_T2U.BIN" (this takes a couple of

seconds).

Write EDID Data to TV

1. First, ensure (via a PC) that the filename on the USB stick

has the correct format: "L11M11L_EDID_U2T.BIN".

2. Insert the USB stick into the USB slot while in SAM mode.

3. Execute the command "NVM Copy" > "EDID Copy from

USB" to copy the USB data to EDID (this takes about a

minute to complete).

Important: The file must be located in the "/Repair" directory

of the USB stick.

5.7.5 How to Copy the Channel List to/from USB

Write Channel List Data to USB

1. Insert the USB stick into the USB slot while in SAM mode.

2. Execute the command "Channel list Copy to USB", to copy

the channel list data to the USB stick. The filename on the

USB stick will be named "L11M11L_CHTB_T2U.BIN" (this

takes a couple of seconds).

Write Channel List Data to TV

1. First, ensure (via a PC) that the filename on the USB stick

has the correct format: "L11M11L_CHTB_U2T.BIN".

2. Insert the USB stick into the USB slot while in SAM mode.

3. Execute the command "Chanel list Copy from USB" to

copy the USB data to the TV (this takes about a minute to

complete).

Important: The file must be located in the "/Repair" directory

of the USB stick.

Alignments

EN 18 L11M1.1L LA6.

2011-Apr-29

6. Alignments

Index of this chapter:

6.1 General Alignment Conditions

6.2 Hardware Alignments

6.3 Software Alignments

6.4 ADC gain adjustment

6.6 Option Settings

Note: Figures below can deviate slightly from the actual

situation, due to the different set executions.

General: The Service Default Mode (SDM) and Service

Alignment Mode (SAM) are described in chapter 5. Menu

navigation is done with the CURSOR UP, DOWN, LEFT or

RIGHT keys of the remote control transmitter.

6.1 General Alignment Conditions

Perform all electrical adjustments under the following

conditions:

• Power supply voltage (depends on region):

– AP-NTSC: 120 V

AC

or 230 V

AC

/ 50 Hz (± 10%).

– AP-PAL-multi: 120 - 230 V

AC

/ 50 Hz (± 10%).

– EU: 230 V

AC

/ 50 Hz (± 10%).

– LATAM-NTSC: 120 - 230 V

AC

/ 50 Hz (± 10%).

– US: 120 V

AC

/ 60 Hz (± 10%).

• Connect the set to the mains via an isolation transformer

with low internal resistance.

• Allow the set to warm up for approximately 15 minutes.

• Measure voltages and waveforms in relation to correct

ground (e.g. measure audio signals in relation to

AUDIO_GND).

Caution: It is not allowed to use heatsinks as ground.

• Test probe: Ri > 10 Mohm, Ci < 20 pF.

• Use an isolated trimmer/screwdriver to perform

alignments.

6.2 Hardware Alignments

There are no hardware alignments foreseen for this chassis,

but below find an overview of the most important DC voltages

on the SSB. These can be used for checking proper functioning

of the DC/DC converters.

6.3 Software Alignments

With the software alignments of the Service Alignment Mode

(SAM) the Tuner and RGB settings can be aligned.

6.3.1 Tuner Adjustment (RF AGC Take Over Point)

Purpose: To keep the tuner output signal constant as the input

signal amplitude varies.

No alignment is necessary, as the AGC alignment is done

automatically.

6.3.2 RGB Alignment

Before alignment, set the picture as follows:

White Tone Alignment:

• Activate SAM.

• Select “RGB Align.“ and choose a color temperature.

• Use a 100% white screen as input signal and set the

following values:

– “Red BL Offset” and “Green BL Offset” to “7” (if

present).

– All “White point” values initial to “127”.

In case you have a color analyzer:

• Measure with a calibrated (phosphor- independent) color

analyzer (e.g. Minolta CA-210) in the centre of the screen.

Consequently, the measurement needs to be done in a

dark environment.

• Adjust the correct x,y coordinates (while holding one of the

White point registers R, G or B on max. value) by means of

decreasing the value of one or two other white points to the

correct x,y coordinates (see Table 6-1 White D alignment

values). Tolerance: dx: ± 0.002, dy: ± 0.002.

• Repeat this step for the other color Temperatures that need

to be aligned.

• When finished return to the SAM root menu and press

STANDBY on the RC to store the aligned values to the

NVM.

Table 6-1 White D alignment values

If you do not have a color analyzer, you can use the default

values. This is the next best solution. The default values are

average values coming from production (statistics).

• Set the RED, GREEN and BLUE default values per

temperature according to the values in the “Tint settings”

table.

• When finished return to the SAM root menu and press

STANDBY on the RC to store the aligned values to the

NVM.

Description

Test

Point

Specifications (V)

DiagramMin. Typ. Max.

+12VS F118 11.7 12.3 12.91 B01_DC-DC

+3V3_STBY F113 3.2 3.3 3.4 B01_DC-DC

+3V3_SW F133 3.17 3.34 3.5 B01_DC-DC

+1V25_SW F131 1.18 1.25 1.31 B01_DC-DC

+5V_SW F132 4.98 5.25 5.51 B01_DC-DC

+1V8_SW F125 1.74 1.83 1.92 B01_DC-DC

+1V1_SW F101 0.94 1.1 1.15 B01_DC-DC

+5VS F235 4.94 5.2 5.46 B02A_Tuner_IF

+2V5_SW F136 2.38 2.5 2.62 B01_DC-DC

+5VTUN_DI

GITAL

F236 4.75 5 5.25 B02_Tuner_IF

VLS_15V6 FJ01 14.82 15.6 16.38 B08C_TCON DC/DC

VGH_35V FM02 34.0 35.0 36.0 B08F_MINI LVDS

VGL_-6V FJ14 -7.0 -6.0 -5.0 B08C_TCON DC/DC

VCC_3V3 FJ13 3.14 3.3 3.47 B08C_TCON DC/DC

VCC1V8 FJ05 1.71 1.8 1.89 B08C_TCON DC/DC

Picture Setting

Dynamic backlight Off

Dynamic Contrast Off

Colour Enhancement Off

Picture Format Unscaled

Light Sensor Off

Brightness 50

Colour 0

Contrast 100

Value Cool (11000 K) Normal (9000 K) Warm (6500 K)

x 0.276 0.287 0.313

y 0.282 0.296 0.329

Alignments

EN 19L11M1.1L LA 6.

2011-Apr-29

Table 6-2 Tint settings 32"

Table 6-3 Tint settings 40"

6.4 ADC gain adjustment

Use a Quantum Data Patters Generator 802BT and apply a

“PgcWrgb” image (“dot, cross and color bar mix pattern”)

according to Figure 6-1

.

Figure 6-1 “PgcWrgb” pattern

6.4.1 YPbPr

Following instructions result in correct alignment of ADC gain,

offset and phase, related to YPbPr input signal. Apply a signal

of format “1080i25”.

• Apply following signals to the YPbPr input connectors:

– Pr signal of 0.7 Vp-p

1

/ 75 ohm to the red cinch

connector.

– Y signal of 0.7 Vb-p

2

/ 75 ohm with a sync pulse of 0.3

Vp-p

1

to the green cinch connector.

– Pb signal of 0.7 Vb-p

1

/ 75 ohm to the blue cinch

connector.

• Select the input source to YPbPr input.

• In SAM, initiate the “Auto ADC” calibration command.

Upon appearance of the “Auto ADC Completed” message, the

alignment is completed.

Notes:

1. Peak-to-Peak

2. Black-to-Peak.

6.4.2 PC VGA

Following instructions result in correct alignment of ADC gain,

offset and phase, related to PC VGA input signal. Apply a

signal of format “DMT1060”.

• Apply following signals to the PC VGA input connector:

– Red signal of 0.7 Vp-p

1

/ 75 ohm.

– Green signal of 0.7 Vp-p

1

/ 75 ohm.

– Blue signal of 0.7 Vp-p

1

/ 75 ohm.

• Select the input source to PC VGA input.

• In SAM, initiate the “Auto ADC” calibration command.

Upon appearance of the “Auto ADC Completed” message, the

alignment is completed.

6.5 TCON Alignment (= VCOM alignment)

New requirement for “TCON on SSB” project:

• The purpose of VCOM alignment is to obtain an equal

voltages for both Positive and Negative LC polarity. This is

important to avoid “Flicker” and “Image Sticking”.

• The P-Gamma + VCOM calibrator IC, ISL24837 is used for

VCOM adjustment.

• The adjusted VCOM data will be stored inside on-chip

memory and will be automatically recalled during each

power-up.

ComPair (see 5.3.1 ComPair

) will foresee in a possibility to do

this alignment.

6.6 Option Settings

6.6.1 Introduction

The microprocessor communicates with a large number of I

2

C

ICs in the set. To ensure good communication and to make

digital diagnosis possible, the microprocessor has to know

which ICs to address. The presence/absence of these specific

ICs (or functions) is made known by the option codes.

Notes:

• After changing the option(s), save them with the STORE

command.

• The new option setting becomes active after the TV is

switched “off” and “on” again with the mains switch (the

EAROM is then read again).

6.6.2 How To Set Option Codes

When the NVM is replaced, all options will require resetting. To

be certain that the factory settings are reproduced exactly, you

must set all option numbers. You can find the correct option

numbers see sticker on the inside the cabinet.

How to Change Options Codes

An option code (or “option byte”) represents eight different

options (bits). All options are controlled via ten option bytes

(OP#1... OP#10).

Activate SAM and select “Options”. Now you can select the

option byte (OP#1... OP#10) with the CURSOR UP/ DOWN

keys, and enter the new 3 digit (decimal) value. For the correct

factory default settings, see the sticker inside the set.

Colour Temp. R G B

Cool t.b.d. t.b.d. t.b.d.

Normal t.b.d. t.b.d. t.b.d.

Warm t.b.d. t.b.d. t.b.d.

Colour Temp. R G B

Cool t.b.d. t.b.d. t.b.d.

Normal t.b.d. t.b.d. t.b.d.

Warm t.b.d. t.b.d. t.b.d.

18920_200_100317.eps

100317

Circuit Descriptions

EN 20 L11M1.1L LA7.

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7. Circuit Descriptions

Index of this chapter:

7.1 Introduction

7.2 Power Supply

7.3 Video

7.3.1 Video: Front-End

7.4 Audio

7.5 Inputs

7.5.1 Inputs: HDMI

7.5.2 Inputs: USB

Notes:

•Only new circuits (circuits that are not published recently)

are described.

• Figures can deviate slightly from the actual situation, due

to different set executions.

• For a good understanding of the following circuit

descriptions, please use chapter 9. Block Diagrams

and

10. Circuit Diagrams and PWB Layouts

. Where necessary,

you will find a separate drawing for clarification.

7.1 Introduction

The LC11M1.1L LA chassis is a digital chassis using a

Mediatek chipset. It covers screen sizes of 32" to 40".

The xxPFL3x06D/xx sets come with the “Thriller” styling, and

the xxPFL5x06D/xx come with the “Berlinale” styling.

Main key components are the Mediatek MT5363 integrated

“System On Chip” (SoC) that supports multimedia video/audio

input, and the integrated TCON (Timing Controller) part for the

LCD panel.

System SoC is based on MT5363:

• NAND Flash – 128 Mbyte, NumOnyx/Hynix.

• DDR – 128 Mbyte (32 × 16M, 2 pcs), Hynix.

• Use internal MT5363 Stand-by micro-controller.

Tuner/Frontend configuration:

• Half NIM tuner (VA1E1BF2403) from Sharp.

• Toshiba Channel Decoder (TC90517).

Interfaces for debug and SW upgrade:

• UART (3.5 mm jack).

• USB port.

•JTAG.

Refer to Figure 7-1

for details.

Figure 7-1 L11M1.1L LA Architecture

19130_009_110426.eps

110429

Circuit Descriptions

EN 21L11M1.1L LA 7.

2011-Apr-29

Figure 7-2 SSB cell layout

Figure 7-3 SSB key component overview

19130_010_110426.eps

110426

19130_047_110429.eps

110429

Circuit Descriptions

EN 22 L11M1.1L LA7.

2011-Apr-29

Figure 7-4 TCON key component overview

7.2 Power Supply

The Power Supply Unit (PSU) in this chassis is a buy-in and is

a black-box for Service. When defective, a new panel must be

ordered and the defective panel must be returned for repair,

unless the main fuse of the unit is broken. Always replace the

fuse with one with the correct specifications! This part is

commonly available in the regular market.

Refer to Figure 7-5

and Figure 7-6 for details

The power supply system consists of stand-by, switched and

regulated voltages. The stand-by voltage, +3V3STBY, will be

available once AC supply is provided to the system. As for the

other voltages, namely switched and regulated voltages, these

are available once the STANDBY signal is pulled “low” to allow

other supplies from the IPB to turn “on”. The switched supplies

are generated from the main +12VS supply, while the regulated

supplies are derived from the switched supplies. There are a

number of detection circuits to detect the following supplies:

+12VS, +12Vdisp and +3V3_SW. The +12VS is the main

supply voltage from the IPB that enables the switched voltages

to be generated. The +12Vdisp is the supply to the display

timing controller, while the +3V3_SW is powering the

microprocessor and its flash memory.

The mains power supply unit distribute the following voltages to

the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel

for panel with inverter (or) high voltage (HV) for inverterless

panel. Requirement of the High Voltage depend on the

specification of the LCD panel.

Figure 7-5 Power distribution overview

Figure 7-6 Power timing overview

19130_048_110429.eps

110429

19130_012_110426.eps

110426

MT5363

Dig Demod

Flash

NVM

DDR2 × 2

+12 V

S

DCDC

Regulator

Regulator

EEPROM

USB

Tuner

+3.3 V

STBY

1.1 V ±0.05 V

1.8 V ±0.09 V

3.3 V ±0.16 V 1.25 V ±0.06 V

5.25 V ±0.26 V

2.5 V

±0.12 V

5.25 V ±0.25 V

DCDC

DCDC

DCDC Regulator

18980_203_100402.eps

100402

Circuit Descriptions

EN 23L11M1.1L LA 7.

2011-Apr-29

7.3 Video

7.3.1 Video: Front-End

Key components for the tuner section are:

• Sharp Half NIM tuner VA1E1BF2403,

• Toshiba channel decoder TC90517 (external ISDB-T

channel decoder).

• Analog demodulator (using internal MT5363 analog

demodulator - pin AH35 VIP, AH37 VIN).

Refer to Figure 7-7

for details.

Figure 7-7 Front-end functional block diagram

19130_013_110426.eps

110426

Circuit Descriptions

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2011-Apr-29

7.4 Audio

In this chassis, audio processing is done by the following key

components:

• MT5363 micro-processor for input selection and audio

processing,

• TPA3123D2 class-D power amplifier for 2 x 10 W

amplification.

The audio profile (optimal setting per screen size and styling) is

stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and

profile 2 for 40-inch Dali.

Table 7-1 Microprocessor control lines - 1 -

Table 7-2 Microprocessor control lines - 2 -

Figure 7-8 Audio signal flow

7.5 Inputs

7.5.1 Inputs: HDMI

In this chassis, the main Mediatek MT5363 SoC has an on-chip

HDMI multiplexer.

Refer to Figure 7-9

for the implementation.

From uP At class D Usage

SW_MUTE SW_MUTE Will pull audio signals to LOW upon DC drops, help

to eliminate plop sound.

RESET_AUDIO A_STBY Co ntrol SHUTDOWN pin of class D amplifier:

ON/OFF the amplifier

MUTE MUTE Corresponding to the MUTE button on Remote

Control, to mute/unmute speakers

DC_PROT DC_PROT Detecting present of DC at speakers output and

feedback to uP. This will trigger TV into protection

mode. This is important to protect speakers

From uP

A_STBY

to class D Class D outputs

SW_MUTE LOW - MUTE

HIGH - Operating (unmute)

RESET_AUDIO LOW HIGH Operating (unmute)

HIGH LOW Class D shutdown (mute)

MUTE LOW - Operating (unmute)

HIGH - MUTE

DC_PROT LOW - DC detected -> set going to protection

HIGH - No DC -> normal operating

19130_014_110426.eps

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Circuit Descriptions

EN 25L11M1.1L LA 7.

2011-Apr-29

Figure 7-9 HDMI implementation

Signal description:

• TMDS: Signals that contain audio and video information.

• PWR5V: Signal to detect the presence of any HDMI source

connected to the TV’s HDMI input port.

• SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate

reading of the TV EDID data by the source device.

• I2C: The EDID data reading and the HDCP authentication

process runs via I2C.

• CEC: Signal direct connected between inputs and uP.

• EDID_WC: Signal used to disable the write protect pin of

the EEPROM. When updating, the program will temporarily

pull this pin “LOW” before writing new data.

7.5.2 Inputs: USB

In this chassis, the main Mediatek MT5363 SoC has an on-chip

USB processor.

Refer to Figure 7-10

for the implementation.

Figure 7-10 USB implementation

19130_015_110426.eps

110426

TMDS

PWR5V

SIDE_HDMI_HPD1

SIDE HDMI SCL1

HDMI SCL2

HDMI_HPD2

RX2

OPWR2_5V

ARC eHDMI+

SIDE_HDMI_SDA1

CEC

EDID

HDMI_CEC

__

_

HDMI_SDA2

7

MT5363

TMDS

PWR5V

HDMI HPD2

EDID

_

_

7

HDMI HPD1

RX1

OPWR1_5V

_

HDMI_SDA2

HDMI_SDA1

HDMI_SDA1

HDMI_SCL2

_

EDID

Buffer & Selection

circuit

ASPDIF_OUT

ARC_SW

18980_207_100402.eps

100402

IC Data Sheets

EN 26 L11M1.1L LA8.

2011-Apr-29

8. IC Data Sheets

This section shows the internal block diagrams and pin layouts

of ICs that are drawn as "black boxes" in the electrical diagrams

(with the exception of "memory" and "logic" ICs).

8.1 Diagram B0 1, Type TPS54386 (IC7116 and 7117)

Figure 8-1 Internal block diagram and pin configuration

18980_300_100402.eps

100402

PIN

CONNECTIONS

1

2

3

4

14

13

12

11

PVDD2

BOOT2

SW2

BP

PVDD1

BOOT1

SW1

GND

5

6

7

10

9

8

SEQ

ILIM2

FB2

EN1

EN2

FB1

ThermalPad

(bottom side)

HTSSOP (PWP)

(Top View)

BLOCK DIAGRAM

7FB1

+

Soft Start

1

C

COMP

+

SQ

QR

R

+

Current

Comparator

BP

f(I

DRAIN1

) + DC(ofst)

2

1

3

Anti-Cross

Conduction

1.2 MHz

Oscilator

Divide

by 2/4

Ramp

Gen 1

Ramp

Gen 2

CLK1

CLK2

BP

CLK1

Weak

Pull-Down

MOSFET

5EN1

6EN2

6A6A

VDD2

Internal

Control

10SEQ

150 k

150 k

Output

Undervoltage

Detect

BP

FB1

FB2

CLK1

4GND

8FB2

+

Soft Start

2

C

COMP

+

SQ

QR

R

+

Current

Comparator

BP

13

14

12

Anti-Cross

Conduction

BP

CLK2

Weak

Pull-Down

MOSFET

11BP

9ILIM2

150 k

150 k

BP

CLK2

4GND

Level

Select

5.25-V

Regulator

References

BOOT1

PVDD1

SW1

BOOT2

PVDD2

SW2

f(I

DRAIN2

)+DC(ofst)

0.8 V

REF

I

MAX2

(Set to one of three limits)

f(I

DRAIN1

)

f(I

MAX1

)

Overcurrent Comp

f(I

SLOPE1

)

Level

Shift

Level

Shift

f(I

DRAIN2

)

f(I

MAX2

)

f(I

SLOPE2

)

FET

Switch

TSD

PVDD2

f(I

SLOPE1

)

f(I

SLOPE2

)

SD1

SD2

UVLO

0.8 V

REF

SD2

0.8 V

REF

SD1

UDG-07124

Overcurrent Comp

R

COMP

R

COMP

IC Data Sheets

EN 27L11M1.1L LA 8.

2011-Apr-29

8.2 Diagram B01A DC-DC, Type LD1117D (IC7119)

Figure 8-2 Internal block diagram and pin configuration

F_15710_166.eps

100402

Block diagram

Pinning information

DPAK

LD1117DT

IC Data Sheets

EN 28 L11M1.1L LA8.

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8.3 Diagram B03 Class-D & muting, Type TPA3123 (IC7400)

Figure 8-3 Internal block diagram and pin configuration

18440_302_090303.eps

090318

Block diagram

Pinning information

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

PVCCL

SD

PVCCL

MUTE

LIN

RIN

BYPASS

AGND

AGND

PVCCR

VCLAMP

PVCCR

PGNDL

PGNDL

LOUT

BSL

AVCC

AVCC

GAIN0

GAIN1

BSR

ROUT

PGNDR

PGNDR

TERMINAL

I/O/P DESCRIPTION

24-PIN

NAME

(PWP)

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to

SD

2I

AVCC

RIN 6 I Audio input for right channel

LIN 5 I Audio input for left channel

GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC

GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC

Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =

MUTE 4 I

outputs enabled). TTL logic levels with compliance to AVCC

BSL 21 I/O Bootstrap I/O for left channel

PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC

LOUT 22 O Class-D 1/2-H-bridge positive output for left channel

PGNDL 23, 24 P Power ground for left-channel H-bridge

VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors

BSR 16 I/O Bootstrap I/O for right channel

ROUT 15 O Class-D 1/2-H-bridge negative output for right channel

PGNDR 13, 14 P Power ground for right-channel H-bridge.

PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC

AGND 9 P Analog ground for digital/analog cells in core

AGND 8 P Analog ground for analog cells in core

Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via

BYPASS 7 O

external capacitor sizing.

AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL

Connect to ground. Thermal pad should be soldered down on all applications to properly

Thermal pad Die pad P

secure device to printed wiring board.

1F

SD

PVCCL

PVCCR

VCLAMP

GAIN1

BYPASS

1F

1F

0.22 F

AGND

}

Control

Shutdown

Control

LIN

RIN

BSR

BSL

PGNDR

PGNDL

0.22 F

22 H

22 H

0.68 F

470 F

0.68 F

1F

470 F

GAIN0

AVCC

MUTE

ROUT

LOUT

IC Data Sheets

EN 29L11M1.1L LA 8.

2011-Apr-29

8.4 Diagram B04 MT5363 Power, Type MT5363 (IC7700)

Figure 8-4 Internal block diagram

18850_300_100107.eps

100222

Block diagram

DVB-T ATD

CVBS/

YC Input

VADCx4

TV

Decoder

HDMI

Rx

HDMI In

I/F

Audio

Demod

Audio

Input

Audio

ADC

Panel

LVDS

CVBS

VDAC

TVE

DDR

DRAM

Controller

ARM

BIM

TS

Demux

VDO-In

PreProc

MDDi

Audio In

JPEG,MPEG

H.264

2-D Graphic

Mix andPost

Processing

OSD

scaler

Vplane

scaler/PIP

Audio DSP

IO Bus

Standby uP CKGEN

Audio I/F

Audio DAC

SPDIF, I

2

S

BScan PVR RTC

UART

MS,SD PWM NAND Flash

JTAG IrDA SIF USB2.0 Watchdog Serial Flash Servo ADC

IC Data Sheets

EN 30 L11M1.1L LA8.

2011-Apr-29

Figure 8-5 Internal block diagram

18850_301_100107.eps

100222

Pinning information

LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

A

B VCC2IO

C

D RA9

E

F RA5

G

H RBA2

J

K RCKE

L

M RA13

N

P RA8

R

T RDQ19

U

V RDQM2

W

Y RDQS3

AA

AB RDQ16

AC

AD RCLK1

AE

AF VCC2IO

AG

AH GPIO44

AJ

AK JTRST_

AL

AM VCCK

AN

AP OSDA0

AR

AT POCE0_

AU

RCLK0_

VCC2IO

RA12

RA10

RBA1

RCAS_

RA11

VCC2IO

RDQ22

RDQS2_

RDQS3_

RDQ21

VCC2IO

GPIO38

JTDI

VCCK

VCCK

PDD0

POOE_

RCLK0

VCC2IO

RA7

RBA0

RWE_

RA2

RCS_

RDQ20

RDQS2

DVSS

RDQ23

RCLK1_

VCC2IO

GPIO43

JTCK

VCCK

OSCL0

POWE_

RDQ10

RDQ13

VCC2IO

RA3

DVSS

DVSS

RA0

VCC2IO

RDQ17

DVSS

RDQ29

RDQ18

VCC2IO

GPIO41

JTMS

VCCK

VCCK

PAALE

PACLE

RDQ8

RDQ5

VCC2IO

RA1

MEMTN

RA4

RRAS_

RDQ30

RDQ28

RDQ24

REXTDN

VCC2IO

GPIO37

JTDO

VCCK

VCCK

PDD1

PARB_

RDQ15

RDQS1_

RDQ2

VCC2IO

DVSS

DVSS

RODT

VCC2IO

RDQM3

DVSS

RDQ26

VCC2IO

GPIO39

GPIO42

VCCK

VCCK

POCE1_

PDD2

PDD3

RDQS1

RDQ0

RDQ7

VCC2IO

MEMTP

RA6

RVREF

RDQ25

RDQ27

RDQ31

VCC2IO

GPIO40

VCCK

VCCK

VCCK

PDD4

PDD5

RDQS0_

DVSS

DVSS

DVSS

RVREF

DVSS

VCCK

VCCK

PDD6

PDD7

RDQS0

DVSS

DVSS

DVSS

AVSS12_U

SB

AVSS33_U

SB

AVSS33_U

SB

RDQ14

RDQM1

RDQM0

DVSS

AVDD12_U

SB

USB_VRT

USB_DM

USB_DP

RDQ11

RDQ9

RDQ6

RDQ1

AVDD33_U

SB

AVDD12_H

DMI

AVSS33_U

SB

RDQ12

VCC2IO

VCC2IO

RDQ3

VCCK

HDMI_SCL

2

AVSS33_H

DMI

RX2_C

RX2_CB

VCC2IO

VCC2IO

VCC2IO

RDQ4

AVDD12_M

EMPLL

AVSS12_M

EMPLL

VCCK

VCCK

DVSS

DVSS

VCCIO33-1

AVDD33_H

DMI

RX2_0

RX2_0B

VCC2IO

VCC2IO

VCC2IO

DVSS

DVSS

VCCK

DVSS

VCCK

DVSS

VCCK

HDMI_SDA

2

HDMI_CEC

RX2_1

RX2_1B

AO0N

AO0P

AVDD33_L

VDS

AVDD33_L

VDS

DVSS

DVSS

DVSS

VCCK

DVSS

VCCK

VCCIO33-1

PWR5V_2

RX2_2

RX2_2B

AO1N

AO1P

AE0N

AE0P

AVDD12_L

VDS

VCCK

DVSS

DVSS

DVSS

DVSS

VCCK

PWR5V_1

HDMI_HPD

2

RX1_C

RX1_CB

AO2N

AO2P

AE1N

AE1P

AVSS12_L

VDS

DVSS

DVSS

DVSS

DVSS

VCCK

HDMI_SCL

1

RX1_0

RX1_0B

AOCKN

AOCKP

AE2N

AE2P

AVSS33_L

VDS

AVDD12_V

PLL

DVSS

DVSS

DVSS

DVSS

DVSS

VCCK

HDMI_HPD

1

HDMI_SDA

1

RX1_1

RX1_1B

AO3N

AO3P

AECKN

AECKP

TP_VPLL

AVSS12_V

PLL

DVSS

DVSS

DVSS

DVSS

VCCK

OPCTRL1

RX1_2

RX1_2B

AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

IC Data Sheets

EN 31L11M1.1L LA 8.

2011-Apr-29

Figure 8-6 Internal block diagram

18850_302_100107.eps

100222

Pinning information

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT

A 0DXRTE 2DXRTE 0DXTTE3OIPG 12OIPG 53OIPG N4OA

AO4P

AE3N

AE3P

DVSS

DVSS

AE4N

AE4P

GPIO36

DVSS

DVSS

GPIO32

GPIO34

GPIO33

VCCIO33

GPIO28

GPIO30

GPIO29

GPIO31

GPIO26

GPIO27

GPIO24

GPIO25

GPIO22

GPIO20

GPIO19

GPIO23

GPIO17

GPIO18

GPIO16

GPIO15

GPIO11

GPIO12

GPIO14

GPIO13

GPIO9

GPIO10

GPIO8

GPIO7

GPIO4

GPIO6

GPIO5

VCCIO33

FSRC_WR

ETTXD3

ETTXEN

ETPHYCLK

VCCIO33

AOSDATA3

IF_AGC

ETTXD1

ETTXD2

ETCOL

GPIO2

ALIN

ETRXCLK

ETTXCLK

CI_MCLKO

CI_MISTR

T

ASPDIF

RF_AGC

ETRXD3

ETTXER

CI_MIVAL

OPWM0

AOBCK

ETRXD1

ETRXER

CI_MCLKI

CI_MDI0

GPIO0

AOMCLK

ETRXDV B

ETCRS C

ETMDIO D

ETMDC E

CI_MOSTR

T

F

CI_MOVAL G

CI_MDO0 H

OPWM1 J

GPIO1 K

AOSDATA0 L

AOLRCK M

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

VCCK

DVSS

DVSS

DVSS

DVSS

DVSS

VCCK

DVSS

DVSS

DVSS

VCCK

VCCK

AVSS33_A

DAC1

OSCL2

AVDD33_A

DAC1

VCCIO33

AOSDATA4

OSDA1

AL1

OSDA2

OPWM2

AR1

TUNER_DA

TA

OSCL1

AR2

AOSDATA1

U1TX

AL2

TUNER_CL

K

U1RX

AR3

N

AOSDATA2 P

R

VCXO T

U

AL3 V

DVSS DVSS VCCK

AVDD33_R

EF_AADC

VCCIO33 VCCIO33 VCCIO33 W

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

VCCK

VCCK

VCCK

AVSS33_R

EF_AADC

VMID_AAD

C

AVDD33_A

ADC

AIN1_L_AA

AIN4_L_AA

DC

AVSS33_A

ADC

AIN4_R_A

AIN5_L_AA

DC

AIN5_R_A

ADC

AIN2_R_A

AIN6_L_AA

DC

AIN6_R_A

ADC

Y

AA

AIN3_R_A

DVSS

VCCK

DVSS

DVSS

VCCK

DVSS

DVSS

DVSS

DVSS

AVDD12_T

VDPLL

AVDD12_A

DC

AIN1_R_A

ADC

AVDD12_S

ADC

AIN0_L_AA

DC

AVDD33_

ADAC0

AIN0_R_A

ADC

AVSS33_A

DAC0

AVDD33_

ADC

AIN2_L_AA

DC

AVICM

AIN3_L_AA

DC

AR0

AVSS33_D

ADC

AB

AC

AD

AE

AL0 AF

OPWRSB

OPCTRL0

ORESET_

AVDD10_L

AVSS33_V

GA_STB

AVDD12_R

AVSS12_P

LL

AVSS33_SI

F

FS_VDAC

PLL

AVSS33_D

IG

AVDD33_S

IF

AVSS12_P

LL

AVDD33_D

IG

BYPASS0

YSPLL

ADIN0_SR

V

AVDD12_A

DCPLL

ADIN1_SR

V

AF

DEMOD1

XTALO

ADIN3_SR

V

ADCINN_D

EMOD

AV

DD

33_X

TAL_STB

ADIN2_SR

EMOD1 AG

ADCINP_D

EMOD

AH

XTALI AJ

AVSS33_X

TAL

AK

ADIN5_SR

V

AL

ADIN4_SR

OPCTRL2

OPCTRL3

OPCTRL4

U0TX

U0RX

OIRI

HSYNC

VSYNC

DO

SOG

BP

AVDD33_V

GA_STB

COM

GP

GB

SOY1

RP

AVSS12_R

GB

COM1

Y1P

PR1P

PB1P

Y0P

SOY0

PB0P

COM0

AVDD33_V

DAC

AVSS33_V

DAC

PR0P

VDAC_OUT

1

VDAC_OUT

2

AVDD33_C

VBS

AVSS33_C

VBS

SY0

SC0

MPXP

SY1

SC1

V

CVBS2P

CVBS3P

V

AM

MPXN AN

TUNER_BY

PASS

AP

CVBS0N AR

CVBS0P AT

CVBS1P AU

20 21 22 23 24 25 26 27 28 29 3

031323334353637 RB

IC Data Sheets

EN 32 L11M1.1L LA8.

2011-Apr-29

8.5 Diagram B06B Analog I/O - Audio, Type LM833 (IC7B01)

Figure 8-7 Pin configuration

18520_306_090325.eps

100402

Pinning information

2

(Top View)

1

3

4

8

7

6

5

Output 1

Inputs 1

Output 2

Inputs 2

V

EE

V

CC

1

2

IC Data Sheets

EN 33L11M1.1L LA 8.

2011-Apr-29

8.6 Diagram T01C TCON DC/DC, Type ISL97653 (IC7J00)

Figure 8-8 Internal block diagram and pin configuration

18770_307_100217.eps

100217

Block diagram

Pinning information

1

40

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

39 38 37 36 35 34 33 32 31

11 12 13 14 15 16 17 18 19 20

LDO-CTL

LDO-FB

PVIN1

AGND

PROT

LX2

LX1

PGND2

PGND1

TEMP

COMP

FBB

RSET

HVS

EN

CDEL

CTL

DRN

COM

POUT

PVIN2

CB

LXL1

LXL2

PGND3

PGND4

CM2

FBL

VL

VREF

FBN

SUPN

NOUT

PGND5

C1P

C1N

C2P

C2N

SUPP

FBP

ISL97653A

40 LD 6X6 QFN

TOP VIEW

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

(

(

CONTROL

LOGIC

SAWTOOTH

GENERATOR

CURRENT

AMPLIFIER

CURRENT LIMIT

COMPARATOR

CURRENT LIMIT

THRESHOLD

REFERENCE BIAS

AND

SEQUENCE CONTROLLER

V

REF

GM AMPLIFIER

UVLO COMPARATOR

OSCILLATOR

0.75 V

REF

REGULATOR

SUPN

0.2V

UVLO COMPARATOR

0.4V

0.75 V

REF

V

REF

P

OUT

R

SENSE

BUFFER

CONTROL

LOGIC

V

REF

SAWTOOTH

GENERATOR

SLOPE

COMPENSATION

GM AMPLIFIER

SUPP

CURRENT LIMIT

THRESHOLD

CURRENT

LIMIT

COMPARATOR

SUPP

C1- C1+ C2+ C2-P

OUT

CTL COM

BUFFER

LX1

PGND1

CB

LXL1

CM2

FBL

FBP

FBN

N

OUT

P

VIN1,2

EN

CDEL

P

VIN1,2

VL

FBB

CM1

PGND2

LX2

CURRENT AMPLIFIER

SLOPE

COMPENSATION

V

REF

FREQ

HVS

LOGIC

RSET HVS PROT

LXL2

DRN

680kHz

VL

LDO

CONTROL

LOGIC2

LDO-CTL

LDO-FB

TEMP

SENSOR

TEMP

IC Data Sheets

EN 34 L11M1.1L LA8.

2011-Apr-29

Personal Notes:

10000_012_090121.eps

090121

Block Diagrams

EN 35L11M1.1L LA 9.

2011-Apr-29

9. Block Diagrams

Wiring Diagram 32" (Thriller)

11P

1M95

9P

1M99

2P3

1308

1735

4P

1M95

11P

1M99

9P

1M99

14P

1G51

51P

1M20

8P

TO DISPLAY

3P

J1

SSB

3139 123 6505.x

(1150)

B

MAIN POWER SUPPLY

32 PSLC-P002A

(1005)

LCD DISPLAY

(1004)

8M99

8M95

WIRING DIAGRAM 32" THRILLER

19130_044_110428.eps

110429

1M99 (B01)

1. +12VDISP

2. +12VDISP

3. GND

4. GND

5. LAMP-ON

6. BACKLIGHT-PWM

7. BACKLIGHT-BOOST

8. INV_STATUS

9. POWER-OK

1M95 (B01)

1. +3V3STDBY

2. STANDBY

3. GND

4. GND

5. GND

6. +12VS

7. +12VS

8. +12VS

9. +24VAUDIO

10. GND-AUDIO

11. ...

1735 (B03)

1. LEFT_SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT_SPEAKER

1M20 (B04c)

1. LIGHT-SENSOR

2. GND

3. RC

4. LED-2

5. +3V3STBY

6. LED-1

7. KEYBOARD

8. +5V_SW

1G51 (B04D)

1. +VDISP-INT

2. +VDISP-INT

3. +VDISP-INT

4. +VDISP-INT

|

51. GND

L

N

Board Level Repair

Component Level Repair

Only For Authorized Workshop

USB

HDMI

HDMI

INLET

VGA

LOUDSPEAKER

(5213)

8M20

J2

3P

J1

8P

TO BACKLIGHT

IR/LED BOARD

(1112)

KEYBOARD CONTROL

(1114)

8G51

8308

MAINS CORD

8191

TUNER

8319

EN 36L11M1.1L LA 9.

Block Diagrams

2011-Apr-29

Wiring Diagram 40" (Thriller)

11P

1M95

9P

1M99

2P3

1308

1735

4P

1M95

11P

1M99

9P

1KA2

80P

1G51

51P

1KA1

80P

1M20

8P

TO DISPLAY TO DISPLAY

3P

J1

SSB

3139 123 6505.x

(1150)

B

TCON

(1157)

T

MAIN POWER SUPPLY

IPB 40 PLHE-P986A

(1005)

LCD DISPLAY

(1004)

8M99

8M95

WIRING DIAGRAM 40" THRILLER

19130_043_110428.eps

110429

1M99 (B01)

1. +12VDISP

2. +12VDISP

3. GND

4. GND

5. LAMP-ON

6. BACKLIGHT-PWM

7. BACKLIGHT-BOOST

8. INV_STATUS

9. POWER-OK

1M95 (B01)

1. +3V3STDBY

2. STANDBY

3. GND

4. GND

5. GND

6. +12VS

7. +12VS

8. +12VS

9. +24VAUDIO

10. GND-AUDIO

11. ...

1735 (B03)

1. LEFT_SPEAKER

2. GND-AUDIO

3. GND-AUDIO

4. RIGHT_SPEAKER

1M20 (B04c)

1. LIGHT-SENSOR

2. GND

3. RC

4. LED-2

5. +3V3STBY

6. LED-1

7. KEYBOARD

8. +5V_SW

1KA2 (T01F)

1. GND

|

11. VLS_15V6

12. VLS_15V6

|

33. VCC_3V3

34. VCC_3V3

|

78. VGH_35V

79. VGL_-6V

80. GND

1KA1 (T01F)

1. GND

|

11. VLS_15V6

12. VLS_15V6

|

33. VCC_3V3

34. VCC_3V3

|

78. VGH_35V

79. VGL_-6V

80. GND

1N01 (T01A)

1. GND

|

47. +VDISP-INT

48. +VDISP-INT

49. +VDISP-INT

50. +VDISP-INT

|

51. GND

1G51 (B04D)

1. +VDISP-INT

2. +VDISP-INT

3. +VDISP-INT

4. +VDISP-INT

|

51. GND

L

N

Board Level Repair

Component Level Repair

Only For Authorized Workshop

USB

HDMI

TUNER

PHONE

SPDIF

HDMI

HDMI

INLET

VGA

LOUDSPEAKER

(5213)

8M20

J2

3P

J1

8P

8KA1

1319

1P3

1316

1P3

HIGH VOL TAGE

TO BACKLIGHT

TO BACKLIGHT

8319

8316

IR/LED BOARD

(1112)

KEYBOARD CONTROL

(1114)

8KA2

8308

MAINS CORD

8191

1N01

51P

8G51

Block Diagrams

EN 37L11M1.1L LA 9.

2011-Apr-29

Block Diagram Video

B02A

TUNER

B02A

DIGITAL DEMOD

T01A

LVDS

DISLAY

T01B

TCON CONTROL

T01D

P GAMMA &

VCOM & NVM

T01E

MPD

T01F

MINI LVDS

B04

MT5363:

B04D

LVDS DISPLAY

B06D

VGA

B06C

ANALOG I/O - VIDEO

B06B

ANALOG I/O

AUDIO

B05B

USB

B05A

HDMI & MUX

B04B

DDR

B04C

CONTROLLER

7700

MT5363BIMG

HDMI-LVDS

B05

MAC-CI

B04C

CONTROL

B04C

AUDIO-VIDEO

B06B

MT5363

19130_020_110427.eps

110427

VIDEO

AGC_IF

CI_MCLKI

CI_MDIO

G34

H33

F35

H35

M31

M33

IF_AGC

RF_AGC_SW

+5VTUN_DIGITAL

1201

VA1E1BF2403

7302

TC90517FG

TUNER

DIGITAL

DEMODULATOR

9

IF_AGC

CI_MIVAL

RESET_DEMOD

DIF_P

10

9

58

IF_OUT+

3

RF_AGC

RF_AGC

8

+B

5208

SCL

SDA

7

6

(I2C)

4321

USB_DM

USB_DP

USB 2.0

CONNECTOR SIDE

SW UPLOAD

JPEG

MP3

AR10

AU10

USB_DP

USB_DM

AE

AO

1D01

1

2

4

3

AGC_RF

HDMI-LVDS

B05

RX1

RX2

AP19

AT19

AR16

AU16

AR18

AU18

AP17

AT17

AP15

AT15

AR12

AU12

AR14

AU14

AP13

AT13

19

1

18 2

1

1902

3

4

7

9

10

12

6

M_RX2_2

M_RX2_2B

M_RX2_1

M_RX2_1B

M_RX2_0

M_RX2_0B

M_RX2_C

M_RX2_CB

M_RX1_2

M_RX1_2B

M_RX1_1

M_RX1_1B

M_RX1_0

M_RX1_0B

M_RX1_C

M_RX1_CB

HDMI 2

CONNECTOR

1

1901

3

4

7

9

10

12

6

19

1

18 2

HDMI 1 (SIDE)

CONNECTOR

PX1

PX2

PX1

PX2

TO DISPLAY

TO DISPLAY

1KA2

72

81

61

50

13

33

34

12

11

1KA1

81

72

79

78

61

2

10

1

1

7H01

VPP1501BFG

7K00

ISL24837IRZ

VL/VH

VH

REF

VOLTAGE

GEN

7L00

ISL24016IRTZ

L

EVEL

SHIFTER

CS(1-12)

ASIC_CS

VLS_15V6

VCC_3V3

12

11

VLS_15V6

VGL_-6V

VGH_35V

2

10

INTERFACE

B08A

33

34

VCC_3V3

50

13

1KA1 1N01

60

2

1

4

3

79

78

VGL_-6V

VGH_35V

VL

VH

VL

LLV(0-7)

RLV(0-7)

7218

7217

RF_AGC_SW

CI_MISTRT

TSO_VALID

11

42

30

IF_OUT-

AGCCNTI

59

TSO_SYNC

61

TSO_CLK

60

TSO_DATA0

DRAM

B04B

CONTROL

B04C

7708

H27U1G8F2BTR

FLASH

1Gb

RDQ

RA

PDD

NAND_PDD(0-7)

A1A1

+1V8_SW

SDRAM

512Mb

7601

H5PS5162FFR

SDRAM

512Mb

7600

H5PS5162FFR

VDD

VDD

RDQ(0-31)

RDQ(0-15)

RDQ(16-31)

RA(0-13)

PB

PR

Y

1C03

CVBS

CVBS_AV3

AP35

2

CVBS_2P

1C01

SC1_B

SC1_G SY0P

SPB0P

SPR0P

AP29

AR28

7

12

9

SC1_CVBS_OUT

AU30

PR0P

Y0P

PB0P

AK22

PBR0N

PB

PR

Y

1C02

PB1P_SC2

SY1P_SC2 SY1P

SPB1P

SPR1P

SY1N

AT27

AU26

7

12

9

PR1P_SC2

AP27

PR1P

Y1P

PB1P

AR26

Y1N

SOY0-AV1

Y0P

PB0P

PR0P

Y0N

AT29

SOY0

2C06

GND_CVBS

AR36

CVBS_0N

2C07

5C05

5C02

5C01

5C00

5C04

5C03

3B08

3B11

3B07

3B09

SOY1-AV2

AP25

SOY1

3B02

3B05

3B03

3B01

3B00

CVI-2

CVI-1

AVIN

1

1E01

2

3

14

13

VGA_R

VGA_G

VGA_Rp

VGA_Gp

VGA_B

H-SYNC

V-SYNC

VGA_Bp

HSYNC

VSYNC

RP

GP

BP

1

6

10

11

5

15

VGA

CONNECTOR

AU22

AR22

AT23

AU24

AT25

RP

VSYNC

GP

BP

HSYNC

SOG

GN

AP23

SOG

AR24

COM

2E08

2E03

RXO

RXE

B04C

B04C

+VDISP-INT

49

50

60

1

47

48

+VDISP-INT

3C24

3C25

3C22

3C20

3C23

3C21

EN 38L11M1.1L LA 9.

Block Diagrams

2011-Apr-29

Block Diagram Audio

B03

CLASS-D & MUTING

B06B

ANALOG I/O - AUDIO

B06B

ANALOG I/O - AUDIO

B06C

ANALOG I/O - VIDEO

B02A

TUNER

B02B

DIGITAL DEMOD

B04

MT5363:

B05B

USB

B04B

DDR

B04C

CONTROLLER

B05A

HDMI & MUX

1B02

2

ALI_ADAC

B06B

ALI_DAC

B06B

MT5363

19130_038_110427.eps

110427

AUDIO

1B01

2

3

1

K33

ASPDIF

E28

ASPDIF

SPDIF_OUT

eHDMI+

ASPDIF_OUT

ARC_SW

DVI_AUL_IN

DVI_AUR_IN

1C02

AC36

AB37

AD33

AIN_AADC_0_L

AC34

AIN_AADC_0_R

AB31

AIN_AADC_1_L

AC32

AIN_AADC_1_R

AV IN

AUDIO

L/R

AV IN

AUDIO

L/R

AV IN

AUDIO

L/R

SPDIF

OUT

AA36

Y37

AIN_AADC_6_L

AIN_AADC_6_R

SAV_L_IN

SAV_R_IN

1C03

AV IN

AUDIO

L/R

5

8

5

3

1C01

5

3

V37

u36

AL_L

AR_R

AOUTL

AOUTR

PREAMPL

PREAMPR

LEFT_SPEAKER

GND-AUDIO

RIGHT_SPEAKER

7400

TPA3123D2PWP

CLASS D

POWER

AMPLIFIER

5

6

2

6

1

7

22

15

MUTE

4

1

2

1735

3

4

DC-DETECTION

SW_MUTE

RESET_AUDIO

A_STBY

2

B04C

B04C

B04C

DC_PROT

B04C

7408

STANDBY

AIN_AADC_3_L

AIN_AADC_3_R

AIN0_R-AV1

AIN0_L-AV1

AIN1_R-AV2

AIN1_L-AV2

AVIN

CVI-2

CVI-1

SPEAKER

LEFT

SPEAKER

RIGHT

7700

MT5363BHMG

MAC-CI

B04C

CONTROL

B04C

AGC_IF

CI_MCLKI

CI_MDIO

G34

H33

F35

H35

M31

M33

IF_AGC

RF_AGC_SW

+5VTUN_DIG

1201

VA1E1BF2403

7302

TC90517FG

TUNER

DIGITAL

DEMODULATOR

9

IF_AGC

CI_MIVAL

DIF_N

DIF_P

10

9

58

IF_OUT+

3

RF_AGC

RF_AGC

8

+B

5207

SCL

SDA

7

6

(I2C)

AGC_RF

7218

7217

RF_AGC_SW

CI_MISTRT

TSO_VALID

11

29

30

IF_OUT-

AGCCNTI

59

TSO_SYNC

61

TSO_CLK

60

TSO_DATA0

B04C

4321

USB_DM

USB_DP

USB 2.0

CONNECTOR SIDE

SW UPLOAD

JPEG

MP3

AR10

AU10

USB_DP

USB_DM

1D01

1

2

4

3

DRAM

B04B

CONTROL

B04C

7708

H27U1G8F2BTR

FLASH

1Gb

RDQ

RA

PDD

NAND_PDD(0-7)

A1A1

+1V8_SW

SDRAM

512Mb

7601

H5PS5162FFR

SDRAM

512Mb

7600

H5PS5162FFR

VDD

VDD

RDQ(0-31)

RDQ(0-15)

RDQ(16-31)

RA(0-13)

HDMI

B05

GPIO

B05

RX0

RX1

AP19

AT19

AR16

AU16

AR18

AU18

AP17

AT17

AP15

AT15

AR12

AU12

AR14

AU14

AP13

AT13

19

1

18 2

1

1902

3

4

7

9

10

12

6

M_RX2_2

M_RX2_2B

M_RX2_1

M_RX2_1B

M_RX2_0

M_RX2_0B

M_RX2_C

M_RX2_CB

M_RX1_2

M_RX1_2B

M_RX1_1

M_RX1_1B

M_RX1_0

M_RX1_0B

M_RX1_C

M_RX1_CB

HDMI 2

CONNECTOR

1

1901

3

4

7

9

10

12

6

19

1

18 2

HDMI 1 (SIDE)

CONNECTOR

14

7B01

RESET_DEMOD

42

B04C

2

1

4

5

3

8

7S09

74LVC00

&

+3V3

GPIO_12

Block Diagrams

EN 39L11M1.1L LA 9.

2011-Apr-29

Block Diagram Control & Clock Signals

CONTROL + CLOCK SIGNALS

B06D

USB

B04C

CONTROLLER

B04B

DDR

T01B

TCON CONTROL

T01D

P GAMMA & VCOM & NVM

B04

MT5363

B04C

FLASH & EJTAG & DISPLAY INTERFACE

T01E

MPD

CONTROL

B04C

DRAM

B04B

GPIO

B04C

TO IR/LED PANEL

AND

KEYBOARD CONTROL

+3V3STBY

3

2

4

5

7

1M20

MT5363

7700

MT5363BIMG

OPWRSB

AT21

AP21

UART

SERVICE

CONNECTOR

1701

3

2

1

B01

STANDBY

U0_RX

U0_TX

AG6

GPIO_42

GPIO_26

GPIO_21

PDD

H29

RCLK1#

RCLK1

AD3

AD1

EDID_WC

B06 B07E

A22

LCD-PWR-ONn

B04C

AH3

LAMP-ON

B01A

DC_PROT

B03

B29

GPIO_9

RF_AGC_SW

B02A

B23

GPIO_32

BYPASS_MODE

B08C

G30

B25

A26

GPIO_5

USB_PWR_EN

B06D

E30

GPIO_6

USB_OCP

B06D

A30

GPIO_3

AN22

OIRI

RESET_DEMOD

B02B

AM35

ADIN_SRV_2

ORESET

KEYBOARD

RC

1

AL36

ADIN_SRV_5

LIGHT-SENSOR

HDMI_CEC

AN14

AL20

HDMI_CEC

B05A

OPCTRL_4

AU20

MUTE

B03

OPCTRL_3

AR20

SW_MUTE

B03

B04C

B04C

OPCTRL_0

AM21

POWER_DOWN

B04C

LED-2

2701

SDM

2700

PANEL

4321

USB_DM0

ADIN_SRV_4

AM37

USB_DM0

AJ5

USB_DP0

AK5

USB_DP0

USB 2.0

CONNECTOR

SIDE

1D01

3

4

2

1

USB_PWR_EN

7D00

TPS2041BD

USB_OCP

EN

OUT

OC

19130_045_110428.eps

110429

7710

CLK

CLK

J8J8 K8K8

TCK

RCLK0#

RCLK0

A2

B3

CLK

CLK

XTAL1

XTALO

1700

54M

AJ34

AJ36

RDQ

RA

SDRAM

512Mb

7601

H5PS5162FFR

SDRAM

512Mb

7H00

H5PS5162FFR

TCON

CONTROL

7H01

VPP1501BFG

SDRAM

512Mb

7600

H5PS5162FFR

TDQ(0-15)

RDQ(0-15)

RDQ(16-31)

RA(0-13)

TA(0-12)

7708

H27U1G8F2BTR

FLASH

1Gb

NAND_PDD(0-7)

GPIO_7

E28

ARC_SW

B06B

GPIO_12

GPIO_35

GPIO_43

AG4

GPIO_41

POWER-OK

B01A

+3V3STBY

AL22

ORESET

7701

BD45292G

VOUT

VDD

5

4

3

OSC_IN

OSC_OUT

SLOPE

CS

1H00

27M

B1

A1

L2

L1

T9

RST

RESET

T01D

U9

T16

RTC50_60

50Hz_60Hz

T01D

T01C

T01F

T01F

T01F

GSLOP

TCK#

P

GAMMA

7K00

ISL24837IRZ

OUT12

24

T01E

T01F

T01F

T01F

CS_L

OUT12

26

INCOM

OUTCOM

25

OUTCOM

VCOM

VH

VL

LLV(0-7)

RLV(0-7)

VCOM

BUFER

7L00

SL24016IRTZ

L

EVEL

SHIFTER

CS(1-12)

ASIC_CS

RDQ(0-31)

EN 40L11M1.1L LA 9.

Block Diagrams

2011-Apr-29

Block Diagram I

2

C

I²C

DIGITAL DEMOD

B2B

LVDS DISPLAY

T01A

TCON CONTROL

T01B

P GAMMA & VCOM & NVM

T01D

VGA

B06D

TUNER

B02A

HDMI & MUX

B05A

CONTROLLER

B04C

CONTROLLER

B04C

DDR

B4B

1KQA

DEBUG ONLY

RES

RES

7700

MT5363BIMG

OSDA_0

OSCL_0

GPIO_44

CONTROL

AH1 7

AP3

AP1

AP21

AT21

SYS_EEPROM_WE

SDA-MAIN

SCL-MAIN

3718

3719

+3V3_SW

TUNER_DATA

TUNER_CLK

19130_011_110426.eps

110426

56

7702

M24C64

EEPROM

(NVM)

3717

3716

N34

N36

3727

3728

3746

3747

+3V3STBY

3746

3747

+3V3STBY

UART

SERVICE

CONNECTOR

3749

3748

1701

3

2

1

B04C

ERR

15

7703

1

6

10

11

5

15

VGA

CONNECTOR

SDA_VGA

SCL_VGA

1E01

12

15

3E21

3E22

DC_5V

3K40

3K41

VCC_3V3

3K54

3K53

VCC

56

7E00

M24C02

EEPROM

4E03

4E02

4818

4817

7

EDID_WC

7E01

B04C

MT5363

1

2

1KQB

2

1

ROM_SDA

ROM_SCL

U8 T8

46 45

7302

TC90517FG

DIGITAL

DEMODULATOR

3352

3351

FE_SDA

FE_SCL

76

1201

VA1E1BF2403

MAIN

TUNER

ERR

16

3228

3230

TUNER_SDA

TUNER_SCL

12

14

7H01

VPP1501BFG

TCON

CONTROL

56

7K04

M24C64

EEPROM

12 13

7K00

ISL24837IRZ

VOLT AGE

GENERATOR

78

7

7801

PCA9540BDP

I2C

SWITCH

HDMI 2

CONNECTOR

HDMI 1 (SIDE)

CONNECTOR

1901

16

15

TO

TCON

TO

SSB

1G51

50

49

3907

3908

AL14

AL12

1902

16

15

3915

3916

HDMI_PLUGPWR2

HDMI_PLUGPWR2

AN18

AM17

SIDE_HDMI_SDA1

SIDE_HDMI_SCL1

HDMI_SDA2

HDMI_SCL2

HDMI_SCL2

HDMI_SCL1

HDMI_SDA2

HDMI_SDA1

7900

M24C02

EEPROM

7901

M24C02

EEPROM

4

3

WP_TCON

RESET

MAIN NVM

SW

Programmable via USB

SW

SW

Programmable via ComPair

EDID

SW

EDID

SW

EDID

SW

3K56

3K55

7708

H27U1G8F2BTR

FLASH

1Gb

PDD

U0_RX

U0_TX

NAND

SDRAM

512Mb

7601

H5PS5162FFR

SDRAM

512Mb

7600

H5PS5162FFR

RDQ(0-31)

RA(0-13)

DRAM

B04B

RDQ

RA

56 56

4816

4814

SDA_VCOM

SCL_VCOM

SDA_VGA

SCL_VGA

SDA-TCON

SCL-TCON

1N01

2

3

4

BYPASS_MODE

B08A

B04C

Block Diagrams

EN 41L11M1.1L LA 9.

2011-Apr-29

Supply Lines Overview

SUPPLY LINES OVERVIEW

MAIN

POWER

SUPPLY

B01

DC - DC

T01B

TCON CONTROL

B04C

CONTROLLER

B06A

ANOLOG I/O - HEADPHONE

B04A

MTK POWER

B04B

DDR

B05A

HDMI & MUX

B05B

USB

T01A

LVDS DISPLAY

B06D

VGA

B04D

LVDS DISPLAY

T01E

MPD

T01F

MINI LVDS

B02A

TUNER

B02B

DIGITAL Demod

B03

CLASS-D & MUTING

T01C

TCON DC/DC

B06B

ANALOG I/O - AUDIO

T01D

P GAMMA & VCOM & NVM

1M99

11

66

77

88

1M95

+3V3STBY

19130_005_110426.eps

110426

B04d

B03,B04c,B06b

B03,B04a,c,d,

B05a

B02b,B04a,c,d,

B06a,B06b

B02a

B02a,B03.B04c,

B06d,B05a,b

B02b

B02b,B04a

B04a,b

B04a

B03

1M99

11

66

77

22

33

44

55

88

LAMP-ON

1M99

BACKLIGHT-BOOST

INV_STATUS

+12VDISP

BACKLIGHT-PWM

B04C

B04C

+12VS

99

GND-AUDIO

10 10

+3V3_SW

+1V1_SW

EN_1

+24VAUDIO

CONTROL

CONTROL

B04C

CONTROL

B06D

CONTROL

99

POWER-OK

22

33

44

55

STANDBY

B04A

CONTROL

11 11

7122

RT8283AHGSP

Synchronous

Step-down

Converter

N.C.

5117

PWR5V_2

+3V3STBY+3V3STBY

1902

18

HDMI 2

CONNECTOR

B01

+5V_SW+5V_SW

HDMI_PLUGPWR1

B01

5121

32

32

+1V8_SW

7124

RT8283AHGSP

Synchronous

Step-down

Converter

7125

RT8283AHGSP

5115 5123

32

7123

RT8283AHGSP

32

VCC_3V3VCC_3V3

T01c

VCC_1V8VCC_1V8

T01c

VDD3V3IO

5H03

VDD3V3LVRS

5H02

VGH_35VVGH_35V

T01c

5H04

5H06

DDR2VDD

5H05

+1V1_SW+1V1_SW

+1V25_SW+1V25_SW

B01

+3V3_SW+3V3_SW

B01

+3V3_SW+3V3_SW

B01

+3V3_SW+3V3_SW

B01

+3V3STBY+3V3STBY

B01

+3V3STBY+3V3STBY

B01

+3V3STBY+3V3STBY

B01

+3V3_SW+3V3_SW

B01

B01

B01

+1V8_SW+1V8_SW

SENCE+1V1_MT5363

B01

+1V8_SW+1V8_SW

1M20

8

5

TO

IR/LED

PAN E L

+12VS+12VS

B01

+5V_SW+5V_SW

B01

+5V_SW

+5V5_TUN

5120

6122

6102

+2V5_SW

B04a

SENSE_1V8SENSE_1V8

B04a

SENSE+1V1_MT5363SENSE+1V0_MT5363

+5V_SW+5V_SW

B01

+VDISP-INT

+5V_SW+5V_SW

B01

B01

SENCE_1V8

B01

PWR5V_1

1901

18

HDMI 1 SIDE

CONNECTOR

HDMI_PLUGPWR2

VDD1V8PLL

1N01

+VDISP+VDISP

T01c

VREF_15V2VREF_15V2

T01d

VLS_15V6VLS_15V6

T01c

T01d,e

T01b,d,f

T01f,d

T01b,f

T01f

T01c

VGH_35VVGH_35V

T01c

+VDISP-INT

+12VDISP+12VDISP

7802

LCD-PWR-ONn

7800

B01

5800

5706

5801

5802

VCC_3V3VCC_3V3

T01c

VGL_-6VVGL_-6V

B08c

B01

+5V_SW+5V_SW

+5V5_TUN+5V5_TUN

B01

+5VTUN_DIGITAL

+1V25_SW+1V25_SW

+3V3_SW+3V3_SW

B01

B01

+3V3STBY+3V3STBY

+5V_SW+5V_SW

B01

+12VS+12VS

B01

+24VAUDIO+24VAUDIO

B01

B01

+VDISP

VLS_15V6_B

VLS_15V6

+VDISP-INT+VDISP-INT

7J00

ISL97653

10

21

T01a

5J06

7J01

VGL_-6V

3J10

3J26

VGH_35V

3,4

VCC_3V3

5J00

T01b

39

VCC_1V8

6J02

4J02

4J01

4J04

LCD

SUPPLY

5105 5106

5225

+5VS

7216

IN OUT

COM

B01

+2V5_SW

+2V5_SW

5222

6900

6901

DC_5V

1E01

9

VGA

CONNECTOR

5H01

VDD1V8

5H00

3J12

3E13

+12VS+12VS

+3V3_SW

+3V3-ARC

+3V3_SW

B01

B01

32

VREF_15V2

7K00

ISL24837IRZ

VOLTAGE

GENERA-

TOR

+VDISP+VDISP

T01c

T01e

VCC_3V3VCC_3V3

T01c

VLS_15V6VLS_15V6

T01c

Synchronous

Step-down

Converter

5104

Synchronous

Step-down

Converter

7120

IN OUT

COM

+1V25_SW

7120

IN OUT

COM

3130

6E05

5E03

50

48

47

49

1G51

4

2

1

3

TO 1N01

TCON

T01A

TO 1G51

SSB

B04D

EN 42L11M1.1L LA 10.

Circuit Diagrams and PWB Layouts

2011-Apr-29

10. Circuit Diagrams and PWB Layouts

10-1 B01 393912365052

DC-DC

19130_016_110426.eps

110426

DC-DC

B01A B01A

2011-01-31

2

2011-01-13

1

3139 123 6505

PCB SB SSB

THRILLER BRZ DIG

COM

OUTIN

GND

GND HS

VIN

EN

SS

VIA

BOOT

SW

FB

COMP

GND

GND HS

VIN

EN

SS

VIA

BOOT

SW

FB

COMP

GND

GND HS

VIN

EN

SS

VIA

BOOT

SW

FB

COMP

COM

OUTIN

GND

GND HS

VIN

EN

SS

VIA

BOOT

SW

FB

COMP

8

ROUND 4.50mm SCREW HOLE

0V

ROUND 4.02mm SCREW HOLE

12V/1V0 CONVERSION

12V/1V8 CONVERSION

2

PIN

12V/3V3 CONVERSION

3V3/1V2 CONVERSION

12V

0V

7

1

1.5V

25V

0V

3V3

12V/5V CONVERSION

1M99

PIN

>1.5V

ON

12V

6

0V

STBY

0V

0V

6

SLOT SCREW HOLE

3V

0V9

7

1M95

12V

3V3

0V

3V

1

3V5

9

0V

ON

12V

5V/2V5 CONVERSION

STBY

0V

I136

2189

10u

10n

2197

22u

2151

33R

5105

22u

2138

22n

2158

10u

2163

RES

1%

3112

15K

RES

100n

2187

100n

2111

GND-AUDIO

100n

2110

F123

F125

I106

SS1_GND

I107

100n

2108

I108

3131

4K7

3130

1K0

LD1117DT25

7120

1

32

SS3_GND

68R

5127

33R

3129

2142

100n

F122

RES

4100

F135

3113

68K 1%

RES

SS2_GND

F118

5%

100K

3146

33R

5120

470p

2186

RES

6122

SS36

3125

1%

5K1

22u

2130

2157

22n

BZX384-C6V8

6102

2125

100n

2140

SS1_GND

16V

2176

22u 6.3V

100n

10u

100n

2123

2177

1X02

REF EMC HOLE

1X01

REF EMC HOLE

F116

2159

6.3V

100u

SS4_GND

2170

100n

100K

3100

I134

+1V1_SW

2146

2u2

2147

100n

15K

3116

100p2127

3127

RES

470p

68R

+2V5_SW

2113

22u

2152

I127

I118

+24VAUDIO

10u

2172

100p2134

F132

3115

1%27K

I110

3u6

5123

5124

33R

6

7

5

4

9

8

3

10

2

7124

RT8283AHGSP

1

3153

470R

33R

5115

10u

2169

100n

2148

SS4_GND

5128

33R

2102

10u

I105

16V10u

2168

F105

7119

LD1117DT

1

32

I123

F108

F109

I112

100n

2126

I109

2195

22n

5

4

9

8

3

10

2

+12VS

RT8283AHGSP

1

6

7

I138

7122

3105

1%

1R0

100K

5125

33R

3151

1n0

2137

RES

SS1_GND

SS3_GND

2185

3n3

RES

2180

1n0

3126

68R

100n

2143

RES

6.3V

5

4

9

8

3

10

2

2101

100u

RT8283AHGSP

1

6

7

F106

7125

2154

10u 16V

GND-AUDIO

SS3_GND

10u

2171

10R

3138

RES

I122

RES

3u6

5106

SS1_GND

I139

1R0

3150

2107

22u

6.3V

RES

10R

3155

470R

RES

3111

6

7

8

9

470R

3154

1M95

1

10

11

2

3

4

5

1n0

2141

1-2041145-1

RES

F121

16V10u

2188

2149

100n

2105

6.3V100u

RES

RES

22u

2155

22u

2166

2161

22u

5%

DGND

F120

470K

3148

10n

2122

I144

I111

1n0

2136

2199

10u

F136

+5V_SW

SS1_GND

EN_1

F131

3140

4K7 1%

I137

2191

22u

+5V_SW

SS4_GND

F114

+3V3STBY

10u

2164

1n0

2144

100n

SENSE+1V1_MT5363

DGND

2139

I142

DGND DGND

470p

I140

RES

2150

F107

SS3_GND

F117

3K6

3145

3106

12K

100n

1%

SS2_GND

SENSE_1V8

2124

2178

100n

EN_1

10u

EN_1

F101

2175

4n7

2167

2

3

4

5

6

7

8

9

2041145-9

1M99

1

2135 10n

I113

5117

33R

SS3_GND

3135

12K

SS1_GND

1R0

3152

6.3V

2106

+5V5_TUN

100u

DGND

I126

I135

100p2132

100p2131

3107

1K5

1%

I120

2100

10u

100K

3101

100K

3102

2192

RES

470p

2179

100n

3128 68R

EN_1

2181

10u

+1V8_SW

GND-AUDIO

I141

F113

F103

2145

1n0

DGND

1%

12K

3118

22u

2165

I125

+1V25_SW

SS3_GND

2129

+3V3_SW

100K

22u

3103

1X04

EMC HOLE

3149

1R0

I132

I143

F102

2153

10u

27K 1%

I117

SS4_GND

3109

I119

2112

4n7

I131

2133 100p

2128 100p

5

4

9

8

3

10

2

RT8283AHGSP

1

6

7

5121

10u

7123

F119

F115

SS2_GND

GND-AUDIO

F133

SS2_GND

3n3

2160

12K

3114

22u

2162

RES

2198

10n

3108

10R

SS4_GND

16V

47u

2109

+3V3_SW

F104

+12VDISP

SS2_GND

22n

2190

+12VS

I104

2193

22u

RES

3136

10R

1X05

REF EMC HOLEREF EMC HOLE

1X03

10u

5104

2183

22u

SS2_GND

10K

3122

47K

3117

22u

2104

RES

+12VS

POWER-OK

STANDBY

BACKLIGHT-PWM

LAMP-ON

BACKLIGHT-BOOST

INV_STATUS

Circuit Diagrams and PWB Layouts

EN 43L11M1.1L LA 10.

2011-Apr-29

10-2 B02 393912365052

Tuner

19130_017_110426.eps

110426

Tuner

B02A B02A

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

COM

OUTIN

MT MT

0R

Near Tuner

Near MTK5363

330n

AGND

220n

5230

5228

AGND

47n

2293

KTK5132E

7218

AGND

F246

F208

AGND AGND

3270

10K

13

2278

1u0

7216

LD29150DT50R

2

2294

47u

AGND

AGND

AGND

AGND

F207

F204

F206

A214

15p

2225

A213

100p

2262

RES

2258 100n

2295

F213

100p

18

10R3271-1

I222

I221

3261

NC2

3

RF_AGC

6

SCL

7

SDA

10K

10

IF_OUT+

11

IF_OUT-

IF_OUT_ANALOG

12

13

14 15

16

NC1

2

4

+B

8

1

ANT_PWR

5

AS

9

IF_AGC

F236

1201

VA1E1BF2403

TUNER

2288

33p

75R

3263

75R

3262

F203

3265

1K0

10R

3228

2286

180p

+5VTUN_DIGITAL

22u

RES

2213

A225

AGND

AGND

AGND

2226

100n

2282

15p

RES

10u

2279

7217

BC847BW

2280

10n

5222

10u

RES

RES

2277

22u

AGND

AGND

5225

10R

3230

+5V5_TUN

AGND

2281

22u

+5VTUN_DIGITAL

F201

RES

F242

+5VS

RES

27

8

3272-2

10R

3272-1 10R

RES

1

2289

AGND

10n

F209

2285

27p

4210

RES

2287

10n

F202

22u

2296

RES

3264

A212

10K

220n

5229

180p

2291

AGND

AGND

+5VS+5V_SW

AGND

2263

47n

3269

1K0

I255

AGND

AGND

F247

I254

27p

2290

AGND

3272-4

10R

RES

45

3272-3

10R

RES

36

30R

I220

RES 5207

RES

RES

4209

45

1n0

2297

36

10R

3271-4

27

10R

3271-3

+5VTUN_DIGITAL

10R

3271-2

5208 4u7

F235

2283

22u

10n

2284

F205

5226

220n

5227

220n

RF_AGC_SW

DIF_P

DIF_N

VIN_ATV

VIP_ATV

RF_AGC_EX

DIF_N

DIF_P

FE_SDA

FE_SCL

IF_AGC

RF_AGC

EN 44L11M1.1L LA 10.

Circuit Diagrams and PWB Layouts

2011-Apr-29

Digital demodulator

19130_018_110426.eps

110426

Digital demodulator

B02B B02B

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

X

XSEL

ADI_AI

ADQ_AI

AD_VREF

TSMD

TN

SLADRS

VSS

DR2VDD

DR1VDD

VDDS

AD_DVDD

AD_AVDD

PLLVDD

VDDC

PBVAL

RERR

RLOCK

RSEORF

SBYTE

SLOCK

SRCK

SRDT

STSFLG1

AGCCNTI

AGCCNTR

STSFLG0

SYRSTN

0

1

SCL

SDA

FIL

AD_AVSS

AD_DVSS

PLLVSS

I

O

0

1

P

N

P

N

P

N

AD_VREF

DTCLK

DTMB

S_INFO

0

1

AGCI

CKI

SCL

SDA

25.4M

FOR DEVELOPMENT USE

DGND

AGND

AGND

+1V25_SW

+2V5_SW

+3V3_SW

F301

4311

DGND

4310

AGND

DGND

AGND

3360

4K7

33R3354

+2V5_SW

1u0

2305

33R3359

F306

DGND

3344

2K7

AGND

I303

I338

1u0

2313

F303

2337 100n

F300

DGND

1u0

I320

2340

3357 33R

3351 100R

4306

1n52335

18p

2334

+3V3_SW

DGND

100n

2302

DGNDDGND

DGND

DGND

+3V3_SW

I318

37

44

47

50

57

62

19

18

3

2

36

56

63

13

35

49

64

4

15

33

61

60

51

38

42

8

12

14

1

41

1617

53

54

55

59

45

46

6

5

52

7

11

34

48

43

39

40

21

58

20

28

2223

32

31

26

25

24

9

10

7302

TC90517FG

)

29

30

27

2317

100n

5304

30R

DGND

I325

2339 1u0

I308

4308

DGND

100n

2304

DGND

10K

3335

DGND

3349 10K

2K7

3343

2321

100n

10n

2322

AGND

2332

100n

2320

1u0

100n2338

3339 20K

1u0

2316

30R

5306

1u0

2318

AGND

I304

5302

30R

5307

30R

+1V25_SW

DGND

39p

2379

RES

+3V3_SW

I316

I306

I302

2307

100n

2308

2309

100n

100n

F302

3332

2K7

DGND

+3V3_SW

10K

3336

2377

100n

I307

RES

RES

2380

39p

4K7

3350

4307

4309

DGND

AGND

DGND

DGND

DGND

10K3337

AGND

2303

100n

33R

5311

100n

AGND

2323

100n

2378

100n

2324

100n2336

2301

100n

2341

100n

RES

30R

5301

100n

2312

30R

5305

4312

4313

DEB

SML-310

6301

5310

DGND

33R

33R

5309

DGND

I305

2314

1u0

3358 33R

7301

DEB

100n

2306

BC847BW

18p

2333

DNGADNGA

DGND

4

13

I301

1301

2

I300

2310

1u0

2K7

3331

DGND

I317

AGND AGND

DGND

DGND

30R

5303

DEB

3356

1K0

AGND

3353 33R

3352 100R

RES

DGND

1K0

DEB

5308

1n2

AGND

DGND

3355

2311

AGND

100n

4314

AGND

DIF_N

RESET_DEMOD

IF_AGC

DIF_P

TUNER_SCL

TUNER_SDA

TSO_CLK

TSO_DATA0

TSO_SYNC

TSO_VALID

FE_SDA

FE_SCL

Circuit Diagrams and PWB Layouts

EN 45L11M1.1L LA 10.

2011-Apr-29

10-3 B03 393912365052

Class-D & muting

19130_019_110427.eps

110427

Class-D & muting

B03 B03

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

VIA VIA

VIA

VIA

VCLAMP

MUTE

IN

BSL

SD

R

AVCC

L

BSR

GND_HS

L

PGND

AGND L R

L

OUT

R

BYPASS

1

R

0

PVCC

GAIN

GND SND

RESERVED

LEFT +

RIGHT -

DC-DETECTION

GND SND

GND-AUDIO

I401

I413

F400

I416

100K

RES

3405-4 4 5

3414

I422

22K

1K0

3418

+5V_SW

3422-3

100K

RES

1R0

3415

2406

47n

F413

I433

1K0

3428

1u02409

3

2

I403

7403

BC847BW

1

7402-2

5

3

4

BC857BS(COL)

5401

220R

2420

10n

I437

2432

1u0

RES

2431

3427

1K0

4n7

2407

47n

2433

1u0

3408

RES

47K

1K0

3412

2423

100n

+24VAUDIO

+24VAUDIO

I412

GND-AUDIO

220n

2413

31

32

33

34

I423

26

35

36

37

38

39

40

27

28

29

30

VIA

7400-2

TPA3123D2PWP

2400

220n

220R

5400

7406

2SD2653K

3430

47K

RES

183406-1 22K

BC857BS(COL)

7402-1

2

61

GND-AUDIO

GND-AUDIO

GND-AUDIO

3439

10K

I441

10K

3433

RES

I434

3405-2 22K27

RES

3416

100K

I417

F411

1K0

RES

I418

3432

F415

I431

10u2426

220n

2411

F414

GND-AUDIO

I415

10u

2405

35V

3426

I442

47K

2422

2418

220n

470u 16V

1403

V_NOM

2408 1u0

+12VS

RES

1K8

3413

3434

47K

22u

5402

35V

I432

2415

220u

I405

F412

F409

7 22K2

+3V3STBY

3406-2

GND-AUDIO

2412

220n

2419

10n

GND-AUDIO

BC847BW

F410

7408

2425

RES

BAS316

4n7

15

2

11

6401

23

24

13

14

1

3

10

12

6

19

20

21

16

7

18

17

25

5

22

4

7400-1

TPA3123D2PWP

CLASS-D

)

AUDIO AMP

8

9

F405

GND-AUDIO

F402

F404

1402

V_NOM

F417

F416

3437

3K0

220u

I443

2401

35V

2404

220n

220n

2414

220n

6402

2417

BAT54C

I445

GND-AUDIO

36

GND-AUDIO

18

3405-3 22K

3405-1 22K

3410

4401

4K7

4K7

3411

22u

5403

100K

3422-2

GND-AUDIO

3438

22K

GND-AUDIO

1K0

+12VS

3454

GND-AUDIO

2421

10n

I424

1K0

3435

RES

RES

I430

2SD2653K

7412

7413

2SD2653K

RES

F401

4R7

3400

3406-3 3 6

+3V3STBY

22K

100K

I406

3422-1

I435

3451

1K0

I425

3431

47K

RES

BAT54C

6403

10K

3417

I411

1

3

2

BC857BW

7404

1u0

2427

I436

2SD2653K

7407

2402

220n

35V220u

2403

F406

47K

3421

1K0

3453

1K0

3452

1

2

BSS84

7405

3

22K3406-4 4 5

6400

BAS316

RES

2424

4n7

RES

BC847BW

7414

2416

220u35V

I414

I440

1

2

3

4

2041145-4

1735

4n7

2430

RES

10K

3419

47K

3420

56K

RES

I429

3409

100K

3422-4

F408

7411

BC857BW

RES

1

3

2

LEFT_SPEAKER

LEFT_SPEAKER

RIGHT_SPEAKER

A_STBY

RIGHT_SPEAKER

HP_ROUT

SW_MUTE

AOUTR

HP_LOUT

AOUTL

AOUTR

AOUTL

MUTE

RESET_AUDIO

A_STBY

DC_PROT

EN 46L11M1.1L LA 10.

Circuit Diagrams and PWB Layouts

2011-Apr-29

10-4 B04 393912365052

MT5363 Power

19130_021_110427.eps

110427

MT5363 Power

B04A B04A

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

AVSS33

AVSS12AVDD12

AVDD33

CVBS

DEMOD1

DIG

HDMI

LVDS

REF_AADC

SIF

USB_1

USB_2

USB_3

VDAC

VGA_STB

XTAL

LVDS

MEMPLL

PLL_1

PLL_2

RGB

USB

VPLL

AADC

ADAC0

ADAC1

USB

VPLL

AADC

ADAC0

ADAC1

CVBS

DEMOD1

DIG

HDMI

LVDS_1

LVDS_2

REF_AADC

SIF

USB

VDAC

VGA_STB

XTAL_STB

AVDD10_LDO

ADCPLL

APLL

HDMI

LVDS

MEMPLL

RGB

SYSPLL

TVDPLL

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

DVSS

VCCK

VCCK

VCC2IO

VCCK

VCCK

VCCK

VCCK

VCCK

VCC2IO

VCCIO33-1

VCC2IO

VCCIO33

VCC2IO

VCC2IO

100n2521

2508 100n

100n2509

2549 100n

30R5503

2514

4u7

1u0

2597

100n2558

30R

5501

100n2515

2532

100n

2542

100n2531

100n

100n2519

100n2544

100n2540

2550

4u7

2536 100n

4u7

2500100n2533

2570

100n

2524 100n

4u7

2588

100n2580

I505

2565 100n

100n2517

+3V3_SW

30R5502

2538 100n

+3V3_SW

100n2584

1u02592

30R5504

4u7

2598

2507

22u

100n

100n2562

2503

SENSE_1V8

100n2535

5505 30R

F503

100n2523

F500

100n

4u7

2579

2582

+1V8_SW

F501

2504 100n

2520

I507

2522 100n

100n

5500

30R

J18

Y29

AK29

AP9

AT9

AT11

AR30

AL24

AK37

AN26

AM9

P19

Y33

AE34

U30

AR32

AG36

AJ30

AN12

H15

W30

AL30

AM11

AN30

AN24

AK35

P17

T13

AH29

AH31

AF29

AL10

N18

Y31

AF33

T31

AN32

AG34

AK31

AM13

F15

7700-7

MT5363BIMG

AM23

AH33

AG30

AP11

N16

P13

AM25

AG32

100n

POWER-MISC

2561

2543

100n

2541

100n

+3V3STBY

2534 100n

100n2577

2574

100n2527

100n

100n2553

2545 100n

100n2566

2559 100n

3500

1R0

2595

2530 100n

10u

100n2529

5506

30R

1u02571

100n2573

2516 100n

100n

100n2537

2581

2528 100n

100n2564

2552 100n

2599

1u0

100n2593

Y13

Y15

AA14

AD15

AD17

AD19

N22

V13

N24

T25

V25

W24

Y25

AA24

AB25

AE20

AE22

U14

AL4

AL6

AL8

AM1

AM3

AM5

AM7

AN2

AN4

R16

AE14

AE16

AE18

AG12

AH7

AJ6

AJ8

AK5

AK7

AL2

E12

E14

AF13

AF15

H23

H31

J30

V31

W32

W34

W36

AD7

AE2

AE4

AF1

AF3

C2

C12

D3

D13

E4

F13

G6

G14

H7

J14

R2

R4

R6

AC6

B13

AD5

AC22

AC24

AD21

AD23

AD25

AE24

J6

L4

B1

F5

V23

W20

W22

Y21

Y23

AA20

AA22

AB21

AB23

AC20

J4

P25

R20

R22

R24

T21

T23

U20

U22

U24

V21

G10

AE8

AF9

B21

D21

E22

G22

N20

P21

P23

G8

AA16

AA18

AB13

AB15

AB17

AB19

AC14

AC16

AC18

F9

AD13

V17

V19

W4

W6

W14

W16

W18

Y3

Y17

E8

Y19

P15

R14

R18

T15

T17

T19

U16

U18

D9

V15

7700-8

MT5363BIMG

POWER-MAIN

C8

L6

N14

I506

I504

2506 100n

2576 100n

2501 100n

2510 100n

2513 100n

2502 100n

+1V25_SW

2567

4u7

2526 100n

100n2525

I502

100n2512

100n2575

100n2560

100n2505

100n

2569

2568 100n

+3V3STBY

2518 100n

F502

2596 100n

+1V1_SW

SENSE+1V1_MT5363

2563 100n

2551

100u 6.3V

Circuit Diagrams and PWB Layouts

EN 47L11M1.1L LA 10.

2011-Apr-29

DDR

19130_022_110427.eps

110427

DDR

B04B B04B

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

RDQS0

RDQS1

RDQS2

RDQS3

RDQM

RDQ

RA

RBA

RVREF

11

12

13

0

1

2

RCLK0

RRAS

RCLK1

RCAS

RCKE

REXTDN

RODT

RCS

RWE

19

20

21

22

23

24

25

26

27

28

29

30

31

0

1

2

3

1

2

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

12

11

10

9

8

7

6

5

4

3

0

1

2

3

4

5

6

7

8

9

10

11

12

CK

VDDL

VREF

VSSDL

14

VDDQ

QSSVSSV

BA

A

LDQS

UDQS

NC

DQ

CKE

WE

ODT

RAS

1

CS

CAS

0

0

1

2

VDD

LDM

UDM

15

13

12

11

10

9

8

7

6

5

4

3

0

1

2

3

4

5

6

7

8

9

10

11

12

CK

VDDL

VREF

VSSDL

14

VDDQ

QSSVSSV

BA

A

LDQS

UDQS

NC

DQ

CKE

WE

ODT

RAS

1

CS

CAS

0

0

1

2

VDD

LDM

UDM

15

13

22R

3612

1%

3621

56R3603-3

1K0 1%

3620

1K0 1%

56R

AB5

N6

P5

N8

P7

K3

3600-2

C10

V1

U6

B9

A8

B7

C6

V3

W2

Y1

AA2

AA4

G12

T5

Y7

H13

D5

F11

F7

B5

D11

E10

E6

T3

AC2

U2

AB3

Y5

T7

AA6

V7

V5

H11

A4

B11

A12

C4

A10

A6

AB1

U4

AC4

T1

J2

H1

L2

K1

B3

A2

AD1

AD3

P3

D7

E2

M1

M3

G4

M5

F1

M7

F3

P1

D1

H3

7700-3

MT5363BIMG

DRAM

N4

H5

G2

N2

3603-2

56R

56R

100n

2609

3610-1

F600

3619

100R

1%22R

3618

2629

100n

1%1K0

3615

3606-2

56R

56R

3608-1

56R

3611-4

56R

3611-2

3610-3 56R

3609-2

56R

3600-1 56R

100n

2600

56R

3602-3

3606-4

56R

22R 1%

3613

100n2620

56R3606-1

3610-2 56R

56R

3607-1

100n

2603

100n

2601

56R

3609-4

56R3611-1

100n

2630

56R

3608-4

1K0

3616

56R3600-4

1%

2625 100n

1K0

3623

1%

100n2624

3605-2 56R

K3

3602-4

56R

J7

A7

H8

B2

B8

D2

D8

E7

F2

F8

H2

E9

G1

G3

G7

J2

A3

E3

J3

N1

P9

E1

J9

M9

R1

J1

A9

G9

C1

C3

C7

C9

R3

R7

R8

K9

K7

B3

B7

A8

A1

H9

F1

F9

C8

C2

F3

F7

E8

A2

E2

L1

G2

D7

D3

D1

D9

B1

B9

H7

H3

H1

P2

P8

P3

L2

L3

L7

J8

K2

K8

L8

G8

M8

M3

M2

P7

R2

M7

N2

N8

N3

N7

)

SDRAM

H5PS5162FFR-G7C

7601

3601-4

56R

3606-3

56R

3602-2

56R

100n

2607

2606

100n

2623 100n

100n2622

2605

100n

100n

2604

56R3605-1

3603-1 56R

+1V8_SW

3604-1

56R

56R3601-2

2627 100n

100n2626

56R

3609-1

100R

3614

3601-3

56R

3607-3

F601

56R

56R

3607-4

3600-3

56R

1%1K0

3622

F602

3609-3

56R

56R3602-1

3607-2 56R

2608

47u 16V

56R

+1V8_SW

3610-4

56R

3604-4

3611-3 56R

1%

2621 100n

3617

22R

16V47u

2628

3603-4 56R

3605-3 56R

56R3605-4

3604-2

3601-1

56R

56R

3624

100R

3604-3 56R

3608-3

56R

3608-2 56R

2602

100n

+1V8_SW

+1V8_SW

D2

D8

E7

F2

F8

H2

K3

J2

A3

E3

J3

N1

P9

J7

A7

H8

B2

B8

A9

G9

C1

C3

C7

C9

E9

G1

G3

G7

K7

B3

B7

A8

A1

E1

J9

M9

R1

J1

F7

E8

A2

E2

L1

R3

R7

R8

K9

B1

B9

H7

H3

H1

H9

F1

F9

C8

C2

F3

L7

J8

K2

K8

L8

G8

G2

D7

D3

D1

D9

M7

N2

N8

N3

N7

P2

P8

P3

L2

L3

7600

H5PS5162FFR-G7C

SDRAM

M8

M3

M2

P7

R2

)

+1V8_SW

RCS#

RDQ(12)

RDQ(11)

RDQ(10)

RDQ(9)

RDQ(8)

RDQ(7)

RA(2)

RA(6)

RRAS#

RDQ(5)

RDQ(14)

RDQ(13)

RDQS(0)

RDQ(4)

RDQ(3)

RDQ(2)

RDQ(1)

RDQ(0)

RDQ(6)

RA(10)

RDQ(15)

RDQM(1)

RDQM(0)

RDQS(1)#

RDQS(1)

RDQS(0)#

RA(1)

RA(11)

RA(7)

RA(0)

RA(4)

RDQM(2)

RCAS#

RWE#

RODT

RCKE

RCLK1#

RCLK1

RCLK0#

RA(9)

RCLK0

RBA(1)

RBA(0)

RA(13)

RA(12)

RA(8)

RA(5)

RA(3)

RDQS(3)#

RDQS(3)

RDQS(2)#

RDQS(2)

RDQM(3)

RDQ(24)

RDQ(23)

RDQ(22)

RDQ(21)

RDQ(20)

RDQ(19)

RDQ(18)

RDQ(17)

RDQ(16)

RBA(2)

RDQ(31)

RDQ(30)

RDQ(29)

RDQ(28)

RDQ(27)

RDQ(26)

RDQ(25)

RDQ(25)

RDQ(26)

RDQ(27)

RDQ(28)

RDQ(29)

RDQ(30)

RDQ(31)

RA(0)

RA(1)

RA(2)

RA(3)

RA(4)

RA(5)

RA(6)

RA(7)

RA(8)

RA(9)

RA(10)

RA(11)

RA(12)

RCAS#

RBA(2)

RA(13)

RBA(0)

RBA(1)

RCKE

RWE#

RCS#

RODT

RRAS#

RA(8)

RA(9)

RA(10)

RA(11)

RA(12)

RA(13)

RBA(1)

RBA(2)

RDQ(1)

RDQ(2)

RDQ(3)

RDQ(4)

RDQ(5)

RDQ(6)

RDQ(7)

RDQ(8)

RDQ(9)

RDQ(10)

RDQ(11)

RDQ(12)

RDQ(13)

RDQ(14)

RDQ(15)

RDQ(16)

RDQ(17)

RDQ(18)

RDQ(19)

RDQ(20)

RDQ(21)

RDQ(22)

RDQ(23)

RDQ(24)

RA(0)

RBA(0)

RCAS#

RCKE

RCLK0

RCLK0#

RCLK1

RCLK1#

RCS#

RDQM(0)

RDQS(0)

RODT

RRAS#

RWE#

RDQ(0)

RDQS(1)

RDQS(0)#

RDQS(2)

RDQS(3)

RDQS(1)#

RDQS(2)#

RDQS(3)#

RDQM(1)

RDQM(2)

RDQM(3)

RA(1)

RA(2)

RA(3)

RA(4)

RA(5)

RA(6)

RA(7)

EN 48L11M1.1L LA 10.

Circuit Diagrams and PWB Layouts

2011-Apr-29

Controller

19130_023_110427.eps

110427

Controller

B04C B04C

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

CLE

7

6

5

4

3

2

1

0

VCC

R

SE

WP

WE

RE

CE_

ALE

NC

IO

B

VSS

ETRXETTX

CICI

D0

D1

D2

D3

ER

EN

CLK

ETMDC

ETMDIO

MCLKO

MDO0

MOVAL

MOSTRT MISTRT

D0

D1

D2

D3

DV

ER

CLK

ETPHYCLK

ETCOL

ETCRS

MCLKI

MDI0

MIVAL

GPIO GPIO

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

18

19

20

21

22

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SUB

ER

GND

VOUT

VDD

SCL

ADR

0

1

2SDA

WC

PDD

USB

ADIN_SRV

OSDA

OSCL

TUNER

OPCTRL

OPWM

U0

RX

TX

U1

POCE

HDMI

AGC

DEMOD

CLK

DATA

BYPASS

BYPASS0

ADCINP

ADCINN

IF

RF

3

4

5

6

7

0

1

PARB

PAALE

PACLE

POWE

POOE

RX

TX

PWR5V

SCL2

0

1

2

OIRI

0

1

2

3

4

OPWRSB

CEC

SDA1

SCL1

SDA2

0

1

2

ORESET

FSRC_WR

MEMTN

MEMTP

TP_VPLL

JTCK

JTDO

JTRST

JTDI

JTMS

0

1

2

0

1

2

0

1

2

3

4

5

DP

DM

VRT

XTALI

XTALO

VCXO

0

ONLY

0

AOSDATA0

RES

AOBCK

XTAL 54MHZ

UART (SERVICE)

RES FOR ITV

OPCTRL3(0)

OPWM1

AOLRCK ASPDIF

PDWNC Normal

SDM

0

10

TRAP2

0

1

0

PANEL

ICE mode +ROM mode

PWM DIMMING

FOR DEBUGGING

TRAP1

TRAP0

ICE mode + Serial Boot

0

I713

3741

1K0

3730

10K

RES

+3V3STBY

3781

4700

100R

+3V3STBY

+3V3STBY

+3V3_SW

I757

+3V3STBY

F758

10K

3729

3717 22R

BC847BW

7703

3754

4K7

F757

+3V3_SW

3721 4K7

2723

RES

1n0

F706

I750

I753

+3V3_SW

+3V3_SW

10p

2717

10p

2703

F746

2709

4u7

2716

10p

RES

2711

100n

3768

6K8

1K0

F743

3798

I744

F705

I727

3732

100R

10K

2

6

1

3733

7709-1

BC847BS(COL)

3711

4K7

100R

RES

3794

I756

10p

2729

RES

I741

F756

3770

1K0

DEB

10K

3759

I754

4K7

3702

3777 4K7

10R

3795

37A6

RES

10K

15

8

7

6

12

37

13

36

18

19

40

45

46

47

48

3

4

5

10

11

14

25

26

27

28

33

2

34

35

38

39

41

42

43

44

1

20

21

22

23

24

17

9

16

29

30

31

32

+3V3_SW

7708

H27U1G8F2B

100R

3744

10K

RES

37A7

3705

F759

100R

3704 100R

2720

47n

F765

30R

RES

5706

+3V3_SW

100K

3790

3712

33R

30R

5701

100n

2730

10K

2710

3763-4

DEB

4u7

4K7

+3V3_SW

3756

BZX384-C6V8

6700

+3V3_SW

10K3778

100n

2727

100R

3709

+3V3STBY

3748 33R

1700

54M

F741

I731

I716

F721

I745

10K

3700

3785 10K

+3V3STBY

I725

10n

RES 2705

BZX384-C3V3

6708

RES

E32

B31

D31

E34

B33

A36

B35

A34

C34

B37

D35

D33

A32

C32

H37

H33

G34

F37

G36

G32

C36

E36

D37

F31

7700-6

MT5363BIMG

MAC-CI

F35F33

H35

6701

BZX384-C6V8

G30

E30

H29

F29

B29

A22

C22

AF5

AG2

AE6

C30

AF7

AG4

AG6

AH3

AH1

H25

B25

D25

C24

G24

A30

E24

J24

B23

F23

D23

H27

F27

B27

D27

G26

J32

E26

A26

C26

J26

F25

K35

K37

D29

C28

E28

J28

G28

1706

7700-4

MT5363BIMG

GPIO

100n

2713

3751 100R

6709

BZX384-C8V2

3791

100R

+3V3_SW

4K73719

3710

4K7

4708

RES

I737

BC847BW

7710

3763-2 10K

DEB

RES

1K0

3743

3745

4K7

1u0

1705

2706

9

12

13

37AA

4K7

1

10

11

2

3

4

5

6

7

8

DEB

1702

502382-1170

3716

+3V3_SW

+3V3_SW

+3V3_SW

22R

100R3787

F747

2722

1n0

I738

100R

RES

10K3763-3

3788

DEB

F718

I747

F719

I755

+3V3_SW

10K3715

I714

4K7

I761

3784

RES

3720

10K

10K

3761

4K7

F748

3746

3753

4K7

2701RES

100n

4

F701

+3V3_SW

Φ

1

3

2

5

I715

BD45292G

7701

2

1

3

MSJ-035-29D PPO

1701

4K7

3749 33R

3747

I760

10K

3757

2704

RES

RES

10p

37A9

10K

3726

RES

4K7

F766

3737 100R

F738

3703

10K

7705

3701

BC847BW

4

5

6

7

8

10K

2041145-8

1M20

1

2

3

RES

+3V3_SW

10K

3731

3742

680R

2700 100n

RES

F704

F716

3735 100R

100R3734

3739

1R0

100R3727

100R3796

F740

3771

1K0

10K

3760

DEB

I726

3706

4K7

I735

4K73783

1

2

3

6

5

84

7

(8K × 8)

)

EEPROM

7702

M24C64-WDW6

37A5

4K7

F724

7709-2

5

3

4

220R

BC847BS(COL)

+5V_SW

5705

3765

33R

DEB

10K3758

F750

+3V3_SW

I739

4K7

3736

10K

3780

DEB

RES

3779

4K7

+3V3STBY

F742

F753

F760

I759

F763

100n

2728

100K

I746

3769

F754

2726

100n

3793

RES

4707

I733

100R

I743

F739

220n

2721

AP21

R36

T35

AR10

AU10

AN10

T37

AJ36

AJ34

AN6

AU2

AT3

AL16

AM15

M33

M19

AP37

N36

N34

AT21

AU4

AT5

AR2

AP5

AR6

AU6

AP7

AT7

AR8

AU8

AT1

T33

AL20

AL22

AP3

R34

P31

AP1

R32

P33

AR4

K5

K7

AN22

AM21

AM19

AN20

AR20

AU20

J34

J36

AN14

AM17

AL12

AN18

AL14

M31

AK3

AJ2

AH5

AJ4

AK1

MT5363BIMG

AH35

AH37

AL32

AK33

AM35

AL34

AM37

AL36

AM31

L30

CONTROL

7700-1

100R3728

6707

BAS316

I734

F755

+3V3_SW

+3V3_SW

I711

F702

F737

DEB

10K3763-1

10K

3713

F707

F751

I700

2702 100n

+3V3_SW

F745

I758

I732

3792

2K2

100R

+3V3_SW

37A8

I749

100n

2712

F749

30R

5700

F761

2724

1n0

2719

47n

F717

RES

3775 4K7

4K73774

1%

3789

RES

5K1

100R3738

3764

1K0

3714 10K

+5V_SW

F708

3724

1R0

I708

I701

+3V3STBY

+3V3STBY

10K

37AB

RES

F725

3762

1K0

DEB

3767

15K

3718 4K7

I742

3707

4K7

3786

10K

10K

3782

10K

RES

3722

10K3723

RES

10K

3740

6706

BAS316

3776

4K7

F736

+3V3STBY

+3V3_SW

+3V3_SW

RES

+12VS

1n0

2725

F744

LIGHT-SENSOR

RESET_AUDIO

RC

NAND_PDD(0)

NAND_PARB

NAND_POCE

NAND_POWE

NAND_PALE

NAND_PCLE

SCL-DISP

SDA-DISP

TUNER_SDA

TUNER_SCL

RF_AGC_SW

NAND_POOE

NAND_PDD(7)

NAND_PDD(6)

NAND_PDD(5)

NAND_PDD(4)

NAND_PDD(3)

NAND_PDD(2)

NAND_PDD(1)

ARC_SW

INV_STATUS

BYPASS_MODE

RESET_DEMOD

VIN_ATV

VIP_ATV

IF_AGC

RF_AGC

BACKLIGHT-PWM

LAMP-ON

STANDBY

BACKLIGHT-BOOST

POWER-OK

POWER_DOWN

JTMS

MUTE

DC_PROT

SW_MUTE

SDA-MAIN

SCL-MAIN

NAND_POCE

SYS_EEPROM_WE

LED-2

BOOST_CONTROL

POWER_DOWN

KEYBOARD

JTDO

JTDO

LIGHT-SENSOR

LED-1

ORESET

JTDI

LED-1

KEYBOARD

JTCK

JTRST

SDA-LCD

PWR5V_1

HDMI_CEC

BACKLIGHT_CONTROL

USB_OCP

USB_PWR_EN

SCL-LCD

USB_DM

USB_DP

PWR5V_2

SIDE_HDMI_SCL1

SIDE_HDMI_SDA1

HDMI_SCL2

HDMI_SDA2

NAND_POWE

NAND_PARB

NAND_POOE

LED-2

JTRST

VCOM_SW

RC

EDID_WC

LCD-PWR-ONn

SDA-MAIN

SCL-MAIN

NAND_PALE

NAND_PCLE

TSO_CLK

TSO_DATA0

TSO_SYNC

TSO_VALID

JTMS

JTDI

JTCK

NAND_PDD(0)

NAND_PDD(1)

NAND_PDD(2)

NAND_PDD(3)

NAND_PDD(4)

NAND_PDD(5)

NAND_PDD(6)

NAND_PDD(7)

Circuit Diagrams and PWB Layouts

EN 49L11M1.1L LA 10.

2011-Apr-29

LVDS Display

19130_024_110427.eps

110427

LVDS Display

B04D B04D

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

-BUS

CTRL

FIL

I

2

C

INP

-

Y

-

Y

Y

PCA5940

Y

Y

-

-

PCA9515 - (RES)

4820

-

4822

4821

-

Y

4817

4818

4810

-

4816

4814 Y

LVDS#1

-

Y

Y

4811

-

4819

-

-

4813

Y

4815

4812

Y

-

Y

Y

-

33R

5800

3803

F801

47R

+3V3STBY

F805

4816

100n

2805

61

53

54 55

56 57

58 59

60

48

49

5

50

51

6

7

8

9

52

39

4

40

41

42

43

44

45

46

47

28

29

3

30

31

32

33

34

35

36

37

38

19

2

20

21

22

23

24

25

26

27

1

10

11

12

13

14

15

16

17

18

FI-RNE51SZ-HF-R1500

1G51

3805

47K

F800

4801

RES

I801

5801

33R

RES

RES

4815

4813

4823

RES

F813

F812

4800

RES

4804

RES

4820

I809

4805

I800

F808

4817

+5V_SW

RES

4822

4810

RES

4811

4824

4814

RES

4818

6

7

8

4

1

2

3

SI4835DDY

5

100u 16V

7800

2804

15K

3806

7803

3807

10K

BC857BW

F823

F821

4812RES

F814

4821

RES

1u0

2806

1K0

3810

I808

I807

10K

3808

7802-2

5

3

4

BC847BS(COL)

33R

5802

F809

2

6

1

BC847BS(COL)

7802-1

+VDISP-INT

+VDISP-INT

F833

F827

F815

F825

F834

F832

F811

I802

4806

RES

I806

220n

2807

BZX384-C6V8

6800

F831

F829

F828

47K

4803

3802

4808

RES

F810

+12VDISP

+3V3_SW

F807

F806

F822

4802

RES

4807

RES

F820

F819

F817

F824

F826

10n2803

RES

2802

100n

1K0

3809

VSS

6

F818

SC0 5

8SC1

SCL 40DS1

SD1 7SDA2

VDD

3

PCA9540B

7801

F816

4819

SCL-DISP

SDA-DISP

SDA-VCOM

LCD-PWR-ONn

SDA_VGA

VCOM_SW

SCL-VCOM

BYPASS_MODE

SCL_VGA

PX2A-

PX2A+

PX2C-

PX2C+

PX2B-

PX2B+

PX2E-

PX2E+

PX2D-

PX2D+

PX2CLK-

PX2CLK+

PX1D+

PX1D-

PX1CLK+

PX1B-

PX1A+

PX1A-

PX1E+

PX1E-

PX1CLK-

PX1C+

PX1C-

PX1B+

EN 50L11M1.1L LA 10.

Circuit Diagrams and PWB Layouts

2011-Apr-29

10-5 B05 393912365052

HDMI & Multiplexer

19130_025_110427.eps

110427

HDMI & Multiplexer

B05A B05A

2011-01-31

2

2011-01-13

1

3139 123 6505

PCBSBSSB

THRILLER BRZ DIG

SCL

ADR

0

1

2SDA

WC

SCL

ADR

0

1

2SDA

WC

AE

0P

0N

1P

1N

2P

2N

3P

3N

4P

4N

CKP

CKN

AO

RX1

0

0B

1

1B

2

2B

C

CB

RX2

0B

1

1B

2

2B

C

CB

HDMI_HPD1

HDMI_HPD2

3N

4P

4N

CKP

CKN

0P

0N

1P

1N

2P

2N

3P

0

H : WRITE

HDMI PORT 2 (SIDE)

L : WP

HDMI PORT 1

F906

F913

F907

4900

F904

HDMI_PLUGPWR2

4902

45

6916

3

8

67 910

21

IP4281CZ10

RES

F912

HDMI_PLUGPWR2

PWR5V_2

10K

3904

7900

1

2

3

6

5

84

7

EEPROM

)

(256 × 8)

M24C02-WMN6

10K

3901

F902

3913

100K

2902

10p

F903

HDMI_PLUGPWR1

+3V3STBY

4903

RES

+3V3STBY

3906

27K

4901

HDMI_PLUGPWR1

RES

3924

68K

DEB

HDMI_PLUGPWR1

MMBT3904

7903

+5V_SW

F905

I906

MMBT3904

7902

3K3

F900

3916

3907

3K3

F901

3K3

100K

3920

3908

HDMI_PLUGPWR1

8

67 910

21

45

IP4281CZ10

RES

6913

3

4904

PWR5V_1

5900 30R

I905

+5V_SW

3900

10K

7907

MMBT3904

RES

3K3

3915

I916

1K0

F911

3912

2900

100n

F915

F914

68K

3923

DEB

I902

F909

F908

HDMI_PLUGPWR2

BSH111

7908

RES

9

20 21

22 23

6902

RB521S-30

16

17

18

19

2

3

4

5

6

7

8

1

10

11

12

13

14

15

84

7

47266-9002

1902

7901

M24C02-WMN6

1

2

3

6

5

(256 × 8)

)

EEPROM

3905

4K7

8

67 910

21

45

RES

IP4281CZ10

6915

3

RES

3914

4K7

CDS2C05HDMI2

5.6V

910

21

45

RES

6917

IP4281CZ10

6914

3

8

67

I915

RES

100n

2901

AU12

AP19

AT19

AR16

AU16

AP13

AT13

AR14

AU14

AP15

AT15

AR12 D19

A20

C20

A18

C18

AL18

AN16

AP17

AT17

AR18

AU18

H21

F19

H19

B15

D15

A16

C16

B17

D17

B19

E16

G16

F17

H17

E18

G18

E20

G20

F21

7700-5

MT5363BIMG

HDMI-LVDS

10K

3903

4K7

3902

1K0

3919

7905

RES

MMBT3904

4K7

3921

RES

HDMI_PLUGPWR2

6901

BAT54C

12

3

12

3

BAT54C

6900

5.6V

7

8

9

20 21

22 23

CDS2C05HDMI2

6903

15

16

17

18

19

2

3

4

5

6

1

10

11

12

13

14

PX1D-

M_RX1_1

M_RX2_C

1901

47266-9002

PX2D+

PX2E+

PX2E-

PX2CLK+

PX2CLK-

PX2D-

M_RX2_C

M_RX2_CB

PX2A-

PX2B+

PX2B-

PX2C+

PX2C-

HDMI_HPD2

M_RX1_0

M_RX1_0B

M_RX1_1

M_RX1_1B

M_RX1_2

M_RX1_2B

M_RX1_C

M_RX1_CB

M_RX2_0

M_RX2_0B

M_RX2_1

M_RX2_1B

M_RX2_2

M_RX2_2B

PX1C-

PX1C+

PX1B-

PX1B+

PX1A-

PX1A+

PX2A+

SIDE_HDMI_HPD1

PX1CLK-

PX1CLK+

PX1E-

PX1E+

PX1D+

PWR5V_2

SIDE_HDMI_SCL1

SIDE_HDMI_SDA1

HDMI_SCL2

HDMI_SDA2

HDMI_CEC

PWR5V_1

HDMI_CEC_A

HDMI_HPD2

EDID_WC

EDID_WC

M_RX2_2B

M_RX2_2

M_RX2_2

M_RX2_1B

M_RX2_1B

M_RX2_1

M_RX2_1

M_RX2_0B

M_RX2_0B

M_RX2_0

M_RX2_0

eHDMI+

SIDE_HDMI_HPD1

M_RX1_CB

M_RX1_C

M_RX1_C

M_RX1_2B

M_RX1_2B

M_RX1_2 M_RX1_1B

M_RX1_1B M_RX1_1

M_RX1_0B

M_RX1_0B

M_RX1_0

M_RX1_0

M_RX2_CB

M_RX2_CB M_RX2_C

M_RX2_2B

HDMI_CEC_A

ARC_eHDMI+

SIDE_HDMI_SCL1

SIDE_HDMI_SDA1

HDMI_SCL2

HDMI_SDA2

M_RX1_CB

M_RX1_2

M_RX1_2

M_RX1_2B

M_RX1_CB

M_RX1_C

M_RX1_0B

M_RX1_0

M_RX1_1B

M_RX1_1

M_RX2_2

M_RX2_2B

M_RX2_CB

M_RX2_C

M_RX2_0B

M_RX2_0

M_RX2_1B

M_RX2_1

HDMI_CEC_A