PDM41024
128K x 8-Bit
High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
Low power operation (typical)
-PDM41024SA Active: 450 mW Standby: 50 mW
-PDM41024LA Active: 400 mW Standby: 25mW
Single +5V (±10%) power supply TTL-compatible inputs and outputs Packages
Plastic SOJ (300 mil) - TSO Plastic SOJ (400 mil) - SO Plastic TSOP (I)- T
The PDM41024 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is accomplished when the write enable (WE) and the chip enable (CE1) inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE and CE2 remain HIGH and CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41024 comes in two versions: the standard power version (SA) and the low power version (LA). The two versions are functionally the same and differ only in their power consumption.
The PDM41024 is available in a 32-pin plastic TSOP (I), and a 300-mil and 400-mil plastic SOJ.
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A 0 |
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Decoder |
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Memory |
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Addresses |
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Matrix |
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I/O0 |
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Data |
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Control |
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CE1 |
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CE2 |
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Control |
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Rev. 3.3 - 4/09/98 |
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PDM41024
Pin Configuration |
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TSOP (I) |
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SOJ |
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Vcc |
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A11 |
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A9 |
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A10 |
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A16 |
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A8 |
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CE1 |
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CE2 |
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I/O7 |
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A12 |
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WE |
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I/O6 |
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CE2 |
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I/O5 |
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A7 |
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A15 |
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I/O4 |
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A6 |
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A8 |
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Vcc |
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I/O3 |
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A5 |
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A9 |
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Vss |
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A4 |
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A11 |
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A16 |
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I/O2 |
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I/O1 |
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A3 |
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OE |
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A12 |
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I/O0 |
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A2 |
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A10 |
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A0 |
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A1 |
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CE1 |
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A1 |
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A0 |
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I/O7 |
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A5 |
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A2 |
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I/O6 |
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A4 |
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A3 |
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I/O0 |
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I/O1 |
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I/O5 |
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Pin Description |
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I/O2 |
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I/O4 |
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Vss |
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I/O3 |
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Name |
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Description |
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Truth Table(1) |
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A16-A0 |
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Address Inputs |
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I/O7-I/O0 |
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Data Inputs/Outputs |
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OE |
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WE |
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CE1 |
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CE2 |
I/O |
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MODE |
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Output Enable Input |
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X |
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X |
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H |
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X |
Hi-Z |
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Standby |
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OE |
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Write Enable Input |
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X |
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X |
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X |
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L |
Hi-Z |
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Standby |
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WE |
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CE2 |
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Chip Enable Inputs |
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L |
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H |
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L |
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H |
DOUT |
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Read |
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CE1, |
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NC |
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No Connect |
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X |
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L |
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L |
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H |
DIN |
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Write |
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VCC |
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Power (+5V) |
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H |
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H |
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L |
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H |
Hi-Z |
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Output Disable |
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VSS |
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Ground |
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NOTE: 1. H = V |
IH |
, L = V |
IL |
, X = DON’T CARE |
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Absolute Maximum Ratings (1) |
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Symbol |
Rating |
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Com’l. |
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Ind. |
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Unit |
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VTERM |
Terminal Voltage with Respect to VSS |
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–0.5 to +7.0 |
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–0.5 to +7.0 |
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TBIAS |
Temperature Under Bias |
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–55 to +125 |
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–65 to +135 |
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°C |
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TSTG |
Storage Temperature |
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–55 to +125 |
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–65 to +150 |
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°C |
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PT |
Power Dissipation |
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1.0 |
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1.0 |
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W |
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IOUT |
DC Output Current |
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50 |
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50 |
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mA |
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Tj |
Maximum Junction Temperature (2) |
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125 |
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145 |
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°C |
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NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja values:
SOJ: 72o C/W
TSOP: 95o C/W
2 |
4/09/98 - Rev. 3.3 |
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PDM41024 |
Recommended DC Operating Condition |
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Symbol |
Parameter |
Min. |
Typ. |
Max. |
Unit |
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VCC |
Supply Voltage |
4.5 |
5.0 |
5.5 |
V |
VSS |
Supply Voltage |
0 |
0 |
0 |
V |
Industrial |
Ambient Temperature |
–40 |
25 |
85 |
°C |
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Commercial |
Ambient Temperature |
0 |
25 |
70 |
°C |
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DC Electrical Characteristics (VCC = 5.0V ± 10%)
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PDM41024SA |
PDM41024LA |
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Symbol |
Parameter |
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Test Conditions |
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Min. |
Max. |
Min. |
Max. |
Unit |
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ILI |
Input Leakage Current |
VCC = MAX., VIN = VSS to VCC |
Com’l/ |
–5 |
5 |
–1 |
1 |
A |
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Ind. |
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ILO |
Output Leakage Current |
VCC = MAX., |
Com’l/ |
–5 |
5 |
–1 |
1 |
A |
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CE1 |
= VIH and CE2 = VIL, |
Ind. |
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VOUT = VSS to VCC |
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VIL |
Input Low Voltage |
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–0.5(1) |
0.8 |
–0.5(1) |
0.8 |
V |
VIH |
Input High Voltage |
|
|
|
|
2.2 |
6.0 |
2.2 |
6.0 |
V |
VOL |
Output Low Voltage |
IOL = 8 mA, VCC = Min. |
|
— |
0.4 |
— |
0.4 |
V |
||
|
|
|
IOL = 10 mA, VCC = Min. |
|
— |
0.5 |
— |
0.5 |
V |
|
VOH |
Output High Voltage |
IOH = –4 mA, VCC = Min. |
|
2.4 |
— |
2.4 |
— |
V |
NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns
Power Supply Characteristics
|
|
|
|
|
|
|
-10 |
-12 |
|
-15 |
|
||
Symbol |
|
Parameter |
Power |
Com’l. |
Com’l. |
|
Ind. |
Com’l. |
|
Ind. |
|||
ICC |
|
Operating Current |
SA |
250 |
230 |
|
240 |
185 |
|
195 |
|||
|
|
CE1 |
|
= VIL and CE2 = VIH |
|
|
|
|
|
|
|
|
|
|
|
f = fMAX = 1/tRC |
LA |
230 |
210 |
|
220 |
165 |
|
175 |
|||
|
|
VCC = Max. |
|
|
|
|
|
|
|
|
|||
|
|
IOUT = 0 mA |
|
|
|
|
|
|
|
|
|||
ISB |
|
Standby Current |
SA |
80 |
70 |
|
70 |
55 |
|
55 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CE1 = VIH and CE2 = VIL |
|
|
|
|
|
|
|
|
|||
|
|
f = fMAX = 1/tRC |
LA |
75 |
65 |
|
65 |
50 |
|
50 |
|||
|
|
VCC = Max. |
|
|
|
|
|
|
|
|
|||
ISB1 |
|
Full Standby Current |
SA |
20 |
20 |
|
25 |
10 |
|
15 |
|||
|
|
|
≥ VHC and CE2 ≤ VLC |
|
|
|
|
|
|
|
|
||
|
|
CE1 |
|
|
|
|
|
|
|
|
|||
|
|
f = 0 |
LA |
10 |
10 |
|
10 |
5 |
|
10 |
|||
|
|
VCC = Max. |
|
|
|
|
|
|
|
|
|||
|
|
VIN ≥ VCC – 0.2V or ≤ 0.2V |
|
|
|
|
|
|
|
|
SHADED AREAS = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
VLC ≤ 0.2V, VHC ≥ VCC – 0.2V
Rev. 3.3 - 4/09/98 |
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