ON Semiconductor SA572 Technical data

SA572

Programmable Analog Compandor

The SA572 is a dual-channel, high-performance gain control circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to detect the average value of input signal, a linearized, temperaturecompensated variable gain cell (G) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors.

The SA572 is intended for noise reduction in high-performance audio systems. It can also be used in a wide range of communication systems and video recording applications.

Features

• Independent Control of Attack and Recovery Time

• Improved Low Frequency Gain Control Ripple

• Complementary Gain Compression and Expansion with

External Op Amp

• Wide Dynamic Range − Greater than 110 dB

• Temperature-Compensated Gain Control

• Low Distortion Gain Cell

• Low Noise − 6.0 V Typical

• Wide Supply Voltage Range − 6.0 V-22 V

• System Level Adjustable with External Components

• Pb−Free Packages are Available*

Applications

• Dynamic Noise Reduction System

• Voltage Control Amplifier

• Stereo Expandor

• Automatic Level Control

• High-Level Limiter

• Low-Level Noise Gate

• State Variable Filter

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MARKING DIAGRAMS

SOIC−16 WB

D SUFFIX

CASE 751G

PDIP−16

N SUFFIX

CASE 648

TSSOP−16

DTB SUFFIX

CASE 948F

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

PIN CONNECTIONS

D, N, DTB Packages*

SA572D

AWLYYWWG

SA572N

AWLYYWWG

572

ALYW G

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference

Manual, SOLDERRM/D.

March, 2006 − Rev. 2

1 Publication Order Number:

TRACK TRIM B

RECOV. CAP B

RECT. IN B

ATTACK CAP B

G OUT B

THD TRIM B

G IN B

G IN A

GND

TRACK TRIM A

RECOV. CAP A

RECT. IN A

ATTACK CAP A

G OUT A

THD TRIM A

*D package released in large SO (SOL) package only.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

SA572/D

(7,9)

(6,10)

500

6.8k

SA572

(5,11)

G

GAIN CELL

(3,13)

(16)

−

270

RECTIFIER

P.S.

(8) (4,12) (2,14)

10k

−

BUFFER

Figure 1. Block Diagram

PIN FUNCTION DESCRIPTION

Pin Symbol Description

1 TRACK TRIM A Tracking Trim A

2 RECOV. CAP A Recovery Capacitor A

3 RECT. IN A Rectifier A Input

4 ATTACK CAP A Attack Capacitor A

5 G OUT A Variable Gain Cell A Output

6 THD TRIM A Total Harmonic Distortion Trim A

7 G IN A Variable Gain Cell A Input

8 GND Ground

9 G IN B Variable Gain Cell B Input

10 THD TRIM B T otal Harmonic Distortion Trim B

11 G OUT B Variable Gain Cell B Output

12 ATTACK CAP B Attack Capacitor B

13 RECT. IN B Rectifier B Input

14 RECOV. CAP B Recovery Capacitor B

15 TRACK TRIM B Tracking Trim B

16 V

Positive Power Supply

(1,15)

10k

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SA572

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage V

Operating Temperature Range T

Operating Junction Temperature T

Power Dissipation P

Thermal Resistance, Junction−to−Ambient N Package

D Package



DTB Package

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

DC ELECTRICAL CHARACTERISTICS Standard test conditions, V

signals at unity gain level (0 dB) = 100 mV

at 1.0 kHz; V

RMS

= V2; R

= 3.3 k; R

= 15 V , T

= 25°C; Expandor mode (see Test Circuit). Input

= 17.3 k unless otherwise noted.

Characteristic Symbol Test Conditions Min Typ Max Unit

Supply Voltage V

Supply Current I

Internal Voltage Reference V

Total Harmonic Distortion (Untrimmed)

Total Harmonic Distortion (Trimmed)

THD

1.0 kHz, C

No Signal Output Noise Input to V1 and V

grounded (20−20 kHz)

DC Level Shift (Untrimmed) Input change from no

signal to 100 mV

− 6.0 − 22 V

No Signal − − 6.3 mA

− 2.3 2.5 2.7 V

100 Hz

= 1.0 F

= 10 F

−

− 6.0 25 V

− "20 "50 mV

RMS

Unity Gain Level − −1.5 0 +1.5 dB

Large-Signal Distortion V

Tracking Error

(Measured relative to value at unity gain) =

(unity gain)] dB−V

O−VO

V2 = +6.0 dB, V1 = 0 dB

Channel Crosstalk 200 mV

channel A, measured

= V

= 400 mV − 0.7 3.0 %

Rectifier Input

−

= −30 dB, V

RMS

= 0 dB

into

−

60 − − dB

output on channel B

Power Supply Rejection Ratio PSRR 120 Hz − 70 − dB

22 V

−40 to +85 °C

150 °C

500 mW

°C/W

105

133

0.2

0.05

0.25

1.0

−

"0.2 "0.5 −2.5, +1.6

22F

100

+15V

−15V

1F

2.2F

17.3k

270pF

−

NE5234

0.1F

2.2F

= 10F

= 1F

2.2F

3.3k

5

(7,9)

(3,13)

6.8k

(2,14)

(4,12)

G

BUFFER

RECTIFIER

(5,11)

(6,10)

(8)

(1,15)

(16)

1k

82k

2.2k

Figure 2. Test Circuit

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SA572

Audio Signal Processing IC Combines VCA and Fast Attack/Slow Recovery Level Sensor

In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain control signal. This is true, for example, in compandor applications for noise reduction. In high end systems the input signal is usually split into two or more frequency bands to optimize the dynamic behavior for each band. This reduces low frequency distortion due to control signal ripple, phase distortion, high frequency channel overload and noise modulation. Because of the expense in hardware, multiple band signal processing up to now was limited to professional audio applications.

With the introduction of the SA572 this highperformance noise reduction concept becomes feasible for consumer hi fi applications. The SA572 is a dual channel gain control IC. Each channel has a linearized, temperature-compensated gain cell and an improved level sensor. In conjunction with an external low noise op amp for current-to-voltage conversion, the VCA features low distortion, low noise and wide dynamic range.

BASIC APPLICATIONS

The novel level sensor which provides gain control current for the VCA gives lower gain control ripple and independent control of fast attack, slow recovery dynamic response. An attack capacitor CA with an internal 10 k resistor RA defines the attack time A. The recovery time

R of a tone burst is defined by a recovery capacitor CR and

an internal 10 k resistor RR. Typical attack time of 4.0 ms for the high-frequency spectrum and 40 ms for the low frequency band can be obtained with 0.1 F and 1.0 F attack capacitors, respectively. Recovery time of 200 ms can be obtained with a 4.7 F recovery capacitor for a 100 Hz signal, the third harmonic distortion is improved by more than 10 dB over the simple RC ripple filter with a single 1.0 F attack and recovery capacitor, while the attack time remains the same.

The SA572 is assembled in a standard 16-pin dual in-line plastic package and in oversized SOL package. It operates over a wide supply range from 6.0 V to 22 V. Supply current is less than 6.0 mA. The SA572 is designed for applications from −40°C to +85°C.

Description

The SA572 consists of two linearized, temperature-

compensated gain cells (G), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.5 V common bias reference derived from the power supply but otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows flexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements.

Gain Cell

Figure 3 shows the circuit configuration of the gain cell. Bases of the differential pairs Q1-Q2 and Q3-Q4 are both tied to the output and inputs of OPA A1. The negative feedback through Q1 holds the VBE of Q1-Q2 and the V

of Q3-Q4 equal. The following relationship can be derived from the transistor model equation in the forward active region.

V

(VBE = VT IIN IC/IS)

Q3Q4

+ 

Q1Q2

* I1* I

(eq. 1)

where I

= 6.8 k

= 140 A

= 280 A

+ V

)

Ǔ* V

) I

* V

IO is the differential output current of the gain cell and I

is the gain control current of the gain cell.

If all transistors Q1 through Q4 are of the same size,

equation 1 can be simplified to:

@ IIN@ IG*

* 2I

@ I

(eq. 2)

The first term of equation 2 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The offset voltage can be trimmed out by feeding a current source within "25 A into the THD trim pin.

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