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NTMFS4833N
l
l
Power MOSFET
30 V, 191 A, Single N−Channel, SO−8 FL
Features
• Low R
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• These are Pb−Free Devices*
Applications
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain
Current R
(Note 1)
Power Dissipation
(Note 1)
R
q
JA
Continuous Drain
Current R
(Note 2)
Power Dissipation
(Note 2)
R
q
JA
Continuous Drain
Current R
(Note 1)
Power Dissipation
(Note 1)
R
q
JC
Pulsed Drain
Current
Operating Junction and Storage
Temperature
Source Current (Body Diode) I
Drain to Source dV/dt dV/dt 6 V/ns
Single Pulse Drain−to−Source Avalanche
Energy (T
= 35 Apk, L = 1.0 mH, RG = 25 W)
I
L
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
to Minimize Conduction Losses
DS(on)
= 25°C unless otherwise stated)
J
Parameter Symbol Value Unit
DSS
GS
TA = 25°C
q
JA
q
JA
q
JC
= 25°C, VDD = 30 V, VGS = 10 V,
J
Steady
State
TA = 85°C 19
TA = 25°C P
TA = 25°C
TA = 85°C 12
TA = 25°C P
TC = 25°C
TC = 85°C 138
TC = 25°C P
TA = 25°C,
= 10 ms
t
p
I
D
D
ID
D
I
D
D
I
DM
TJ, T
STG
S
EAS 612.5 mJ
T
L
30 V
±20 V
26
2.35 W
16
0.91 W
191
125 W
288 A
−55 to
+150
104 A
260 °C
A
A
A
°C
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V
(BR)DSS
30 V
G (4)
R
MAX ID MAX
DS(ON)
2.0 mW @ 10 V
3.0 mW @ 4.5 V
D (5,6)
S (1,2,3)
N−CHANNEL MOSFET
191 A
MARKING
DIAGRAM
D
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
S
S
S
G
4833N
AYWWG
G
D
ORDERING INFORMATION
Device Package Shipping
NTMFS4833NT1G SO−8 FL
(Pb−Free)
NTMFS4833NT3G SO−8 FL
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1500/Tape & Ree
5000/Tape & Ree
D
D
†
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 2
1 Publication Order Number:
NTMFS4833N/D
NTMFS4833N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case (Drain)
Junction−to−Ambient – Steady State (Note 3)
Junction−to−Ambient – Steady State (Note 4)
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
R
q
JC
R
q
JA
R
q
JA
1.0
53.2
137.8
°C/W
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
V
(BR)DSS
V
(BR)DSS
T
DSS
GSS
VGS = 0 V, ID = 250 mA
/
J
VGS = 0 V,
V
= 24 V
DS
VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient V
Drain−to−Source On Resistance R
V
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V to
11.5 V
VGS = 4.5 V
Forward Transconductance g
FS
VDS = 15 V, ID = 15 A 30 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Total Gate Charge Q
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
G(TOT)
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
Fall Time t
Turn−On Delay Time t
Rise Time t
Turn−Off Delay Time t
Fall Time t
t
d(ON)
r
d(OFF)
f
d(ON)
r
d(OFF)
f
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
= 3.0 W
R
G
VGS = 11.5 V, VDS = 15 V,
= 15 A, RG = 3.0 W
I
D
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
30 V
17
TJ = 25 °C 1
TJ = 125°C 10
1.5 2.5 V
7.12 mV/°C
ID = 30 A 1.3 2.0
ID = 15 A 1.3
ID = 30 A 2.3 3.0
ID = 15 A 2.3
5600
1200
650
39 58
6.0
16
17
88
25
34
35
17
14
19
50
10
mV/°C
mA
mW
pF
nC
nC
ns
ns
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2
NTMFS4833N
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise specified)
J
Parameter UnitMaxTypMinTest ConditionSymbol
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 30 A
S
VGS = 0 V, dIS/dt = 100 A/ms,
I
= 30 A
S
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance L
Gate Inductance L
Gate Resistance R
L
S
D
G
G
TA = 25°C
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
TJ = 25°C − 0.8 1.0
TJ = 125°C − 0.68 −
− 38 −
− 19 −
− 19 −
− 36 − nC
− 0.50 − nH
− 0.005 − nH
− 1.84 − nH
− 1.0 −
V
ns
W
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3
NTMFS4833N
0
I
, DRAIN CURRENT (AMPS)
0
200
TYPICAL PERFORMANCE CURVES
200
175
150
125
100
75
50
D
25
0
021
0.010
0.008
0.006
0.004
0.002
, DRAIN−TO−SOURCE RESISTANCE (W)
0
DS(on)
2
R
4.2 V thru 10 V
TJ = 25°C
3
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
VGS = 4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
, DRAIN CURRENT (AMPS)
3.0 V
I
2.8 V
40
5
175
150
125
100
D
75
50
25
0
VDS ≥ 10 V
TJ = 125°C
TJ = 25°C
TJ = −55°C
1
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
GS
23
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
ID = 30 A
T
= 25°C
J
4
650
8
10 12
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
0.004
0.003
0.002
0.001
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
TJ = 25°C
VGS = 4.5 V
VGS = 11.5 V
0
100
25
75
125 175150
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
45
20
1.75
ID = 30 A
V
GS
= 10 V
1.5
1.25
1.0
0.75
0.5
0.25
0
−50 250−25 50 75
, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
DS(on)
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
100
125
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100,000
10,000
, LEAKAGE (nA)
1,000
DSS
I
150
4
VGS = 0 V
TJ = 150°C
TJ = 125°C
100
0
5
1510 3
20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
25
C, CAPACITANCE (pF)
t, TIME (ns)
I
, DRAIN CURRENT (AMPS)
0
8000
)
12
0
7000
6000
5000
NTMFS4833N
TYPICAL PERFORMANCE CURVES
Q
C
iss
TJ = 25°C
C
iss
10
8
T
V
GS
4000
C
rss
3000
2000
C
1000
VDS = 0 V VGS = 0 V
0
−10 0 10 15
−5 5
V
GS
V
DS
oss
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
VDD = 15 V
I
= 15 A
D
= 11.5 V
V
GS
t
d(off)
t
f
100
t
r
t
d(on)
10
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
25
6
, GATE−TO−SOURCE VOLTAGE (VOLTS
GS
V
Q1
4
2
0
0
Q2
2010 30 807060
Q
, TOTAL GATE CHARGE (nC)
G
40
50
ID = 30 A
T
= 25°C
J
Figure 8. Gate−T o−Source and Drain−To−Source
V oltage vs. Total Charge
30
VGS = 0 V
25
TJ = 25°C
20
15
10
, SOURCE CURRENT (AMPS)
5
S
I
0
0 1.0
0.2 0.4
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
V
SD
0.6 0.8
Figure 10. Diode Forward Voltage vs. Current
9
1000
100
10
VGS = 20 V
1
SINGLE PULSE
TC = 25°C
0.1
D
R
DS(on)
LIMIT
THERMAL LIMIT
0.01
0.1 1 100
V
PACKAGE LIMIT
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
100 ms
1 ms
10 ms
dc
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
AS
E
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5
650
600
550
500
450
400
350
300
250
200
150
100
50
0
25
50 75
T
, STARTING JUNCTION TEMPERATURE (°C)
J
100 125
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
ID = 35 A
15
1000
100
NTMFS4833N
TYPICAL PERFORMANCE CURVES
25°C
10
, DRAIN CURRENT (AMPS)
D
I
1
100°C
125°C
10
PULSE WIDTH (ms)
1,000
Figure 13. Avalanche Characteristics
10,0001 100
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6
0.05
0.10 C
0.10 C
c
D
2
D1
1234
TOP VIEW
SIDE VIEW
b
8X
A0.10 BC
L
14
56
e/2
2 X
0.20 C
A
E1
E
2
A
DETAIL A
K
NTMFS4833N
PACKAGE DIMENSIONS
SO−8 FLAT LEAD (DFN6)
CASE 488AA−01
ISSUE B
B
2 X
0.20 C
c
DETAIL A
3 X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
DIM MIN NOM
4 X
A1 0.00 −−−
q
D1 4.50 4.90
A1
D2 3.50 −−−
E1 5.50 5.80
E2 3.45 −−−
C
e
SEATING
PLANE
L1 0.05 0.17
STYLE 1:
MILLIMETERS
A 0.90 0.99
b 0.33 0.41
c 0.23 0.28
D 5.15 BSC
E 6.15 BSC
e 1.27 BSC
G 0.51 0.61
K 0.51 −−−
L 0.51 0.61
M 3.00 3.40
q 0 −−−
_
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
MAX
1.20
0.05
0.51
0.33
5.10
4.22
6.10
4.30
0.71
−−−
0.71
0.20
3.80
12
_
E2
6
G
5
D2
L1
M
BOTTOM VIEW
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NTMFS4833N/D
7
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