All-in-One Power Supply
Evaluation Board User's
Manual
240 W Power Supply using NCP1618,
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NCP13992, NCP4306 and NCP431
Description
This evaluation board user’s manual provides basic information
about a high efficiency, low no−load power consumption reference
design that was tailored to power All−in−One PC or similar type of
equipment that accepts 12 V
implements PFC front stage to assure unity power factor and low
DC on the input. The power supply
THD, current mode LLC power stage to enhance transient response
and secondary side synchronous rectification to maximize efficiency.
This design note provides brief information about controllers’
implementation into design, their interconnections and cooperation.
Please use links in literature section to get detail technical information
about NCP1618, NCP13992, NCP4306 and NCP431.
The NCP1618 is an innovative multimode power factor controller.
The controller automatically change operation mode depending on
conditions so that the efficiency is optimized over the line and load
range. In very light−load conditions, the circuit enters a soft−skip
cycle mode. NCP1618 enters Continuous Conduction Mode (CCM)
under Heavy−Load Conditions, while Frequency−Clamped Critical
Conduction Mode (FCCrM) is used for Medium− and Light−Load
Conditions. PFC−OK Output serves as Brown−Out signal for LLC
controller as well as communication interface which sends NCP1618
into stand−by mode (using Soft−skip cycles).
The NCP13992 is a high performance current mode LLC controller
for half bridge resonant converters. This controller implements 600 V
gate drivers, simplifying layout and reducing external component
count. In applications where a PFC front stage is needed, the
NCP13992 features a dedicated output to drive the PFC controller.
This feature together with quiet skip mode technique further improves
light load efficiency of the whole application. Both controllers provide
a suite of protection features allowing safe power supply operation in
any application. Built−in high voltage input function ease
implementation of the controllers in all applications startup circuits.
Input side of evaluation board is protected by a several
components. As first, it’s a 5 A slow reaction fuse F101,
which disconnects input in case wrong manipulation, line
overvoltage stress event and unexpected stresses or
conditions. Voltage dependent resistor R101 serves as input
overvoltage protection triggered at approximately 275 V
AC. Demo−board implements inrush−current limiting
device, R102 NTC thermistor which is not assembled to
allow clear efficiency measurement (Figure 2). It’s
recommended to assemble R102 in case of testing in hard
conditions (using power grid directly or AC power supply
without current limit). Use appropriate NTC inrush current
limiter in case of need.
EMI filter is formed by components L101, L102, L103,
C101, C102, C103, C104, CY101 and CY102 (Figure 2).
The IC101 − NCP1618 measures input line voltage via
diodes D108, D109, D1 10 and resistors R1 18, R121 to detect
present of Brown−out/ Brown−in and SAG conditions as
well as distinguishes input line level. This circuit also
provides PFC Vcc Start−up feature for building controller
Vcc supply. The Power Factor Corrector (PFC) power stage
implements standard boost PFC topology composed of
following power devices; bridge rectifier B101, power
(boost) inductor L104, power MOSFET switch Q101, boost
power diode D103, bypass diode D102, shunt resistors
R106−R107 and bulk capacitors C107, C201−C202. The
PFC controller IC101 (NCP1618) senses input voltage
directly via pin 10 (HV) through network of D108, D109,
D110 and resistors R118, R121. The PFC inductor current
is monitored on the shunt resistor R106−R107. The series
resistors R105−R1 19 set maximum current. Capacitor C108
that is connected between those resistors filters noise caused
by switching. Maximum current through resistors can be
calculated based on NC1618 datasheet. The PFC feedback
divider has high impedance (approximately 10.8 MW)
which ensures low consumption in no−load or light−load
mode conditions. PFC FB divider is created from upper
resistor R113−R116, lower resistor R120 and capacitor
C109. The PFC FB signal is filtered by capacitor C109 to
minimize noise caused by the parasitic capacitive coupling
between pin and other nodes that handle high dV/dt signals.
PFC FB divider sets nominal bulk voltage level which is
400 V approximately. NCP1618 features positive bulk
voltage hiccup, so that while LLC Stage runs under burst
mode, NCP13992 forces NCP1618 to enter skip mode
(stand−by mode), thus bulk−voltage is maintained between
+103% and 98 % of nominal bulk voltage i.e. between
~420 V and ~394 V on this design. NCP1618 can be sent
into soft−skip−mode (stand−by mode) by two ways. This
demo−board implements only one solution – via
pulling−down the PFC−OK pin. Refer to NCP1618
datasheet for more detailed description. Devices D111,
D112, C116 and R222 are used for PFC−OK pulling−down
purpose. Once, IC203 NCP13992 enters to skip, MODE pin
(9) goes low level and pulls down PFC−OK for interval
longer than 29 ms, which results in establishing PFC
stand−by soft skip mode. NCP1618 PFC−OK pin generates
signal which is green−light for down−stream LLC converter .
If no fault occurs and bulk voltage level is in regulation
range, PFC−OK pin sources current which is translated into
drop at R217 and this voltage enables NCP13992 operation.
NCP1618 has integrated driver but the external PNP
transistor Q102 was implemented. The Q102 is connected
directly to source of Q101 in order to minimize discharge
loop and thus allow faster PFC switch turn−off and also
minimizing EMI caused by the driver loop. Q101 Gate
turn−on path is secured by R110, R111 and D106, on the
contrary turn−off path is realized mainly via R1 10 and Q102.
This solution enables to define required switching speeds for
both processes independently. The PFC choke auxiliary
winding voltage is processed by circuit R109, R112, R124,
C105, C106, C114, D10, D104, D105 and D107. Processed
signal is fed into ZCD pin, which detects valleys
zero−current and OVP2 events. This pin provides a voltage
VM for duty cycle modulation when the circuit operates in
continuous conduction mode. The NCP1618 external
network connected to the VM pin adjusts the maximum
power which can be delivered by the PFC stage. R122−R123
set maximum power in CCM mode, C110−C112 filter noise
coupled to this pin.
Schematics diagram in Figure 2 contains module with
designator MOD101. Internal schematic diagram of this
module is displayed in Figure 4. MOD101 was designed as
a part of PFC stage and it’s a discrete solution for discharging
EMI filter differential capacitors. This element was named
as “EMI Capacitor Discharging Module”. Module works in
very simple way based on charge pump principle made of
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NCP13992MM240WGEVB
C301, R301, R302, D301 and D302. When AC voltage is
presented at pin ECD_AC, charge pump creates voltage (at
C302/R303) which is clamped by Zener−diode D303. This
voltage turn−on MOSFET Q301, which pull−down Gate
voltage of Q303. While AC line is presented charge pump
continues to operate and generates voltage/current which
disables Q303. Once, AC line turns out, charge pump stops
and Q303 is turned on and discharges differential capacitors
in EMI filter (through bridge rectifier B101).
Entire LLC power stage is displayed in Figure 3. Power
stage at primary side of LLC converter is composed of these
devices: MOSFETs Q202, Q203, external resonant inductor
L201, transformer TR201 and resonant capacitors C205 and
C206. The IC203 NCP13992, LLC controller senses
primary current indirectly, via resonant capacitor voltage,
which is divided down by a capacitive divider, using
capacitors C227−C228 and C229. The capacitive divider
has to be optimally loaded and in the same time assure fast
signal stabilization after application startup. This is
achieved by resistor R228. Scaled signal from CS divider
passes through resistor R224 which limits maximum current
that can flow into the LLC_CS pin. The FB optocoupler
OK201 is connected to the LLC_FB pin and defines
converter output voltage by pulling down this pin when
lower output power is needed. Capacitor C220 forms high
frequency pole in FB loop characteristics and helps to
eliminate eventual noise that could be coupled to the FB pin
by parasitic coupling paths. The VB/PFC−FB pin allows
LLC converter operation once input level is approximately
above 1.1 V. VB/PFC−FB signal is provided by PFC
controller NCP1618, which sources current from PFC−OK
pin as aforementioned. VB/PFC−FB pin voltage is filtered
by C218. The Skip/REM pin of the NCP13992 is sued for
skip threshold adjustment. Resistor R221 is used for this
purpose together with noise filtering capacitor C219. The
over−voltage and over−temperature protections are
implemented via OVP/OTP pin by using resistor R223,
temperature dependent resistor NTC201, Zener−diode
D208, filtering capacitor C221 and optocoupler OK202.
Simple OVP detector is located on the secondary side and it’s
made of resistor R245, Zener−diode D211 OK202
optocoupler diode. The FB_FREEZE pin (8) defines
minimum internal feedback voltage (lower saturation level),
which influences maximum switching frequency. Resistor
R225 sets FB freeze level and C222 decouples noise. The
PFC stand−by mode (or PFC soft−skip) is activated by
MODE pin ( 9 ) , w hich goes high during LLC stage switching
and stays low during idle mode– as described in PFC section.
The VCC decoupling capacitor C224 and also bootstraps
capacitor C223 for high side driver powering are located as
close to the LLC controller package as possible to minimize
parasitic inductive coupling to other IC adjust components
due to high driver current peaks that are present in the circuit
during drivers rising and falling edge transitions. The
bootstrap capacitor is charged via HV bootstrap diode D209
and series resistor R226 which limits charging current and
VBOOT to HB power supply slope during initial C223
charging process. The gate driver currents are reduced by
added series resistors R201, R202 to optimize EMI signature
of the application. Schottky diodes D203 and D204 are used
to speed−up the MOSFETs turn−off process. The primary
controllers are biased by voltage limiter circuitry, which is
used in order to not exceed VCC pin maximum ratings. The
upper value of the primary VCC voltage is clamped to
approximately 15 V. The VCC clamp is composed of these
components: R205, R206, Q201, D202 and C203. The VCC
clamp is fed from auxiliary windings via rectifier
D205−D206 and current limiting resistor R207−R208. The
secondary side synchronous rectification uses IC201 and
IC202 NCP4306 SR controllers. Two MOSFTEs are
connected in parallel for each SR channel to achieve low
total voltage drop − Q204, Q206 and Q205, Q207. RC
snubber circuits C208−R209 and C209−R210 are used to
damp down the parasitic ringing and thus limit the
maximum peak voltage on the SR MOSFETs. The SR
controllers are supplied from converter output via resistors
R211 and R216. These resistors with decoupling capacitors
C210 and C211 form RC filter. The minimum on−time –
R213, R214 and minimum off−time – R212, R215 resistors
define needed blanking periods that help to overcome SR
controllers false triggering to ringing in the SR power stage.
Each SR controller implements clever light load detection
feature LLD. After first incoming pulse from skip burst, the
LLD feature wakes−up the controller from low power mode
(50 mA). SR controller enters to stand−by mode after defined
period of time (68 ms) once the last pulse from the skip burst
ends. Internal setup cares about LLD feature timing thus
eliminates need for complicated external light−load guard
circuitry. The NCP4306 LLD feature offers great benefits
compare to the traditional solutions, in which SR operation
and no−load consumption is much less efficient. The output
filtering capacitor bank composes from low ESR
electrolytic capacitors C212 to C215 and ceramic capacitors
C217, C235 and C236. Output filter L202, C216 is used to
smooth output voltage from switching glitches. The output
voltage of the converter is regulated by standard shunt
regulator NCP431− IC204. The regulation optocoupler
OK201 is driven via resistor R232 which defines loop gain.
The NCP431 is biased via resistor R237 in case there is no
current flowing via regulation optocoupler –which can
happen before the nominal V
level is reached or during
OUT
transients from no−load to full−load conditions. The output
voltage is adjusted by divider R239, R241, and R243. The
feedback loop compensation network is formed partially by
resistor R240 and capacitor C233.
PCB layout is prepared with options so user can modify
demo−board accordingly if needed – please refer to
schematics. The PCB consists of a 2 layer FR4 board with
70 mm copper thickness to minimize resistance in secondary
side where high currents are conducted. Leaded components
are assembled form the top side of the board and all SMT
components are place from the bottom only. The board was
designed to work as open frame with natural air flow
cooling. Forced air flow cooling management should be
considered in case the board is packed into some box or
target application.
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Figure 5. Evaluation Board − Top Side Components
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Figure 6. Evaluation Board − Bottom Side Components
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NCP13992MM240WGEVB
Figure 7. Evaluation Board − PCB Design of Top Layer
Figure 8. Evaluation Board − PCB Design of Bottom Layer
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NCP13992MM240WGEVB
Figure 9. Evaluation Board Photograph − Bottom Side
Single N−Channel Power MOSFET 40 V, 130 A, 2.5 mW
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