ON Semiconductor NCP12400 User guide

Fixed Frequency Current
f
Mode Controller for Flyback Converters
NCP12400
It features a timer−based fault detection that ensures the detection of overload and an adjustable compensation to help keep the maximum power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent efficiency in light load condition while still achieving very low standby power consumption. Internal frequency jittering, ramp compensation, and a versatile latch input make this controller an excellent candidate for the robust power supply designs.
A dedicated Off Mode allows to reach the extremely low no load input power consumption via “sleeping” whole device and thus minimize the power consumption of the control circuitry.
Features
Fixed−Frequency Current−Mode Operation 65 kHz or 100 kHz
Frequency Options
Frequency Foldback then Skip Mode for Maximized Performance
in Light Load and Standby Conditions
Timer−Based Overload Protection with Latched (Option A) or
Autorecovery (Option B) Operation
High−Voltage Current Source with Brown−Out Detection and
Dynamic Self−Supply, Simplifying the Design of the V
Frequency Modulation for Softened EMI Signature
Adjustable Overpower Protection Dependant on the Mains Voltage
Fault Input for Overvoltage and Over Temperature Protection
V
Operation up to 28 V, with Overvoltage Detection
CC
300/500 mA Source/Sink Drive Peak Current Capability
4/10 ms Soft−Start
Internal Thermal Shutdown
No−Load Standby Power < 30 mW
X2 Capacitor in EMI Filter Discharging Feature
These are Pb−Free Devices
Typical Applications
Offline Adapters for Notebooks, LCD, and Printers
Offline Battery Chargers
Consumer Electronic Power Supplies
Auxiliary/Housekeeping Power Supplies
Offline Adapters for Notebooks
capacitor by activating
CC
Circuitry
CC
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SOIC−7
CASE 751U
MARKING DIAGRAM
8
XXXXX ALYWG
G
1
400VWXYZf
(Note: Microdot may be in either location)
See detailed ordering and shipping information on page 44 o this data sheet.
= Specific Device Code
(see page 2) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
PIN CONNECTIONS
1
FAULT
FB
CS
GND DRV
4
(Top View)
ORDERING INFORMATION
8
HV
V
CC
5
© Semiconductor Components Industries, LLC, 2017
February, 2021 − Rev. 6
1 Publication Order Number:
NCP12400/D
NCP12400
Table 1. OPTIONS
Part
OPN
Brown Out
OCP Fault
Frozen
Quiet skip
Soft
Frequency
OTP/OVP
NCP12400BAHAB0DR2G
103 − 100 V
Latched
300 mV
No, min. 3 pulses
4 ms
65 kHz
Latched
NCP12400BAHBB0DR2G
111 − 103 V
Latched
300 mV
Yes, min. 3 pulses,
4 ms
65 kHz
Latched
NCP12400BBBBB2DR2G
111 − 103 V
Autorecovery
150 mV
Yes, min. 3 pulses,
4 ms
65 → 100
Latched
NCP12400BBHAA1DR2G
111 − 103 V
Autorecovery
300 mV
No, min. 3 pulses
10 ms
100 kHz
Autorecovery
NCP12400CAHAB0DR2G
95 − 93 V
Latched
300 mV
No, min. 3 pulses
4 ms
65 kHz
Latched
NCP12400CBAAB0DR2G
95 − 93 V
Autorecovery
No
No, min. 3 pulses
4 ms
65 kHz
Latched
NCP12400CBBAB0DR2G
95 − 93 V
Autorecovery
150 mV
No, min. 3 pulses
4 ms
65 kHz
Latched
NCP12400CBHAA0DR2G
95 − 93 V
Autorecovery
300 mV
No, min. 3 pulses
10 ms
65 kHz
Autorecovery
NCP12400EAHBB0DR2G
Brown In, No
Latched
300 mV
Yes, min. 3 pulses,
4 ms
65 kHz
Latched
NCP12400BBBBA0DR2G
111 − 103 V
Autorecovery
150 mV
Yes, min. 3 pulses,
10 ms
65 kHz
Latched
NCP12400BBHAB0DR2
111 − 103 V
Autorecovery
300 mV
No, min. 3 pulses
4 ms
65 kHz
Latched
NCP12400BBEBA0DR2G
111 − 103 V
Autorecovery
210 mV
Yes, min. 3 pulses,
10 ms
65 kHz
Latched
NCP12400BBAAA0DR2G
111 − 103 V
AutorecoveryNoNo
10 ms
65 kHz
Latched
TYPICAL APPLICATION SCHEMATIC
Figure 1. Flyback Converter Application using the NCP12400
NCP12400
Start − Stop
BO
Current
Setpoint
only
800 Hz burst
800 Hz burst
only
only
only
only
only
800 Hz burst
800 Hz burst
only
800 Hz burst
Start
kHz
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2
NCP12400
Table 2. SPECIFIC DEVICE CODE KEY
400VWXYZf
BO
OCP Fault
Frozen Current
Quiet Skip
Soft Start
Frequency
A − 229−211 V
A − Latched
A −No
A − No, min. 3
A − 10 ms
0 − 65 kHz
Table 3. PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Function
Pin Description
1
FAULT
FAULT Input
Pull the pin up or down to stop the controller. An internal current source allows the
2FBFeedback + Shutdown
An optocoupler connected to ground controls the output regulation. The part goes to
3CSCurrent Sense
This input senses the primary current for current−mode operation, and offers an
4
GND
The controller ground.
5
DRV
Drive Output
Drives external MOSFET.
6
VCCVCC Input
This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
8HVHigh−Voltage Pin
Connects to the rectified ac line to perform the functions of start−up current source,
Part
B − 111−103 V
C − 95−93 V
D − No BO
E − Brown In, no BO
Pin
B − Autorecovery
direct connection of an NTC for over temperature detection. Device can restart in autorecovery mode or can be latched depending on the option.
the low consumption Off mode if the FB input pin is pulled to GND.
overpower compensation adjustment. This pin implements over voltage protection as well.
connected to an external auxiliary voltage.
Setpoint
B − 150 mV C − 170 mV D − 190 mV E − 210 mV
F − 230 mV G − 250 mV H − 300 mV
pulses
B − Yes, min. 3
pulses,
800 Hz burst
B − 4 ms
1 − 100 kHz
2 − 65 100 kHz
Self−Supply, brown−out detection and X2 capacitor discharge function and the HV sensing for the overpower protection purposes.
It is not allowed to connect this pin to a dc voltage.
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3
FAULT
FB
CS
GND
Vdd
Intc
Intc
1k
Rcla m p
1. 2 V
Vclamp
SS_end
Brown_Out
RESET
VCC
5u A
Von
Vfb(reg)
Voff
Rfb1
Internalresitance40k
Vhv DC sample
V to I
Iopc = 0 .5u*(Vhv −125)
Vdd
1uA
Vfb < 1.64 V fix current setpoint 210mV
OVP_CMP
Vov p
2. 5V OTP_CMP
Votp
0. 4 V
Off_mode_CMP1
2.2V
Off_mode_CMP2
0. 6V
NCP12400
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
300 us
Filter
Vfb(o pc)
Div i sion ratio 4
LEB 250 ns
LEB 120 ns
Latch
Rfb2Rf b3
OVP
OTP
Vskip
Vilim
VCSs to p
LEB 1 us
VccOVP
Set Q
Reset Qb
Skip_CMP
PWM_CMP
SoftStart_CMP
Ilimit_CMP
0.7V
CSstop_CMP
1.05V
10us Filter
ICstart
jittering
freq folback
CSref
SkipB
Soft Start timer
VccMIN
PWM
MAX_ton
Ilimit
OVP_CMP
VccOVP_CMP
UVLO_CMP
UVLO
ON_CMP
VccON
STOP_CMP
FM input
OSC 65kHz
PFM input
Ramp_OTA
4uMho
4 events timer
26V
9.5V
12V10.5 V
Square output
ton_ max output
Saw output
1.4V
Vramp_offset
MAX_ton
Enable SS_end
VccOVP
Vcc_Int
Vdd reg
VccOFF
Vdd
VccONVccMI N
Reset
55us Filter
Set Q
Reset Qb
GoToOffMode timer 500ms
FBbuffer
2. 6V
Bro wn_Ou tB
QSet
Qb
4 events timer600ns timer
IC stopB
FaultB
Vhv DC sample
Brown_In
AC_Off
OM & X2 & Vcc
TSD
X2 discharge
ICstar tB
11V regulator
3. 0V
LatchB
Fault timer
control
PowerOnReset_CMP
Fault
Brown_Out
TSD
Reset
TSD
Dual HV
start−up
current source
Vcc regulator
RESET
QSet
Qb
HV
8mA
VCC
10.8V7V Vcc( reg )VccRESET
VCC
Clamp
DRV
RESET
IC stop Latch
Latch management
Vovp
DRV
1.05V
Figure 2. Simplified Internal Block Schematic
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NCP12400
Table 4. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DRV
Maximum voltage on DRV pin
–0.3 to 20
V
V
VCCPower Supply voltage, VCC pin, continuous voltage
–0.3 to 36
VmAHV
Maximum voltage on HV pin
–0.3 to 500
V
V
Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
–0.3 to 5.5
V
R
Thermal Resistance SOIC−7
C/W
R
Thermal Resistance Junction−to−Case
73
C/W
T
Operating Junction Temperature
−40 to +150
C
T
Storage Temperature Range
−60 to +150
C
ESD Capability, HBM model (All pins except HV) (Note 1)
> 4000
V
ESD Capability, HBM model (pin 8, HV)
> 2000
V
ESD Capability, Charge Discharge Model (Note 1)
> 500
V
Table 5. ELECTRICAL CHARACTERISTICS
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source
V
−3040
V
Current flowing out of VCC pin
VCC = 0 V
I
0.250.580.811mA
Off−state leakage current
VHV = 500 V, VCC = 15 V
I
−26
A
SUPPLY
Turn−on threshold level, VCC going up
V
11.0
12.0
13.0
V
HV current source restart threshold
V
9.5
10.5
11.5
V
Turn−off threshold
V
8.4
8.9
9.3
V
Overvoltage threshold
V
253026.5322834V
Blanking duration on V
and V
t
−10−
s
(pin 5)
(pin 6)
(pin 8)
max
q
q
JMAX
STRGMAX
(Dc−Current self−limited if operated within the allowed range) (Note 2)
CC
Power Supply voltage, VCC pin, continuous voltage (Note 2)
(Dc−Current self−limited if operated within the allowed range)
(Dc−Current self−limited if operated within the allowed range) (Note 2)
J−A
Junction-to-Air, low conductivity PCB (Note 3) Junction-to-Air, medium conductivity PCB (Note 4) Junction-to-Air, high conductivity PCB (Note 5)
J−C
±1000 (peak)
±30 (peak)
±20
±10 (peak)
162 147 115
mA
mA
mA
°
°
°
°
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC standard JESD22, Method A114E Charge Discharge Model Method 500 V per JEDEC standard JESD22, Method C101E
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm
2
of 2 oz copper traces and heat spreading area. As specified
2
of 2 oz copper traces and heat spreading area. As specified
2
of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
operation
HV current source stop threshold
VCC = V
CC(on)
− 0.5 V
HV(min)
start1
I
start2
start(off)
CC(on)
15.0
16.2
(depending on the version)
CC(min)
CC(off)
Overvoltage threshold (option EAHBB,
CC(ovp)
BBBBB)
detection
CC(off)
CC(ovp)
VCC(blank)
6. Guaranteed by design.
7. CS pin source current is a sum of I
bias
and I
, thus at VHV = 125 V is observed the I
OPC
only, because I
bias
is switched off.
OPC
m
17.5
m
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5
NCP12400
VCC decreasing level at which the internal
V
4.8
7.0
7.7
V
VCC level for I
to I
transition
V
1.0
2.1
3.0
V
Internal current consumption
DRV open, VFB = 3 V, 65 kHz
I
1.0
1.3
2.0
mA
BROWN−OUT
Brown−out thresholds (option A)
VHV going up
V
210
229
248
V
Brown−out thresholds (option B)
VHV going up
V
10294111
120
V
Brown−out thresholds (option BAHAB)
VHV going up
V
9390103
113
V
Brown−out thresholds (option C)
VHV going up
V
87859593103
V
Brown−out thresholds (option E)
VHV going up
V
90
100
110
V
Timer duration for line cycle drop−out
tHV424864738698ms
X2 DISCHARGE
Comparator hysteresis observed at HV pin
V
2.0
3.0
4.0
V
HV signal sampling period
t
1.0−ms
Timer duration for no line detection
t
213243
ms
Discharge timer duration
t
213243
ms
Shunt regulator voltage at VCC pin during X2
V
10.0
11.0
12.0
V
OSCILLATOR
Oscillator frequency 65 kHz version
f
619465
69
kHz
Maximum duty−ratio (corresponding to
D
758085
%
Frequency jittering amplitude, in percentage
A
3.0±4.0±5.0
kHz
Frequency jittering modulation frequency
F
85
125
165
Hz
FREQUENCY FOLDBACK
Feedback voltage threshold below which
TJ = 25°C
V
2.4
2.5
2.6
V
Feedback voltage threshold below which
TJ = 25°C
V
2.05
2.15
2.25
V
Minimum switching frequency
VFB = V
+ 0.1
f
252831
kHz
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T
SUPPLY
logic resets
= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
J
Characteristics UnitMaxTypMinSymbolTest Condition
START1
START2
Cdrv = 1 nF, V
DRV open, VFB = 3 V, 100 kHz Cdrv = 1 nF, VFB = 3 V, 65 kHz
= 3 V, 100 kHz
FB
Skip or before start−up
Fault mode (fault or latch)
Off−mode
VHV going down
VHV going down
VHV going down
VHV going down
CC(reset)
CC(inhibit)
CC1
I
CC2
I
CC3
I
CC4
I
CC5
HV(start)
V
HV(stop)
HV(start)
V
HV(stop)
HV(start)
V
HV(stop)
HV(start)
V
HV(stop)
HV(start)
1.1
1.5
2.0 400 300
194
1.4
2.1
2.6 500 430
25
211
103
100
2.1
2.9
3.4 650 550
228
116
110
101
mA mA
mA
mA mA mA
(depending on the version)
discharge event
Oscillator frequency 100 kHz version
maximum on time at maximum switching frequency)
of F
OSC
frequency foldback starts
frequency foldback is complete
HV(hyst)
sample
DET
DIS
CC(dis)
OSC
MAX
jitter
jitter
FB(foldS)
FB(foldE)
100
110
±
6. Guaranteed by design.
7. CS pin source current is a sum of I
bias
and I
skip(in)
, thus at VHV = 125 V is observed the I
OPC
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6
OSC(min)
only, because I
bias
is switched off.
OPC
NCP12400
OUTPUT DRIVER
Rise time, 10 to 90% of V
VCC = V
+ 0.2 V,
t
−4070
ns
Fall time, 90 to 10% of V
VCC = V
+ 0.2 V,
t
−3060
ns
Current capability
VCC = V
+ 0.2 V,
mA
Clamping voltage (maximum gate voltage)
VCC = V
– 0.2 V, DRV high,
V
101214
V
High−state voltage drop
VCC = V
+ 0.2 V,
V
−−1
V
CURRENT SENSE
Input Pull−up Current
VCS = 0.7 V
I
−1−
A
Maximum internal current setpoint
VFB > 3.5 V
V
0.66
0.70
0.74
V
Propagation delay from V
detection to
VCS = V
t
−5070
ns
Leading Edge Blanking Duration for V
t
180
250
320
ns
Threshold for immediate fault protection
V
0.95
1.05
1.15
V
Leading Edge Blanking Duration for V
)
t
75
120
150
ns
Soft−start duration (option A)
From 1st pulse to VCS = V
t
10
13
ms
Frozen current setpoint (option B)
V
100
150
200
mV
Over voltage protection threshold when DRV
VCS going up
V
1.00
1.05
1.10
V
Blanking duration on OVP detection
t
0.7
1.0
1.3
s
Delay time constant before OTP confirmation
t
600−ns
INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp
S
−−−32.5
−−mV /
FEEDBACK
Internal pull−up resistor
TJ = 25°C
R
304050
k
VFB to internal current setpoint division ratio
KFB−4−
Internal pull−up voltage on the FB pin
V
4.555.5
V
Offset between FB pin and internal FB
TJ = 25°C
V
0.8−V
SKIP CYCLE MODE
Feedback voltage thresholds for skip mode
VFB going down, TJ = 25°C
V
0.9
1.0
1.1
V
Minimum number of pulses in burst
n
3−−
Skip out delay
t
−−38
s
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T
DRV off
activation
= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
J
Characteristics UnitMaxTypMinSymbolTest Condition
CC
CC
Ilimit
ILIM
C
C
C DRV high, V DRV low, V
CC(ovp)
R
= 33 kW, C
DRV
R
= 33 kW, DRV high
DRV
CC(off)
DRV
CC(off)
DRV
CC(off)
DRV
CC(min)
= 1 nF
= 1 nF
= 1 nF
DRV
DRV
load
ILIM
= 0 V
= V
CC
= 220 pF
rise
fall
I
DRV(source)
I
DRV(sink)
DRV(clamp)
DRV(drop)
bias
ILIM
delay
LEB
CS(stop)
300 500
m
(Note 6)
Soft−start duration (option B)
Frozen current setpoint (option D) Frozen current setpoint (option E) Frozen current setpoint (option H)
is low
(Note 6)
divider
CS(stop
ILIM
BCS
SSTART
I(freeze)
OVP(CS)
OVP,CS OVP,del
comp(65kHz)
S
comp(100kHz)
FB(up)
FB(ref) FB(off)
3.2
140 145 250
4.0
190 210 300
−50
4.8
240 270 350
m
ms
W
6. Guaranteed by design.
7. CS pin source current is a sum of I
skip(in)
V
skip(out)
P,skip
skip
only, because I
bias
1.05
1.15
is switched off.
OPC
1.25
m
bias
and I
VFB going up, TJ = 25°C
, thus at VHV = 125 V is observed the I
OPC
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NCP12400
REMOTE CONTROL ON FB PIN
The voltage above which the part enters the
VCC > V
, VHV = 60 V
VON−
2.2−V
The voltage below which the part enters the
VCC > V
V
0.5
0.6
0.7
V
Minimum hysteresis between the VON and
VCC > V
, VHV = 60 V
V
500−−
mV
Pull−up current in off mode
VCC > V
I
−5−
A
Go To Off mode timer
VCC > V
t
400
500
600
ms
OVERLOAD PROTECTION
Fault timer duration
t
108
128
178
ms
Fault timer reset time
VCS < 0.7 V, D < 90% D
t
150
200
250
s
Autorecovery mode latch−off time duration
t
0.85
1.00
1.35
s
OVERPOWER PROTECTION
VHV to I
conversion ratio
K
0.54
A / V
Current flowing out of CS pin (Note 7)
VHV = 125 V
I
0
A
FB voltage above which I
is applied
VHV = 365 V
V
2.6−V
FB voltage below which is no I
applied
VHV = 365 V
V
1.6−V
FAULT INPUT
High threshold
V
going up
V
2.43
2.50
2.57
V
Low threshold
V
going down, TJ = 25°C
V
0.380
0.400
0.420
V
OTP resistance threshold (TJ = 25°C)
External NTC resistance is going
R
7.6
8.0
8.5
k
OTP resistance threshold (TJ = 80°C)
External NTC resistance is going
R
8.5
k
OTP resistance threshold (TJ = 110°C)
External NTC resistance is going
R
9.5
k
Current source for direct NTC connection
V
= 0.2 V
A
Current source for direct NTC connection
V
= 0.2 V, TJ = 25°C
I
475053
A
Blanking duration on high latch detection
t
355070
s
Blanking duration on low latch detection
t
350
s
Clamping voltage
I
= 0 mA
V
1.0
1.2
1.4
V
TEMPERATURE SHUTDOWN
Temperature shutdown
TJ going up
T
150
−°C
Temperature shutdown hysteresis
TJ going down
T
−30−°C
6. Guaranteed by design.
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T
on mode
off mode
V
OFF
OPC
= 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
J
Characteristics UnitMaxTypMinSymbolTest Condition
OPC
OPC
CC(off)
CC(off)
CC(off)
CC(off) CC(off)
VHV = 162 V
= 325 V
V
HV
V
= 365 V
HV
MAX
OFF
HYST
OFF
GTOM
fault
fault,res
autorec
OPC
OPC(125)
I
OPC(162)
I
OPC(325)
I
OPC(365)
FB(OPCF)
FB(OPCE)
105
20 110 130
m
m
m
m
150
During normal operation During soft−start
During normal operation
7. CS pin source current is a sum of I
bias
and I
Latch
Latch
down
down
down
Latch
Latch
Latch
I
= 1 mA
Latch
, thus at VHV = 125 V is observed the I
OPC
OVP OTP OTP
OTP
OTP
I
NTC
I
NTC(SSTART)
NTC
Latch(OVP) Latch(OTP)
clamp0(Latch)
V
clamp1(Latch)
TSD
TSD(HYS)
only, because I
bias
30 60
1.8
50 100
2.4
is switched off.
OPC
W
W
W
m
70
140
m
m
m
3.0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP12400
TYPICAL CHARACTERISTIC
Figure 3. Minimum Voltage for HV Current Source
Operation V
HV(min)
Figure 5. HV Pin Device Startup Threshold
V
HV(start)
Figure 4. High Voltage Startup Current Flowing
Out of V
CC
Pin I
of VCC Pin Fault/Short
start1
Figure 6. Off−state Leakage Current from HV Pin
I
start(off)
Figure 7. High Voltage Startup Current Flowing
Out of V
CC
Pin I
start2
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Figure 8. HV Pin Device Stop Threshold V
9
HV(stop)
NCP12400
Figure 9. Maximum Internal Current Setpoint
V
ILIM
Figure 11. Propagation Delay t
delay
Figure 10. Threshold for the Very Fast Fault
Protection Activation V
Figure 12. Frozen Current Setpoint V
CS(stop)
I(freeze)
Light Load Operation
for the
Figure 13. Over Voltage Protection Threshold at
CS Pin V
OVP(CS)
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Figure 14. Leading Edge Blanking Duration t
LEB
NCP12400
Figure 15. FB Pin Internal Pull−up Resistor
R
FB(up)
Figure 17. FB Pin Skip−In and Skip−Out Levels
V
skip(in)
and V
skip(out)
Figure 16. Built in Offset between FB Pin and
Internal Divider V
Figure 18. FB Pin Open Voltage V
FB(off)
FB(ref)
Figure 19. FB Pin Frequency Foldback Thresholds
V
FB(foldS)
and V
FB(foldE)
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NCP12400
Figure 20. Oscillator Switching Frequency f
OSC
Figure 22. X2 Discharge Comparator Hysteresis
Observed at HV Pin V
HV(hyst)
Figure 21. Minimum Switching Frequency
f
OSC(min)
Figure 23. Maximum Duty Cycle D
MAX
Figure 24. The Fault Timer Duration t
fault
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Figure 25. HV Signal Sampling Period T
sample
NCP12400
Figure 26. VCC T urn−on Threshold Level, VCC Going
Up HV Current Source Stop Threshold V
CC(on)
Figure 28. Internal Current Consumption when
DRV Pin is Unloaded I
CC1
Figure 27. VCC Turn−off Threshold (UVLO) V
CC(off)
Figure 29. HV Current Source Restart Threshold
V
CC(min)
Figure 30. VCC Decreasing Level at which the
Internal Logic Resets V
CC(reset)
Figure 31. Internal Current Consumption when
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DRV Pin is Loaded by 1 nF Capacitance I
CC2
NCP12400
Figure 32. Internal Current Consumption in Skip
Mode I
CC3
Figure 34. Go To Off Mode Timer Duration t
GTOM
Figure 33. FB Pin Voltage Level Above which is
Entered Normal Operating Mode V
ON
Figure 35. Internal Current Consumption in Off
Mode I
CC5
Figure 36. FB Pin Voltage Level Below which is
Entered Off Mode V
OFF
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NCP12400
Figure 37. FB Pin Voltage Thresholds for
Overpower Compensation
Figure 39. Current I
Sourced Out from the
NTC
Fault Pin, allowing Direct NTC Connection
Figure 38. Fault Pin High Threshold for OVP V
Figure 40. Current Flowing Out from CS Pin for
Over Power Compensation @ 365 V at HV Pin
I
OPC(365)
OVP
Figure 41. Fault Pin Low Threshold for OTP V
OTP
NOTE: The OTP resistance maximum and minimum courses are not the guaranteed limits, but the maximum and minimum measured data values from the device characterization.
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Figure 42. The OTP Resistance Threshold R
OTP
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