ON Semiconductor CAT24C64 User manual

64 Kb I2C CMOS Serial EEPROM

CAT24C64

Description

The CAT24C64 is a 64 Kb CMOS Serial EEPROM device,

internally organized as 8192 words of 8 bits each.

It features a 32−byte page write buffer and supports the Standard

(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I

External address pins make it possible to address up to eight

CAT24C64 devices on the same bus.

Features

• Supports Standard, Fast and Fast−Plus I

C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 32−Byte Page Write Buffer

• Hardware Write Protection for Entire Memory

• Schmitt Triggers and Noise Suppression Filters on I

(SCL and SDA)

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Industrial and Extended Temperature Range

• SOIC, TSSOP, UDFN 8−pad and Ultra−thin WLCSP 4−bump

Packages

• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS

Compliant

SCL

A2, A1, A

CAT24C64

SDA

C protocol.

C Bus Inputs

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SOIC−8

W SUFFIX

CASE 751BD

UDFN−8

HU4 SUFFIX

CASE 517AZ

C4C SUFFIX CASE 567JY

TSSOP−8 Y SUFFIX

CASE 948AL

WLCSP−4

PIN CONFIGURATIONS (Top Views)

UDFN (HU4)

A A

SOIC (W), TSSOP (Y),

WP SCL SDA

MARKING

DIAGRAMS

(WLCSP−4)

X = Specific Device Code

= (see ordering information)

Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) W = Production Week Code

For the location of Pin 1, please consult the corresponding package drawing.

A1 A2

SCL

B1 B2

(C4C) (C4U)

WLCSP−4

C4U SUFFIX

CASE 567PB

SDA

WLCSP

Figure 1. Functional Symbol

March, 2021 − Rev. 28

PIN FUNCTION

FunctionPin Name

Device AddressA0, A1, A

Serial DataSDA Serial ClockSCL Write ProtectWP

Power SupplyV GroundV

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

For serial EEPROM in a US8 package, please consult the N24C64 datasheet.

1 Publication Order Number:

CAT24C64/D

CAT24C64

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Storage Temperature –65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V undershoot to no less than −1.5 V or overshoot to no more than V

+ 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

(Note 3) Endurance 1,000,000 Program/Erase Cycles

END

Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods.

3. Page Mode, V

= 5 V, 25°C.

Parameter Min Units

Table 3. D.C. OPERATING CHARACTERISTICS

= 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol

CCR

CCW

OL1

OL2

Parameter Test Conditions Min Max Units

Read Current Read, f

Write Current Write, f

Standby Current All I/O Pins at GND or V

= 400 kHz 1 mA

SCL

= 400 kHz 2 mA

SCL

TA = −40°C to +85°C V

TA = −40°C to +125°C 5

I/O Pin Leakage Pin at GND or V

Input Low Voltage −0.5 VCC x 0.3 V

Input High Voltage VCC x 0.7 VCC + 0.5 V

Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

+ 0.5 V. During transitions, the voltage on any pin may

1 mA

≤ 3.3 V

> 3.3 V

Table 4. PIN IMPEDANCE CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol

Parameter Conditions Max Units

CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF

IWP (Note 5) WP Input Current

VIN < VIH, VCC = 5.5 V 130 mA

VIN < VIH, VCC = 3.3 V 120

VIN < VIH, VCC = 1.8 V 80

IA (Note 5) Address Input Current

(A0, A1, A2) Product Rev F

> V

VIN < VIH, VCC = 5.5 V 50 mA

VIN < VIH, VCC = 3.3 V 35

VIN < VIH, VCC = 1.8 V 25

> V

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods.

5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V

), the strong pull−down reverts to a weak current source.

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CAT24C64

Table 5. A.C. CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)

Fast−Plus

= 1.7 V − 5.5 V

= −405C to +855C

Units

Symbol

SCL

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

Standard

= 1.7 V − 5.5 V

Parameter

Min Max Min Max Min Max

Clock Frequency 100 400 1,000 kHz

START Condition Hold Time 4 0.6 0.25

Low Period of SCL Clock 4.7 1.3 0.45

High Period of SCL Clock 4 0.6 0.40

START Condition Setup Time 4.7 0.6 0.25

Data In Hold Time 0 0 0

Data In Setup Time 250 100 50 ns

Fast

= 1.7 V − 5.5 V

tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns

tF (Note 7) SDA and SCL Fall Time 300 300 100 ns

SU:STO

BUF

Ti (Note 7) Noise Pulse Filtered at SCL

STOP Condition Setup Time 4 0.6 0.25

Bus Free Time Between

4.7 1.3 0.5

STOP and START

SCL Low to Data Out Valid 3.5 0.9 0.40

Data Out Hold Time 100 100 50 ns

100 100 100 ns

and SDA Inputs

SU:WP

HD:WP

WP Setup Time 0 0 0

WP Hold Time 2.5 2.5 1

Write Cycle Time 5 5 5 ms

tPU (Notes 7, 8) Power−up to Ready Mode 1 1 0.1 1 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

is the delay between the time VCC is stable and the device is ready to accept commands.

8. t

Table 6. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x V

Input Rise and Fall Times ≤ 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x V

Output Reference Levels 0.5 x V

Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (V

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< 2.5 V); CL = 100 pF

CAT24C64

Power−On Reset (POR)

Each CAT24C64 incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after V power down into Reset mode when V

exceeds the POR trigger level and will

drops below the

POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the clock signal generated by the Master.

SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.

, A1 and A2: The Address inputs set the device address

that must be matched by the corresponding Slave address bits. The Address inputs are hard−wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. The Address inputs are not available for use with WLCSP 4−bumps.

WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. The WP input is not available for the WLCSP 4−bumps, therefore all write operations are allowed for the device in this package.

transmit or receive, but only the Master can assign those roles.

I2C Bus Protocol

The 2−wire I2C bus consists of two lines, SCL and SDA,

connected to the V

supply via pull−up resistors. The

Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH.

START/STOP Condition

An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH.

Device Addressing

The Master addresses a Slave by creating a START condition and then broadcasting an 8−bit Slave address. For the CAT24C64, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A

, A1 and A0, must match

the logic state of the similarly named input pins. The devices in WLCSP 4−bumps respond only to the Slave Address with A2 A1 A0 = 000 (CAT24C64C4xTR). The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3).

Functional Description

The CAT24C64 supports the Inter−Integrated Circuit

C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24C64 operates as a Slave device. Both Master and Slave can

SCL

SDA

START

CONDITION

Figure 2. Start/Stop Timing

1010

* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 000, CAT24C64C4xTR

Figure 3. Slave Address Bits

Acknowledge

During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5.

STOP

CONDITION

A2A1A0R/W

DEVICE ADDRESS*

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CAT24C64

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

SCL

SU:STA

SDA IN

SDA OUT

BUS RELEASE DELAY (TRANSMITTER)

189

START

ACK DELAY (≤ t

Figure 4. Acknowledge Timing

LOW

HD:STA

HIGH

HD:DAT

LOW

BUS RELEASE DELAY (RECEIVER)

)

SU:DAT

ACK SETUP (≥ t

SU:DAT

SU:STO

BUF

)

Figure 5. Bus Timing

WRITE OPERATIONS

Byte Write

To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W

bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (t

), the SDA output is tri−stated

and the Slave does not acknowledge the Master (Figure 7).

Page Write

The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (t

Acknowledge Polling

As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow−up with a new Read or Write request, rather than wait for the maximum specified Write time (t

) to elapse. Upon receiving a NoACK

response from the Slave, the Master simply repeats the request until the Slave responds with ACK.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1

data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected.

Delivery State

The CAT24C64 is shipped erased, i.e., all bytes are FFh.

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