ON Semiconductor 74FST3400 Technical data

74FST3400

4−Bit, 4−Port Bus Exchange
Switch

The ON Semiconductor 74FST3400 is a 4−bit, 4−port bus exchange

switch. The device is CMOS TTL compatible when operating between

4.0 and 5.5 Volts. The device exhibits extremely low R
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.

Features

• R

 4  Typical

ON

• Less Than 0.25 ns−Max Delay Through Switch

• Nearly Zero Standby Current

• No Circuit Bounce

• Control Inputs are TTL/CMOS Compatible

• Pin−For−Pin Compatible With QS3400, FST3400, CBT3400

• All Popular Packages: SOIC−24, TSSOP−24, QSOP−24

• All Devices in Package TSSOP are Inherently Pb−Free*

BE

C
A
B
D
C
A
B

D
BX
BX

GND

1
2

0

3

0

4

0

5

0

6

1

7

1

8

1

9

1

10

0

11

1

12

Figure 1. 24−Lead Pinout

24
23

22
21
20
19
18
17
16
15
14
13

V
D
B
A
C
D
B
A
C
NC
BX
BX

CC
3
3
3
3
2
2
2
2

3
2

and adds

ON

24

24

24

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1

SOIC−24
DW SUFFIX
CASE 751E

1

TSSOP−24
DT SUFFIX

CASE 948H

1

QSOP−24
QS SUFFIX
CASE 492B

MARKING

DIAGRAMS

24

FST3400

AWLYWW

1

24

FST

3400

ALYW

1

24

FST3400

AWLYYWW

1

TRUTH TABLE

BE

BX

H

L
L

NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care,

NOTE: Hi−Z = High Impedance, i = 0, 1, 2 or 3

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 5

BX

0

X

1

X

BXi = L

BXi = H

BX

BX

A0−3

Hi−Z
C0−3
D0−3

B0−3

Hi−Z
D0−3
C0−3

2

X

3

X

Function

Disconnect

Connect

Exchange

1 Publication Order Number:

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week

PIN NAMES

Pin

BE
Ax, Bx, Cx, Dx Bus A, Bus B, Bus C, Bus D

, OE

OE

1

2

, OE

OE

1

2

, OE

OE

1

2

, OE

OE

1

2

, OE

OE

1

2

OE

, OE

1

2

OE1, OE

2

Bus Enable Input (Active LOW)

Bus Exchange (Bit 0)
Bus Exchange (Bit 1)
Bus Exchange (Bit 2)
Bus Exchange (Bit 3)
No Connect
Ground
Power

Description

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

74FST3400/D

74FST3400

†

A

0

B

0

A

1

B

1

A

2

B

2

A

3

B

3

C

0

D

0

C

1

D

1

C

2

D

2

C

3

D

3

BX

0

BX

1

BX

2

BX

3

BE

Figure 2. Logic Diagram

ORDERING INFORMATION

Device Order Number Package Shipping

74FST3400DW SOIC−24 48 Units / Rail
74FST3400DWR2 SOIC−24 2500 Units / Tape & Reel
74FST3400DT TSSOP−24*

(Pb−Free)

74FST3400DTR2 TSSOP−24*

(Pb−Free)
74FST3400QS QSOP−24 96 Units / Rail
74FST3400QSR QSOP−24 2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

96 Units / Rail

2500 Units / Tape & Reel

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2

74FST3400

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

I

CC

I

GND

T

STG

T
T



MSL Moisture Sensitivity Level 1

F

V

ESD

I

Latchup

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. Tested to EIA/JESD22−A114−A.

2. Tested to EIA/JESD22−A115−A.

3. Tested to JESD22−C101−A.

4. Tested to EIA/JESD78.

DC Supply Voltage 0.5 to 7.0 V

CC

DC Input Voltage 0.5 to 7.0 V

I

DC Output Voltage 0.5 to 7.0 V

O

DC Input Diode Current VI  GND 50 mA

IK

DC Output Diode Current VO  GND 50 mA
DC Output Sink Current 128 mA

O

DC Supply Current per Supply Pin 100 mA
DC Ground Current per Ground Pin 100 mA
Storage Temperature Range 65 to 150 °C
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C

L

Junction Temperature Under Bias 150 °C

J

Thermal Resistance SOIC

JA

TSSOP

QSOP

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

R

ESD Withstand Voltage Human Body Model (Note 1)

Machine Model (Note 2)

Charged Device Model (Note 3)

125
170
200

2000

200

N/A

Latchup Performance Above VCC and Below GND at 85°C (Note 4) 500 mA

°C/W

V

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

V

V

T

t/V Input Transition Rise or Fall Rate Switch Control Input

5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.

Supply Voltage Operating, Data Retention Only 4.0 5.5 V

CC

Input Voltage (Note 5) 0 5.5 V

I

Output Voltage (HIGH or LOW State) 0 5.5 V

O

Operating Free−Air Temperature 40 85 °C

A

Switch I/O VCC = 5.0 V  0.5 V

0

DC

5

ns/V

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74FST3400

V

DC ELECTRICAL CHARACTERISTICS

CC

Symbol Parameter Conditions

V
V
V

I

R

Clamp Diode Resistance IIN = 18mA 4.5 1.2 V

IK

High−Level Input Voltage 4.0 to 5.5 2.0 V

IH

Low−Level Input Voltage 4.0 to 5.5 0.8 V

IL

I

Input Leakage Current 0  VIN  5.5 V 5.5 1.0 A

I

OFF−STATE Leakage Current 0  A, B  V

OZ

Switch On Resistance (Note 6)

ON

VIN = 0 V, IIN = 64 mA 4.5 4 7

CC

(V)

5.5 1.0 A

VIN = 0 V, IIN = 30 mA 4.5 4 7
VIN = 2.4 V, IIN = 15 mA 4.5 8 15
VIN = 2.4 V, IIN = 15 mA 4.0 11 20

I

I

Quiescent Supply Current VIN = VCC or GND, I

CC

Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA

CC

= 0 5.5 3 A

OUT

*Typical values are at VCC = 5.0 V and TA = 25°C.

6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.

AC ELECTRICAL CHARACTERISTICS

C

L

VCC = 4.5−5.5 V VCC = 4.0 V

Symbol Parameter Conditions

t

PHL

t

PLH

t

PZH

t

t

PHZ

t

,

Prop Delay Bus to Bus (Note 7)
Prop Delay, BXn to An, Bn, Cn or Dn 1.0 5.3 6.0

,

Output Enable Time, BXn to An, Bn, Cn or Dn VI = 7 V for t

PZL

Output Enable Time, IOE to An, Bn, Cn or Dn VI = OPEN for t

,

Output Disable Time, BXn to An, Bn, Cn or Dn VI = 7 V for t

PLZ

Output Disable Time, IOE to An, Bn, Cn or Dn VI = OPEN for t

VI = OPEN

PZL

PZH

PLZ

PHZ

7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

Min Max Min Max

1.0 5.8 6.5

1.0 5.8 6.5

1.0 5.3 6.2

1.0 5.3 6.2

TA = 40C to 85C
Min Typ* Max

TA = 40C to 85C

= 50 pF, RU = RD = 500 

0.25 0.25

Unit



Unit

ns

ns

ns

CAPACITANCE (Note 8)

Symbol

C

C

Control Pin Input Capacitance VCC = 5.0 V 6 pF

IN

Port Input/Output Capacitance VCC, OE = 5.0 V 13 pF

I/O

8. TA = 25°C, f = 1 MHz, Capacitance is characterized but not tested.

Parameter Conditions Typ Max Unit

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74FST3400

AC Loading and Waveforms

V

I

FROM

OUTPUT

UNDER

TEST

CL*

NOTES:

1. Input driven by 50  source terminated in 50 .

2. CL includes load and stray capacitance.
*C

= 50 pF

L

Figure 3. AC Test Circuit

t

= 2.5 nS

f

90 %

SWITCH
INPUT

OUTPUT

90 %

10 % 10 %

t

PLH

1.5 V 1.5 V

500 

500 

t

= 2.5 nS

f

3.0 V

1.5 V1.5 V
GND

t

PLH

V

OH

V

OL

ENABLE
INPUT

t

= 2.5 nS

f

OUTPUT

OUTPUT

Figure 4. Propagation Delays

90 %

t

PZL

t

PZH

1.5 V
10 %10 %

1.5 V

1.5 V

90 %

1.5 V

Figure 5. Enable/Disable Delays

t

= 2.5 nS

f

3.0 V

t

PZL

t

PHZL

GND

V

OL

V

OL

V

OH

V

OH

+ 0.3 V

− 0.3 V

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74FST3400

PACKAGE DIMENSIONS

SOIC−24

D SUFFIX

CASE 751E−04

ISSUE E

−T−

SEATING
PLANE

−A−

1324

−B− P12X

M

0.010 (0.25) B

1

D24X

0.010 (0.25) B

M

T

12

J

S

A

S

M

F

X 45

R



C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 15.25 15.54 0.601 0.612
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019

F 0.41 0.90 0.016 0.035

G 1.27 BSC 0.050 BSC

J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
M 0 8 0 8
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS



M

22X

G

K

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6

74FST3400

PACKAGE DIMENSIONS

TSSOP−24
DT SUFFIX

CASE 948H−01

ISSUE A

U0.15 (0.006) T

U0.15 (0.006) T

0.10 (0.004)

−T−

K

K1

S

S

SEATING
PLANE

24X REFK

M

2X L/2

0.10 (0.004) V

24

L

PIN 1
IDENT.

1

S

U

T

S

13

B

−U−

12

A

−V−

C

D

G

N

0.25 (0.010)

H

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 7.70 7.90 0.303 0.311
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8



INCHESMILLIMETERS

−W−

J1

SECTION N−N

J

N

F

DETAIL E

DETAIL E

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7

74FST3400

PACKAGE DIMENSIONS

QSOP−24

QS SUFFIX

CASE 492B−01

ISSUE O

−B−

P

L

0.25 (0.010) T

C

0.25 (0.010) T BA

−A−
R

G

M

U

Q

H x 45

RAD.

0.013 X 0.005
DP. MAX

RAD.

0.005−0.010
TYP

DETAIL E



MOLD PIN
MARK

V

N

8 PL

K

J

M

−T−

D24 PL

M

S S

SEATING
PLANE

F

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.

4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.

5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.

8



8



MILLIMETERS

MIN




0 8 0



INCHES

DIM MAXMINMAX

A 8.56 8.740.337 0.344
B 3.81 3.990.150 0.157
C 1.55 1.730.061 0.068
D 0.20 0.310.008 0.012
F 0.41 0.890.016 0.035
G 0.64 BSC0.025 BSC
H 0.20 0.460.008 0.018
J 0.249 0.1910.0098 0.0075
K 0.10 0.250.004 0.010
L 5.84 6.200.230 0.244
M 0 8 0
N 0 7 0 7
P 0.69 0.940.027 0.037
Q 0.89 DIA0.035 DIA
R 0.89 1.140.035 0.045
U 0.89 1.140.035 0.045
V

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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74FST3400/D

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