OKI MSM82C84A-2RS, MSM82C84A-2GS-K, MSM82C84A-2JS Datasheet

E2O0012-27-X2

¡ Semiconductor MSM82C84A-2RS/GS/JS

¡ Semiconductor

This version: Jan. 1998

Previous version: Aug. 1996

MSM82C84A-2RS/GS/JS

CLOCK GENERATOR AND DRIVER

GENERAL DESCRIPTION

The MSM82C84A-2RS/GS is a clock generator designed to generate MSM80C86A-10 and MSM80C88A-10 system clocks of 8MHz. Due to the use of silicon gate CMOS technology, standby current is only 40 mA (MAX.), and the power consumption is very low with 16 mA (MAX.) when a 8 MHz clock is generated.

FEATURES

• Operating frequency of 6 to 24 MHz (CLK output 2 to 8 MHz)

•3 m silicon gate CMOS technology for low power consumption

• Built-in crystal oscillator circuit

• 3 V to 6 V single power supply

• Built-in synchronized circuit for MSM80C86A-10 and MSM80C88A-10 READY and RESET

• TTL compatible

• Built-in Schmitt trigger circuit (RES input)

• 18-pin Plastic DIP (DIP18-P-300-2.54): (Product name: MSM82C84A-2RS)

• 20-pin Plastic QFJ (QFJ20-P-S350-1.27): (Product name: MSM82C84A-2JS)

• 24-pin Plastic SOP (SOP24-P-430-1.27-K): (Product name: MSM82C84A-2GS-K)

FUNCTIONAL BLOCK DIAGRAM

RES

x x

F/C

EFI

CSYNC

RDY

AEN

RDY

ASYNC

1 2

1

2

Crystal

Oscillator

D

Q

C

RESET

OSC

1 3

S Y N C

1 2

S Y N C

PCLK

CLK

C≠

D

Q

(F1)

CØ

D

(F2)

READY

Q

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¡ Semiconductor MSM82C84A-2RS/GS/JS

PIN CONFIGURATION (TOP VIEW)

18 pin Plastic DIP

24 pin Plastic SOP

CSYNC

PCLK

AEN

RDY

READY

RDY

AEN

CLK

GND

CSYNC

READY

1

2

PCLK

NC

AEN

RDY

NC

RDY2

AEN

NC

CLK

GND

1

2

3

4

5

6

7

8

9

1

2

3

4

1

5

1

6

7

8

9

2

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

18

17

16

15

14

13

12

11

10

V

cc

X

1

X

2

NC

ASYNC

EFI

NC F/C

OSC

NC

RES

RESET

V

CC

X

1

X

2

ASYNC

EFI

F/C

OSC

RES

RESET

20 pin Plastic QFJ

RDY

READY

RDY

AEN

NC

1

CC

AEN

PCLK

CSYNC

3

2

1

4

1

5

6

2

7

2

8

9

10

11

CLK

GND

RESET

V

20

12

RES

1

X

19

13

OSC

X

18

2

ASYNC

17

EFI

16

F/C

15

NC

14

(NC not connected)

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¡ Semiconductor MSM82C84A-2RS/GS/JS

ABSOLUTE MAXIMUM RATINGS

Parameter Unit

Supply Voltage

Input Voltage

Output Voltage

Storage Temperature

Power Dissipation

Symbol

V

CC

V

IN

V

OUT

T

STG

P

D

Condition

Respect

to GND

—

Ta = 25°C

MSM82C84A-2RS/JS

–0.5 to +7

–0.5 to V

–55 to +150

MSM82C84A-2GS

+0.5

CC

+0.5

CC

0.70.8

OPERATING RANGES

Rating

Parameter UnitSymbol

Supply Voltage

Operating Temperature

V

CC

T

op

Range

3 to 6

–40 to +85

RECOMMENDED OPERATING CONDITIONS

Parameter UnitSymbol

Supply Voltage

Operating Temperature

"L" Level Input Voltage V "H" Level Input Voltage (except RES)

"H" Level Input Voltage (RES)

Min.

V

CC

T

op

IL

V

IH

4.5

–40

–0.5

2.2

0.6*V

CC

Typ.

5V

+25

—

Max.

+85

+0.8

V

CC

5.5

+0.5

V

°C

W

V

°C

V

DC CHARACTERISTICS

Parameter

"L" Level Output Voltage (CLK) V

"L" Level Output Voltage (Others)

"H" Output Voltage (CLK) "H" Output Voltage (Others) V

RES Input Hysteresis

Input Leak Current (Except ASYNC)

Input Current (ASYNC)

Standby Supply Current

Operating Supply Current

Input Capacitance C

Note: 1. X1 ≥ V

F/C ≥ V VIH ≥ V

– 0.2 V, X2 £ 0.2 V

CC

– 0.2 V, ASYNC = VCC or open

CC

– 0.2 V, VIL £ 0.2 V

CC

(V

= 5 V ± 10%, Ta = –40 to 85°C)

CC

Symbol Min.

OL

V

OL

V

OH

V

IHR

-V

ILR

I

LI

I

LIA

I

CCS

I

CC

IN

I

= 4 mA

OL

= 2.5 mA

I

OL

I

= –4 mA

OH

I

= –1 mA

OH

0 £ V

Note 1

Condition

£ V

IN

CC

£ V

IN

CC

—

V

CC

0.2*V

–1

—

–0.4

CC

Max.

0.4

Unit

V

—V

—

+1

+10

40

VV

V

mA

mA–100 mA—

16 mAf = 24 MHz, CL= O PF

7

pFf =1 MHz —

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¡ Semiconductor MSM82C84A-2RS/GS/JS

AC CHARACTERISTICS

(1)

= 5 V ± 10%, Ta = –40 to 85°C)

(V

CC

Parameter

EFI "H" Pulse Width

EFI "L" Pulse Width

EFI Cycle Time

Crystal Oscillator Frequency

Symbol

t

EHEL

t

ELEH

t

ELEL

—

Min. Max. Unit

13

17

36

—

6

24

ns

MHz

90% to 90%

10% to 10%

Conditions

—

Set up Time of RDY

or RDY 2 to

1

CLK Falling Edge (Active)

Set up Time of RDY

or RDY 2 to

1

CLK Rising Edge (Active)

Set up Time of RDY

or RDY 2 to

1

CLK Falling Edge (Inactive)

Hold Time of RDY

or RDY 2 to

1

CLK Falling Edge

Set up Time of ASYNC to CLK Falling Edge

Hold Time of ASYNC to CLK Falling Edge

Set up Time of AEN RDY

(RDY 2) Rising Edge

1

Hold Time of AEN

(AEN2) to

1

(AEN2) to

1

CLK Falling Edge

Set up Time of CSYNC to EFI Rising Edge

t

R1VCL

t

R1VCH

t

R1VCL

t

CLR1X

t

AYVCL

t

CLAYX

t

A1R1V

t

CLA1X

t

YHEH

35

50

15

20

—

ns

ASYNC

= High

—

ns

ASYNC

= Low

—

0

—

ns

—

Output Load Capacitance

—

0

—

0

—

ns

—

CLK output

= 100 pF

C

L

Others 30 pF

Hold Time of CSYNC to EFI Rising Edge

CSYNC Pulse Width

Set up Time of RES to CLK Falling Edge

Hold Time of RES to CLK Falling Edge

Input Rising Edge Time

Input Falling Edge Time

t

EHYL

t

YHYL

t

I1HCL

t

CLI1H

t

ILIH

t

IHIL

2 ¥

10

65

20

—

t

ELEL

—

15

ns

15 ns

—

Note: Parameters where timing has not been indicated in the above table are measured at

VL = 1.5 V and VH = 1.5 V for both inputs and outputs.

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¡ Semiconductor MSM82C84A-2RS/GS/JS

AC CHARACTERISTICS

(2)

(V

= 5 V ± 10%, Ta = -40 to 85°C)

CC

Parameter

CLK Cycle Time

CLK "H" Pulse Width

Symbol

t

CLCL

t

CHCL

Conditions

—

Min. Max. Unit

125

1

T

+ 2

CLCL

3

—

ns

CLK "L" Pulse Width

CLK Rising and Falling Edge Times

PCLK "H" Pulse Width

PCLK "L" Pulse Width

Time from READY Falling Edge to CLK Falling Edge

Time from READY Rising Edge to CLK Rising Edge

Delay from CLK Falling Edge to RESET Falling Edge

Delay from CLK Falling Edge to PCLK Rising Edge

Delay from CLK Falling Edge to PCLK Falling Edge

Delay from OSC Falling Edge to CLK Rising Edge

t

CLCH

t

CH1CH2

t

CL2CL1

t

PHPL

t

PLPH

t

RYLCL

t

RYHCH

t

CLIL

t

CLPH

t

CLPL

t

OLCH

—

1.0 V to 3.5 V

—

Output Load Capacitance

CLK Output

= 100 pF

C

L

Others 30 pF

2

3

T

CLCL

T

CLCL

—

-8

—

–5

–20

–15

—

10

—

40

22

ns

Delay from OSC Falling Edge to CLK Falling Edge

Output Rising Edge Time (Except CLK)

Output Falling Edge Time (Except CLK)

t

OLCL

t

OLOH

t

OHOL

—

0.8 V to 2.2 V

2.2 V to 0.8 V

—

2

35

15

ns

Note: Parameters where timing has not been indicated in the above table are measured at

VL = 1.5 V and VH = 1.5 V for both inputs and outputs.

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¡ Semiconductor MSM82C84A-2RS/GS/JS

PIN DESCRIPTION

Pin Symbol

Name

Input/Output

Clock

CSYNC

Synchronization

Single

PCLK

AEN

RDY RDY

READY

CLK

RES

Peripheral Clock

1

Address Enable

2

1

2

Bus Ready

Ready Output Output

Clock Output

Output

Signals

Reset in Input

RESET Reset Output Output

Input

Output

Input

Output

Function

Synchronizing signal for output of in-phase CLK signals when more than one MSM82C84A-2 is used. The internal counter is reset when this signal is at high level, and a high level CLK output is generated. The internal counter is subsequently activated and a 33% duty CLK output is generated when this signal is switched to low level. When this signal is used, external synchronization of EFI is necessary. When the internal oscillator is used, it is necessary for this pin to be kept to be low level.

This peripheral circuit clock signal is output in a 50% duty cycle at a frequency half that of the clock signal.

The AEN

signal enables RDY1, and the AEN2 signal RDY2.

1

The respective RDY inputs are activated when the level applied to these pins is low. Although two separate inputs are used in multi-master systems, only the AEN which enables the RDY input to be used is to be switched to low level in the case of not using multi-master systems.

Completion of data bus reading and writing by the device connected to the system data bus is indicated when one of these signals is switched to high level. The relevant RDY input is enables only when the corresponding AEN is at low level.

This signal is obtained by synchronizing the bus ready signal with CLK. This signal is output after guaranteeing the hold time for the CPU in phase with the RDY input.

This signal is the clock used by the CPU and peripheral devices connected to the CPU system data bus. The output waveform is generated in a 33% duty cycle at a frequency 1/3 the oscillating frequency of the crystal oscillator connected to the X

and X2 pins,

1

or at a frequency 1/3 the EFI input frequency.

This low-level active input is used to generate a CPU reset signal. Since a Schmitt trigger is included in the input circuit for this signal, "power on resetting" can be achieved by connection of a simple RC circuit.

This signal is obtained by CLK synchronization of the input signal applied to RES and is output in opposite phase to the RES input. This signal is applied to the CPU as the system reset signal.

F/C

EFI

X1, X

OSC

Clock Select

External Clock

Crystal Oscillator

2

Connecting Pins

Resonator

Signal

Crystal

Output

Input

Output

This signal selects the fundamental signal for generation of the CLK signal. The CLK is generated from the crystal oscillator output when this signal is at low level, and from the EFI input signal when at high level.

The signal applied to this input pin generaters the CLK signal when F/C is at high level. The frequency of the input signal needs to be three times greater than the desired CLK frequency.

Crystal oscillator connections. The crystal oscillator frequency needs to be three times greater than the desired CLK frequency.

Crystal oscillator output. This output frequency is the same as the oscillating frequency of the oscillator connected to the X pins. As long as a Xtal oscillator is connected to the X

and X2

1

and X2 pins,

1

this output signal can be obtained independently even if F/C is set to high level to enable the EFI input to be used CLK generation purpose.

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