OKI MSM63P238-xxxGS-BK Datasheet

E2E0041-18-95

¡ Semiconductor MSM63P238

This version: Sep. 1998

¡ Semiconductor

MSM63P238

4-Bit Microcontroller with Built-in 16K Word PROM, POCSAG Decoder, and Melody Circuit

GENERAL DESCRIPTION

The MSM63P238 is a CMOS 4-bit microcontroller with a built-in POCSAG (Post Office Code Standardization Advisory Group) decoder, which employs Oki's original nX-4/250 CPU core. The MSM63P238 is a one-time-programmable ROM-version product having one-time PROM (OTP) as internal program memory. The specifications of the MSM63P238 are equal to those of the MSM63238 except for electrical characteristics, packaging (only 80-pin flat package is available for the MSM63P238), and some functions.

FEATURES

The features of the MSM63P238 with an asterisk (*) differ from those of the mask ROM-version MSM63238.

• Rich instruction set 439 instructions

Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control.

• Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register. Data memory bank internal direct addressing mode.

• Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle. Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)

1 ms (@ 2 MHz system clock)

• Clock generation circuit Low-speed clock : 32.768 kHz/38.4 kHz/76.8 kHz crystal oscillator High-speed clock : 2 MHz (Max.) RC or ceramic oscillator select

• Program memory (PROM) space* 16K words Basic instruction length is 16 bits/1 word

• Data memory space 1K nibbles

• External data memory space 64 Kbytes (expandable by using an I/O port)

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¡ Semiconductor MSM63P238

• Stack level Call stack level : 16 levels Register stack level : 16 levels

• POCSAG decoder Data rate : 512 bps/1200 bps/2400 bps User frame : 3 types User address : 6 types Battery saving mode (for controlling intermittent operations of RF receiver)

• I/O ports Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/

high-impedance input

Output ports: Selectable as P-channel open drain output/N-channel open drain output/

CMOS output/high-impedance output

Input-output ports: Selectable as input with pull-up resistance/input with pull-down

resistance/high-impedance input Selectable as P-channel open drain output/N-channel open drain

output/CMOS output/high-impedance output Can be interfaced with external peripherals that use a different power supply than this device uses. Number of ports:

Input port : 1 port ¥ 4 bits Output port : 6 ports ¥ 4 bits Input-output port : 5 ports ¥ 4 bits

1 port ¥ 2 bits

• Melody output function Melody sound frequency : 529 to 2979 Hz Tone length : 63 types Tempo : 15 types Note data : Resides in the program memory Buzzer drive signal output : 4 kHz

• Reset function Reset through RESET pin Power-on reset Reset by low-speed oscillation halt

• Battery check* Low-voltage supply check

Criterion voltage : Can be selected as 2.20 ±0.20 V or 2.80 ±0.30 V

• Power supply backup* Backup circuit (voltage multiplier) enables operation at 1.45 V minimum

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¡ Semiconductor MSM63P238

• Timers and counter 8-bit timer ¥ 4

Selectable as auto-reload mode/capture mode/clock frequency measurement mode Watchdog timer ¥ 1 15-bit time base counter ¥ 1

1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read

• Serial port Mode : UART mode, synchronous mode UART communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps Clock frequency in synchronous mode : 32.768 kHz (internal clock mode), external

clock frequency

Data length : 5 to 8 bits

• Interrupt sources External interrupt : 3 Internal interrupt : 15 (watchdog timer interrupt is a nonmask-

able interrupt)

• Operating voltage* When backup used : VDD = 1.45 to 2.7 V When backup not used : VDD = 2.7 to 5.5 V

• Package*:

80-pin plastic QFP (QFP80-P-1420-0.80-BK) : (Product name: MSM63P238-xxxGS-BK)

xxx indicates a code number.

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¡ Semiconductor MSM63P238

BLOCK DIAGRAM

An asterisk (*) indicates the port secondary function. and indicate that the power is supplied from V V

to the circuits corresponding to signal names inside . (V

DDR

for interface)

TIMING CONTROL

to the circuits corresponding to the signal names inside , and from

DDI

CBR

EBR

nX-4/250

and V

DDI

PROM 16KW

: power supply

DDR

RSP

STACK CAL.S: 16-level REG.S: 16-level

RESET

TST1 TST2 TST3

XTM0 XTM1

XT0 XT1

OSC0 OSC1

TBCCLK*

HSCLK*

XTSEL0 XTSEL1

DDH

DDL

DD2

CB1 CB2

ALU

INSTRUCTION DECODER

RST

TST

OSC

BACKUP

Internal PORT

P0.0-P0.3 P8.2, P8.3 PE.0-PE.3 PF.0-PF.3

INT

C G

RAM

1024N

INT

MIE

TBC

BLD

WDT

BUS CONTROL

DATA BUS

INT

EXTMEM

TIMER

8bit ¥ 4

SIO

MELODY

I/O PORT

INPUT

PORT

OUTPUT

PORT

D0-7*

A0-15*

RD*

WR*

TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK*

RXC* TXC* RXD* TXD*

P8.0, P8.1

P9.0-P9.3

PA.0-PA.3

PB.0-PB.3

PC.0-PC.3

PD.0-PD.3

P1.0-P1.3

P7.0-P7.3

P6.0-P6.3

P5.0-P5.3

P4.0-P4.3

P3.0-P3.3

P2.0-P2.3

SIGIN

BS1 BS2

POCSAG

Dec

DDI

DDR

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¡ Semiconductor MSM63P238

PIN CONFIGURATION (TOP VIEW)

P9.0

P9.1

P9.2

P9.3

PA.0

PA.1

PA.2

PA.3

P4.0

P4.1

P4.2

P4.3

P5.0

P5.2

P5.1

P5.3

(NC) P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3

BS1 BS2

SIGIN

DDR

XT0

XT1 TST1 TST2 TST3

OSC0

OSC1 XTSEL0 XTSEL1

XTM0 XTM1

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2 3 4 5 6 7 8 9

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P8.1 (NC) P8.0 P3.3 P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 PB.3 PB.2 PB.1 PB.0 PC.3 PC.2 PC.1 PC.0 (NC)

(NC)

DD2

DDL

DDH

CB1

CB2

RESET

DDI

PD.0

PD.1

PD.2

PD.3

80-Pin Plastic QFP

Note: Pins marked as (NC) are no-connection pins which are left open.

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¡ Semiconductor MSM63P238

PIN DESCRIPTIONS

The basic functions of each pin of the MSM63P238 are described in Table 1. A symbol with a slash (/) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.

Table 1 Pin Descriptions (Basic Functions)

Function Symbol Type Description

DDR

31 32 13

— — — —

Power supply (+12.5 V) for PROM writing35 Positive power supply Negative power supply Interface power supply for SIGIN, BS1, BS2 Positive power supply pin for external interface

—

(power supply for input, output, and I/O ports) Positive power supply pin for internal logic (internally generated). A capacitor (0.1 mF) should be connected between this pin and V Positive power supply pin for low-speed clock (internally generated)

Power

Supply

DDI

DDL

DD2

Voltage multiplier pin for power supply backup

DDH

—

(internally generated).

A capacitor (1.0 mF) should be connected between this pin and VSS. CB1 Pins to connect a capacitor for voltage multiplier. CB2

XT0 I

29 30

— —

A capacitor (1.0 mF) should be connected between CB1 and CB2.

Clock oscillation pins for POCSAG decoder.

A 32.768 kHz, 38.4 kHz, or 76.8 kHz crystal and capacitor (C XT1 O

XTM0 I

15 23

should be connected to these pins.

Low-speed clock oscillation pins for CPU.

A 32.768 kHz crystal and capacitor (C

Oscillation

XTM1 O

OSC0 I

to these pins.

High-speed clock oscillation pins.

A ceramic resonator and capacitors (C

OSC1 O

oscillation resistor (R

) should be connected to these pins.

Low-speed CPU clock select pins.

16 17 18

These pins are used to select a low-speed CPU clock.

Because these are high impedance inputs, be sure to tie these

pins to V

or VSS.

Pull-down resistors are internally connected to these pins.

The user cannot use these pins.

Test

XTSEL0

XTSEL1

TST1 Input pins for testing. TST2 I TST3

Reset input pin.

Setting this pin to "H" level puts this device into a reset state.

hen, setting this pin to "L" level starts executing an instruction

Reset

RESET I

from address 0000H.

A pull-down resistor is internally connected to this pin.

) should be connected

, CL1) or external

)

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¡ Semiconductor MSM63P238

Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Type Description

Melody

POCSAG

Decoder

Port

MD O Melody output pin (normal phase) BS1 BS2

SIGIN I

P1.0/INT5

P1.1/INT5

P1.2/INT5

P1.3/INT5 53

P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3

P4.0/A0 P4.1/A1 P4.2/A2 P4.3/A3 P5.0/A4 P5.1/A5 P5.2/A6 P5.3/A7 P6.0/A8

P6.1/A9 P6.2/A10 P6.3/A11 P7.0/A12 P7.1/A13 P7.2/A14 P7.3/A15 9

33 10 11

54 55 56 57 58 59 60 61 73 74 75 76 77 78 79 80

2 3 4 5 6 7 8

Battery saving outputs.

Signals to control intermittent operations of RF receiver. Receive data input pin. Input pin for receive data from RF receiver. 4-bit input port. Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit.

4-bit output ports. P-channel open drain output, N-channel open drain output,

CMOS output, or high-impedance output is selectable for each bit.

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¡ Semiconductor MSM63P238

Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Type DescriptionPin

P8.0/RD P8.1/WR

P9.0/D0

P9.1/D1

P9.2/D2

P9.3/D3

PA.0/D4

PA.1/D5

PA.2/D6

PA.3/D7

PB.0/INT0/

TM0CAP/

TM0OVF

PB.1/INT0/

TM1CAP/

TM1OVF

Port

PB.2/INT0/

T02CK

PB.3/INT0/

T13CK

PC.0/INT1/

RXD

PC.1/INT1/

TXC

PC.2/INT1/

RXC

PC.3/INT1/

TXD PD.0 37 PD.1 38 PD.2 39 PD.3 40

62 64 65 66 67 68 69 70 71 72

I/O

2-bit input-output port and 4-bit input-output ports. In input mode, pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit.

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¡ Semiconductor MSM63P238

Table 2 shows the secondary functions of each pin of the MSM63P238.

Table 2 Pin Descriptions (Secondary Functions)

Function Symbol Type DescriptionPin

External

Interrupt

Capture

PB.0/INT0 PB.1/INT0 47 PB.2/INT0 48 PB.3/INT0 49 PC.0/INT1 42 External 1 interrupt input pins. PC.1/INT1 43 PC.2/INT1 44 PC.3/INT1 45 P1.0/INT5 P1.1/INT5 51 P1.2/INT5 52

P1.3/INT5 53 PB.0/TM0CAP 46 PB.1/TM1CAP 47

50 External 5 interrupt input pins.

External 0 interrupt input pins. The change of input signal level causes an interrupt to occur.

The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit.

The change of input signal level causes an interrupt to occur.

The Port C Interrupt Enable register (PCIE) enables or disables an interrupt for each bit.

The change of input signal level causes an interrupt to occur.

The Port 1 Interrupt Enable register (P1IE) enables or disables an interrupt for each bit.

Timer 0 capture trigger input pin.

Timer 1 capture trigger input pin.

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