OKI ML60851A User Manual

E2N0026-18-Y3

Preliminary

This version: Nov. 1998

ML60851A¡ Semiconductor

¡ Semiconductor

ML60851A

USB Device Controller

GENERAL DESCRIPTION

The ML60851A is a general purpose Universal Serial Bus (USB) device controller. The ML60851A provides a USB interface, control/status block, application interface, and FIFOs. The FIFO interface and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn devices such as digital still cameras and image scanners. In addition, Mass Storage devices are also applicable to this device.

FEATURES

• USB 1.0 compliant

• Built-in USB transceiver circuit

• Full-speed (12 Mb/sec) support

• Supports printer device class, image device class, and Mass Storage device class

• Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer

• Built-in FIFOs for control transfer Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)

• Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO) One 64-byte FIFO Two 64-byte FIFOs

• Built-in FIFO for interrupt transfer One 8-byte FIFO

• Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint address

• Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer

• Supports 8 bit/16 bit DMA transfer

•VCC is 3.0 V to 3.6 V

• Supporting dual power supply enables 5 V application interface

• Built-in 48 MHz oscillator circuit

• Package options: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851AGA) 44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851ATB)

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ML60851A

BLOCK DIAGRAM

48 MHz

USB Bus

XIN

XOUT

D+

D–

Oscillator

USB

Transceiver

DPLL

Protocol

Engine

Status/Control

Endpoint FIFO/

8-byte Setup Register

Application

Interface

A7:A0

D15:D0

CS, WR, RD

RESET

INTR

DREQ

DACK

Application

Module

(Local MCU)

ML60851A¡ Semiconductor

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PIN CONFIGURATION (TOP VIEW)

ML60851A¡ Semiconductor

CC3

TEST1

TEST2

XIN

XOUT

RESET

D+

D–

CC5

AD3

AD2

AD1

AD0

444342

121314

INTR

D15

D14

D13

D12

AD5

AD4

VSSV

CC5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

44-Pin Plastic QFP

D+

D–

CC3

TEST1

TEST2

XIN

XOUT

RESET

CC5

AD3

AD2

AD1

AD0

D15

D14

D13

INTR

D12

AD5

AD4

VSSV

CC5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

44-Pin Plastic TQFP

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PIN DESCRIPTION

ML60851A¡ Semiconductor

1, 2

6, 7

4, 5 I Test Pins (normally "L")TEST1, 2

13 to 16,

19 to 22

35 to 38,

41 to 44

25 to 32

Symbol Type

D+, D– USB data

XIN, XOUT

D15:D8

AD7:AD0

A7:A0

DREQ

DACK

ADSEL

RESET

CS RD

INTR

ALE

I/O

—

I/O

Description

Pin for external crystal oscillator

Data bus (MSB)

Data bus (LSB)/address input

Address input

Chip select signal input pin. LOW active

Read signal input pin. LOW active

Write signal input pin. LOW active

Interrupt request signal output pin

DMA request output pin

DMA acknowledge signal input pin

Address latch enable signal input pin

Address input mode select input pin. "H": address/data multiplex

System Reset signal input pin. LOW active

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INTERNAL REGISTERS

Addresses and Names of Registers

Address

A5:A0

00h

01h

02h

03h

04h

08h

09h

0Ah

0Bh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

Read

A7, A6

11b

—

11b

—

11b

—

11b

—

Write

A7, A6

01b

—

01b

—

01b

—

01b

—

01b

—

01b

—

01b

—

Device Address Register

Device State Register

Packet Error Register

Receive FIFO Register

Transmit FIFO Register

Endpoint Packet-Ready Register

Endpoint 0 Receive-Byte Count Register

Endpoint 1 Receive-Byte Count Register

Endpoint 2 Receive-Byte Count Register

Flash Transmit FIFO

System Control

bmRequestType Setup Register

bRequest Setup Register

wValue LSB Setup Register

wValue MSB Setup Register

wIndex LSB Setup Register

wIndex MSB Setup Register

wLength LSB Setup Register

wLength MSB Setup Register

Assertion Select Register

Interrupt Enable Register

Interrupt Status Register

DMA Control Register

DMA Interval Register

Reserved

Endpoint 0 Receive Control Register

Endpoint 0 Receive General Register

Endpoint 0 Receive Payload Register

Reserved

Endpoint 1 Control Register

Endpoint 1 General Register

Endpoint 1 Payload Register

Reserved

ML60851A¡ Semiconductor

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Addresses and Names of Registers (Continued)

Address

A5:A0

30h

31h

32h

33h

34h

35h

36h

37h

00h

01h

02h

00h

01h

03h

Read

A7, A6

11b

—

01b

—

Write

A7, A6

—

01b

—

11b

Endpoint 0 Transmit Control Register

Endpoint 0 Transmit General Register

Endpoint 0 Transmit Payload Register

Endpoint 0 General Register

Endpoint 2 Control Register

Endpoint 2 General Register

Endpoint 2 Payload Register

Reserved

Endpoint 3 Control Register01b11b38h

Endpoint 3 General Register01b11b39h

Endpoint 3 Payload Register01b11b3Ah

Endpoint 0 Receive FIFO data

Endpoint 1 Receive FIFO data

Endpoint 2 Receive FIFO data

Endpoint 0 Transmit FIFO data

Endpoint 1 Transmit FIFO data

Endpoint 2 Transmit FIFO data11b—02h

Endpoint 3 Transmit FIFO data

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(W)

Device Address Register (C0h, 40h)

D7 D6 D5 D4 D3 D2 D1 D0

ML60851A¡ Semiconductor

RFU

Device Address (R/W)

The local MCU writes a device address, which is given by the SET_ADDRESS command form the host computer, into this register. Thereafter, this device processes an only token packet transmitted to the given device address.

Device State Register (C1h, 41h)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Default State (R/W)

Address State (R/W)

Configuration State (R/W)

Suspended State (R)

Remote Wakeup (R/W)

USB Bus Reset Clear

Default, Address, and Configuration States: D2, D1, and D0 are set to 0, 0, and 1 (default states) by reset respectively. Changing the values of this register gives no influence on operation of this device.

Suspended State: This register is asserted when the device enters the suspended state. This register is deaserted by reset or when the device exits the suspended state by a resume signaling from the USB bus.

Remote Wakeup: When this device signals a remote wakeup during the suspended state, this register is asserted by a local MCU. This register is automatically deasserted when the device exits the suspended state by a resume signaling from the USB bus.

USB Bus Reset Status Clear: Writing "1" to this bit causes the interrupt status to be cleared (the USB bus reset interrupt status bit is "0" and the INTR pin is deasserted) while the USB bus reset interrupt is being serviced (when D5, the USB bus reset interrupt status bit, of the interrupt status register is "1" and the INTR pin is asserted). This bit is readable, and when read, its value will be always "0".

Packet Error Register (C2h, –)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Bit Stuff Error (R)

RFU = 0000b

Data CRC Error (R)

Address CRC Error (R)

PID Error (R)

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FIFO Status Register 1 (C3h, –)

pty (R)

)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

RFU = 0000b

FIFO Status Register 2 (C4h, –)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

RFU = 0000b

ML60851A¡ Semiconductor

Receive FIFO0 Full (R)

Receive FIFO0 Empty (R)

FIFO1 Full (R)

FIFO1 Em

Transmit FIFO0 Full (R)

Transmit FIFO0 Empty (R)

FIFO2 Full (R)

FIFO2 Empty (R)

FIFO3 Full (R)

FIFO3 Em

Endpoint Packet-Ready Register (C8h, 48h)

D7 D5 D4 D3 D2 D1 D0D6

RFU

EP0 Receive Packet Ready (R/Reset)

EP1 Receive Packet Ready (R/Reset)

EP2 Receive Packet Ready (R/Reset)

EP0 Transmit Packet Ready (R/Set)

EP1 Transmit Packet Ready (R/Set)

EP2 Transmit Packet Ready (R/Set)

EP3 Transmit Packet Ready (R/Set

Receive Packet Ready: When a valid packet arrives at an endpoint, this bit is automatically set and the endpoint is locked. When "1" is written in this register, Receiver Packet Ready is reset and the endpoint is unlocked. (This bit also is set to "0".) When DMA is enabled, EP1 Receive Packet Ready is automatically reset after all the data in EP1 is read during DMA transfer.

Transmit Packet Ready: When "1" is written in this register, the Transmit Packet Ready is set and the packet in the corresponding endpoint is transmitted. Transmit Packet Ready is automatically reset when the ACK handshake is returned from the host. When DMA is enabled, EP1 Transmit Packet Ready is automatically set after the data written in EP1 reaches the maximum packet size during DMA transfer.

The value of this register remains unchanged when "0" is written in this register.

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Endpoint 0 Receive Byte Count Register (C9h, –)

D7 D6 D5 D4 D3 D2 D1 D0

ML60851A¡ Semiconductor

RFU

EP0 Byte Count (R)

Endpoint 1 Receive Byte Count Register (CAh, –)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

EP1 Byte Count (R)

Endpoint 2 Receive Byte Count Register (CBh, –)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

EP2 Byte Count (R)

Flash Transmit FIFO (–, 4Eh)

D7 D6 D5 D4 D2 D1 D0D3

000 0

In case EP1 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP1 is cleared and Packet

Ready at EP1 is reset by the WRITE pulse.

In case EP2 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP2 is cleared and Packet

Ready at EP2 is reset by the WRITE pulse.

In case EP3 is set as a transmission endpoint, when "1" is

written in this bit, the FIFO at EP3 is cleared and Packet

Read

at EP3 is reset by the WRITE pulse.

Note: Please clear all FIFOs at the same time, otherwise some of them may not be cleared.

System Control (–, 4Fh)

D7 D6 D5 D4 D2 D1 D0D3

When "1" is written in this bit, the ML60851A is reset

by the WRITE pulse.

Oscillation Stop Command

Oscillation Stop Command: Writing 1010b to D7 to D4, (writing A0h into this register) causes the oscillator circuit of the ML60851A to be deactivated and go into the standby mode. When oscillation is stopped, reading and writing into the register is possible but reading and writing into FIFO is not possible. Asserting the RESET pin restarts oscillation.

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bmRequestType Setup Register (D0h, –)

D7 D6 D5 D4 D2 D1 D0D3

ML60851A¡ Semiconductor

Type (R)

Data Transfer Direction (R)

Recipient (R)

bRequest Setup Register (D1h, –)

D7 D6 D5 D4 D2 D1 D0D3

Specific Request (R)

• wValueLSB Setup Register (D2h, –) D7:D0 = LSB of Word Size Field (R)

• wValueMSB Setup Register (D3h, –) D7:D0 = MSB of Word Size Field (R)

0 = Device

1 = Interface

2 = Endpoint

3 = Others

4 to 31 = Reserved

0 = Standard

1 = Class

2 = Vendor

3 = Reserved

0 = Host to device

1 = Device to host

• wIndexLSB Setup Register (D4h, –) D7:D0 = LSB of Word Size Field (R)

• wIndexMSB Setup Register (D5h, –) D7:D0 = MSB of Word Size Field (R)

• wLengthLSB Setup Register (D6h, –) This field defines the length of data that is transferred in the second stage (data stage) of control transfer. (R)

• wLengthMSB Setup Register (D7h, –) This field defines the length of data that is transferred in the data stage of control transfer. (R)

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Assertion Select Register (DAh, 5Ah) (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Assertion

of DACK

Assertion of DREQ

Interrupt Enable Register (DBh, 5Bh) (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

Assertion of INTR

0 = Active LOW (Initial value)

1 = Active HIGH

0 = Active LOW (Initial value)

1 = Active HIGH

0 = Active HIGH (Initial value)

1 = Active LOW

Setup Ready Interrupt Enable

EP1 Packet Ready Interrupt Enable

EP2 Packet Ready Interrupt Enable

EP0 Receive Packet Ready Interrupt Enable

EP0 Transmit Packet Ready Interrupt Enable

USB Bus Reset Interrupt Enable

Suspended State Interrupt Enable

EP3 Packet Ready Interrupt Enable

ML60851A¡ Semiconductor

Initial value of D0 is 1. Initial values of D1 to D7 are 0.

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ML60851A¡ Semiconductor

Interrupt Status Register (DCh, 5Ch) (R)

D7 D6 D5 D4 D3 D2 D1 D0

Setup Ready Interrupt Status (R)

EP1 Packet Ready Interrupt Status (R)

EP2 Packet Ready Interrupt Status (R)

EP0 Receive Packet Ready Interrupt Status (R)

EP0 Transmit Packet Ready Interrupt Status (R)

USB Bus Reset Interrupt Status

Suspended State Interrupt Status (R)

EP3 Packet Ready Interru

t Status

Setup Ready Interrupt Status: Equivalent to Setup Ready at (F3h) described later when the corresponding Interrupt Enable bit is asserted.

EP1 Packet Ready Interrupt Status: Equivalent to EP1 Receive Packet Ready (the complement of EP1 Transmit Packet Ready when EP1 is set for transmitter) at (C8h) described before when the corresponding Interrupt Enable bit is asserted.

EP2 Packet Ready Interrupt Status: Equivalent to EP2 Receive Packet Ready (the complement of EP2 Transmit Packet Ready when EP2 is set for transmitter) at (C8h) described before when the corresponding Interrupt Enable bit is asserted.

EP0 Receive Packet Ready Interrupt Status: Equivalent to EP0 Receive Packet Ready at (C8h) described before when the corresponding Interrupt Enable bit is asserted.

EP0 Transmit Packet Ready Interrupt Status: Equivalent to the complement of EP0 Transmit Packet Ready at (C8h) described before when the corresponding Interrupt Enable bit is asserted.

USB Bus Reset Interrupt Status: This bit is set to "1" at USB bus reset when the D5 bit of the interrupt enable register (DBh) is "1". To return this bit back to "0", "1" should be written to the D5 bit of the device states register.

Suspended State Interrupt Status: Equivalent to Suspended State Register at (C1h) described before when the corresponding Interrupt Enable bit is asserted.

EP3 Packet Ready Interrupt Status: When the D7 bit of the interrupt enable register (DBh) is "1", the complement of the D7 bit of the endpoint packet ready register (C8h) is being copied.

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ML60851A¡ Semiconductor

DMA Control Register (DDh, 5Dh) (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Transfer

Mode

Transfer

Size

Byte

Count

Address

Mode

DMA

Enable

0 = Disables DMA Transfer (Initial value)

1 = Enables DMA Transfer for EP1

0 = Single Address Mode (Initial value)

1 = Dual Address Mode 0 = (Initial value)

1 = Inserts EP1 receive byte count into the top byte or

top word of the transfer data. (Note 1)

0 = Byte (8 bits) (Initial value)

1 = Word (16 bits) (Note 2)

0 = Single Transfer Mode (Initial value)

1 = Demand Transfer Mode

(Note 1) When 16-bit mode is set, the upper byte of the top word is 00h. (Note 2) When 16-bit mode is set and the packet size is an odd-number byte, the upper byte of the

last word is 00h.

DMA Interval Register (DEh, 5Eh) (R/W)

D7 D6 D5 D4 D3 D2 D1 D0

This register specifies a DMA transfer interval between de-assertion and re-assertion of DREQ in Single Transfer mode. The interval is specified between 0 and 255 (bit times). The initial value is 0.

1-bit time = 1/12 MHz (= 84 ns)

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Endpoint 0 Receive Control Register (E0h, –)

(R)

D7 D6 D5 D4 D3 D2 D1 D0

ML60851A¡ Semiconductor

RFU

00000RFU

Configuration Bit (R)

Transfer Type (R)

Endpoint Address

Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from a host computer to this EP is received. The packet is ignored when this bit is deasserted ("0"). This bit is deasserted by system reset and is asserted by USB reset (both D+ and D- are 0s for more than 2.5 ms).

Endpoint 0 Receive General Register (E1h, –)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Data Sequence

Toggle Bit (R)

Endpoint 0 Receive Payload Register (E2h, 62h)

D7 D6 D5 D4 D3 D2 D1 D0

RFU

Maximum Packet Size (R/W)

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