OKI ML54051 User Manual
DATA SHEET ¡
ML54051
NAND Flash Memory Controller
PRELIMINARY
SECOND EDITION
ISSUE DATE : JAN. 1999
E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
Table of Contents
1. FEATURES...........................................................................................................2
2. BLOCK DIAGRAM ............................................................................................... 2
3. PIN SPECIFICATIONS ........................................................................................ 3
3.1 Host Interface (PCMCIA) .................................................................................... 3
3.2 NAND Flash Memory Interface .......................................................................... 4
3.3 External SRAM Interface .................................................................................... 5
3.4 Extended Bus Interface ...................................................................................... 5
3.5 Other Interfaces .................................................................................................. 5
3.6 Power Supply....................................................................................................... 6
3.7 Pin Totals ............................................................................................................. 6
3.8 Pin Configuration ................................................................................................ 7
4. FUNCTIONS ........................................................................................................ 8
5. SECTOR FORMATTER AND SEQUENCER....................................................... 9
5.1 Data Formats ....................................................................................................... 9
5.1.1 Data Format Within Sector ........................................................................ 9
5.1.2 Data Format Within Port .......................................................................... 10
5.1.3 Substitute Management Information Format ........................................... 11
5.2 Write Sector Commands .................................................................................. 12
5.2.1 Dual Port Control ..................................................................................... 12
5.2.2 Block Control ........................................................................................... 12
5.3 Substitute Processing (Defect Management)................................................. 13
5.3.1 Substitute Management Information Format Processing ........................ 13
5.3.1.1 Sector Management .............................................................................. 13
5.3.1.2 Substitute Management Information Management............................... 14
5.4 Generation of Substitute Management Information ...................................... 14
5.5 Substitute Processing....................................................................................... 15
5.6 Substitute Destination Detection Processing ................................................ 16
6. ATA REGISTERS ...............................................................................................17
6.1 Memory Mapped Configuration ....................................................................... 17
6.2 I/O Mapped 16 Contiguous Registers Configuration .................................... 18
6.3 Primary I/O Mapped Configuration ................................................................. 18
6.4 Secondary I/O Mapped Configuration ............................................................ 19
6.5 True IDE Mapped Configuration ...................................................................... 19
6.6 ATA Registers .................................................................................................... 20
6.6.1 Data Register (Write/Read) ...................................................................... 20
6.6.2 Error Register (Read Only) ....................................................................... 20
6.6.3 Feature Register (Write Only) ................................................................... 20
6.6.4 Sector Count Register (Write/Read) ........................................................ 20
6.6.5 Sector Number Register (Write/Read) ..................................................... 21
6.6.6 Cylinder Low Register (Write/Read) ......................................................... 21
6.6.7 Cylinder High Register (Write/Read) ........................................................ 21
6.6.8 Drive Head Register (Write/Read) ............................................................ 21
6.6.9 Status Register & Alternate Status Register (Read Only) ........................ 22
6.6.10 Device Control Register (Write Only) ....................................................... 22
6.6.11 Command Register (Write Only) .............................................................. 22
7. PCMCIA INTERFACE ........................................................................................ 23
7.1 ATA Commands (Standard).............................................................................. 23
7.2 Commands for CompactFlash ......................................................................... 24
7.3 Vendor-Unique Commands.............................................................................. 24
7.4 Card Information Structure .............................................................................. 24
7.5 Identify Information........................................................................................... 24
7.6 Number of Installed Memory Chips and CHS Structure................................ 25
7.7 Modes................................................................................................................. 27
7.7.1 Memory Mapped ..................................................................................... 27
7.7.2 I/O Mapped 16 Contiguous Registers ..................................................... 27
7.7.3 Primary I/O Mapped ................................................................................ 27
7.7.4 Secondary I/O Mapped ........................................................................... 27
7.7.5 True IDE ................................................................................................... 27
8. CHIP MODES .................................................................................................... 28
8.1 Types .................................................................................................................. 28
8.2 Settings .............................................................................................................. 28
8.3 Pin Assignment.................................................................................................. 28
9. ELECTRICAL CHARACTERISTICS .................................................................. 29
9.1 Absolute Maximum Ratings ............................................................................. 29
9.2 Recommended Operating Conditions............................................................. 29
9.3 DC Characteristics ............................................................................................ 29
10. BUS SPECIFICATIONS .....................................................................................30
10.1 I/O Mode ........................................................................................................... 30
10.2 Bus Timing Specifications ............................................................................... 30
10.3 Power ON/OFF, Reset, Busy Timing .............................................................. 30
11. PACKAGE DIMENSIONS ..................................................................................31
12. APPLICATION EXAMPLES ...............................................................................32
E2F0018-29-13
Preliminary
¡ Semiconductor ML54051
¡ Semiconductor
This version: Jan. 1999
Previous version: Oct. 1998
ML54051
NAND Flash Memory Controller
The ML54051 is a controller that integrates into a single chip a host interface that conforms to
PCMCIA, an interface to a buffer used for data transfer, the necessary functions to control NAND
memory, and a microcontroller.
Internal 256 byte RAM is provided for storage of the card information structure (CIS). Also,
128KB of SRAM may be connected as a buffer for data transfer.
A maximum of 16 chips of 64 Mbit or larger NAND flash memory can be controlled when the chip
is used as stand-alone. If a decoder circuit is externally added, a maximum of 64 chips can be
controlled.
CompactFlashTM is a trademark of SanDisk Corporation.
1/33
¡ Semiconductor ML54051
1. FEATURES
• Single chip controller with internal microcontroller (min. 4 cycles/instruction execution)
• Operating voltage: 3.3 V, Interface voltage: 3.3 V/5 V
• Internal 256B RAM for card information structure (CIS) storage
• Conforms to PC card standard - PC card ATA specification
• Auto-sleep mode support
• True IDE Mode support
• ECC system by BCH code (3-bit random error correction is possible for user data and ECC data)
• Substitute control function (defect management function)
• Debug mode support
• External buffer (128KB SRAM) control is possible
• High-speed operation via dual port bus control
• Low power consumption due to single chip controller
• Control of multiple NAND flash memories (64MB to 512MB) is possible
Chip stand-alone : 16 pcs max.
Chip and external decoder circuit : 64 pcs max.
• 144-pin LQFP package (LQFP144-P-2020-0.50-K)
2. BLOCK DIAGRAM
PCMCIA
I/F
Host I/F
PCMCIA
ATA
CIS
External
CPU Bus
ECC
MPU
RAMROM
RAM Arbiter
External
SRAM
Media I/F
NAND
Flash
Bus
2/33
¡ Semiconductor ML54051
p
3. PIN SPECIFICATIONS
Refer to Section 12, “Application Examples” for specific connection examples.
3.1 Host Interface (PCMCIA)
Signal Name
ha [10:0]
hd [15:0]
hcen [2:1]
hiordn
hiowrn
hoen
hwen
hregn
hirqn
hstschgn
hinpackn
hiois16n O 1 16-bit address enable signal (when the card is configured as an I/O card,
hwaitn O 1 Wait signal
hspkr B 1 Audio digital waveform signal
hrst I 1 Reset signal
hcseln I/(O) 1 Cable select signal (used only in True IDE Mode, GND: Master, X: Slave)
Type
I
B
I
I
I
I
I
I
O
O
O
Pin Count
11
16
2
1
1
1
1
1
1
1
1
Total 42
Description
Address bus (A10 is MSB, A0 is LSB)
Data bus (D15 is MSB, D0 is LSB)
Card enable signal (hcen1 controls even addresses and hcen2 controls odd
addresses. The combination of ha0, hcen1 and hcen2 allows even/odd
addresses to be accessed by hd[7:0].)
I/O read signal (control signal to read data from ATA registers)
I/O write signal (control signal to write data to ATA registers)
Output enable signal
Write enable signal
Register select & I/O Enable signal
Interrupt request signal (when the card is configured as an I/O card)
Card status change signal (signal to change the status of the configuration
status register)
Input port acknowledge signal (acknowledge signal during I/O read)
this signal indicates that 16-bit addresses are enabled)
ins
* In an external CPU connection mode, hcseln functions as a control signal (xint) for the
extended bus.
I: Input, O: Output, B: Bidirectional
3/33
¡ Semiconductor ML54051
3.2 NAND Flash Memory Interface
Signal Name
maio [7:0]
macle
maale
maren
mawen
marbn
mbio [7:0]
mbcle
mbale
mbren
mbwen
mbrbn I 1 Port B ready/busy signal (signal to check internal status of device)
mctl I 1 Chip enable signal mode select (mcen[7:0] control)
mcen [7:0] O 8 Chip enable signals
mwpn O 1 Write protect signal (signal to forcibly prohibit write and erase operations)
Type
B
O
O
O
O
I
B
O
O
O
O
Pin Count
8
1
1
1
1
1
8
1
1
1
1
Total 36 pins
Description
Port A I/O bus
Port A command latch enable signal (signal to control latching of an
operation command into a device)
Port A address latch enable signal (signal to control latching of an address
or input data into a device)
Port A read enable signal
Port A write enable signal (signal to latch data into a device)
Port A ready/busy signal (signal to check internal status of device)
Port B I/O bus
Port B command latch enable signal (signal to control latching of an
operation command into a device)
Port B address latch enable signal (signal to control latching of an address
or input data into a device)
Port B read enable signal
Port B write enable signal (signal to latch data into a device)
mct1 = 0 : Chip enable signal
mct1 = 1 : Chip select and chip enable signals
* mcen[7:0] performs 2 types of operations depending upon the mctl signal.
If mctl = 0, mcen[7:0] functions as the chip enable signals.
If mctl = 1, mcen[5:1] functions as the chip select signals and mcen[0] functions as the chip
enable signal.
In the latter case, mcen[5:1] and mcen[0] must be connected to an external decoder and
mcen[7:6] are not used.
* In an external CPU connection mode, mctl and mcen[7:6] function as control signals (xpsen,
xrst, xclk, respectively) for the extended bus.
4/33
¡ Semiconductor ML54051
p
p
3.3 External SRAM Interface
Signal Name
ra [16:0]
rd [7:0] B 8 Data bus for external SRAM
rren O 1 Read enable signal for external SRAM
rwen O 1 Write enable signal for external SRAM
rcen O 1 Chip enable signal for external SRAM
TypeOPin Count
17
Total 28
ins
Address bus for external SRAM
Description
3.4 Extended Bus Interface
The extended bus interface is a signal line for the ML54051’s internal microcontroller. The
extended bus interface is used for purposes such as debugging.
Signal Name
xah [15:8]
xad [7:0] B 8 Address/data bus for extended bus
xrd B 1 Read signal for extended bus
xwr B 1 Write signal for extended bus
xale B 1 Address latch enable signal for extended bus
xpsen I (1) Program store enable signal for extended bus
xint O (1) Interrupt signal for extended bus
xrst O (1) Reset signal for extended bus
xclk O (1) Clock signal for extended bus
TypeBPin Count
8
Total 19 pins
Address bus for extended bus
Description
* In an external ROM connection mode, xah, xad, xrd, xwr, and xale are used to connect to
external ROM.
3.5 Other Interfaces
Signal Name
txd/pcfg [0]
rxd/pcfg [1] I 1
porn I 1 Power-on-reset signal (connect to power monitor circuit)
xin I 1 Clock I/O (connect a crystal oscillator between xin and xout)
xout O 1
TypeBPin Count
1
Total 5
ins
Serial data I/O and chip mode setting
Description
* The chip mode is determined depending upon the status of pcfg[1:0] when the porn signal
rises.
pcfg[1:0] = 11 : Normal mode
pcfg[1:0] = 01 : External CPU connection mode
pcfg[1:0] = 10 : External ROM connection mode
pcfg[1:0] = 00 : Test mode (normally not used)
5/33
¡ Semiconductor ML54051
3.6 Power Supply
Signal Name
VDD-CORE
VSS-CORE DC 2
VDD DC 4 Power supply for I/O pad
VSS DC 6
TypeDCPin Count
2
Total 14 pins
Power supply for core
3.7 Pin Totals
Host Interface 42
NAND Flash Memory Interface 36
External SRAM Interface 28
Extended Bus Interface 19
Other Interfaces 5
Power Supply 14
Total 144
Description
6/33
¡ Semiconductor ML54051
3.8 Pin Configuration
porn
mwpn
mctl
rxd
txd
ra12
ra13
ra11
ra14
ra10
ra15
ra9
ra16
ra8
rwen
rd4
rd3
rd5
VDD-CORE
VDD
VSS
rd2
rd6
rd1
rd7
rd0
rren
rcen
ra7
ra0
ra6
ra1
ra5
ra2
ra4
ra3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
macle
maale
maren
mawen
marbn
VSS
xout
xin
maio0
maio7
maio1
maio6
maio2
maio5
VDD
maio3
maio4
mcen0
VSS-CORE
mcen1
mcen2
mcen3
mcen4
mcen5
mcen6
mcen7
VSS
mbcle
mbale
mbren
mbwen
mbrbn
mbio0
mbio7
mbio1
mbio6
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3839404142434445464748495051525354555657585960616263646566676869707172
37
ML54051
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
hd3
hd11
hd4
hd12
hd5
hd13
hd6
VSS
hd14
hd7
hd15
hce1n
hce2n
ha10
hoen
hiordn
ha9
hiowrn
VSS-CORE
ha8
hwen
ha7
hirqn
ha6
hcseln
VDD
ha5
ha4
hrst
ha3
hwaitn
ha2
hinpackn
ha1
hregn
ha0
mbio2
mbio5
mbio3
mbio4
VDD
xrdn
xale
VSS
xad7
xad6
xad5
xad4
xad3
xad2
xad1
xad0
xa15
144-Pin Plastic LQFP
xa14
xa13
VDD-CORE
xa12
xa11
xa10
xa9
xa8
xwrn
hd10
hd9
VSS
hiois16n
hd2
hd8
hd1
hstschgn
hd0
hspkr
7/33
¡ Semiconductor ML54051
4. FUNCTIONS
(1) Sector Formatter and Sequencer
The sector formatter and sequencer control the logical format of the NAND flash memory
and efficiently perform defect management (substitute processing).
(2) PCMCIA Interface
The PCMCIA interface conforms to PCMCIA-ATA specification. Since True IDE Mode is
also supported, the general usefulness of this interface is increased.
(3) Chip Modes
An external ROM connection mode for the ML54051’s internal microcontroller and an
external CPU connection mode are supported. With these modes, evaluation can be
performed efficiently.
(4) Auto-Sleep Mode
If there is no access from the host over a specific period of time, operation automatically
transfers to the sleep mode.
(5) Dual Port Bus Control Mode
When erasing data or writing the same data, two port buses (Port A, Port B) can be utilized
simultaneously for high-speed operation.
8/33
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