OKI 8c Troubleshooting Manual

OKIP AGE 8c Color LED Page Printer

T roubleshooting Manual with Component Parts List

ODA/OEL/INT

1999. 2. 9 Rev.1

40985501TH Rev.1 1 / 157

CONTENTS

1. OUTLINE ............................................................................................................ 3

2. TOOLS................................................................................................................ 3

3. CIRCUIT DESCRIPTION.................................................................................... 4

3.1 CU (controller unit : PCR)......................................................................... 4

3.1.1 Outline ...................................................................................................................... 4

3.1.2 CPU and Memory ..................................................................................................... 7

3.1.3 Reset Control............................................................................................................ 9

3.1.4 EEPROM Control ................................................................................................... 10

3.1.5 Centronics Parallel Interface................................................................................... 12

3.1.6 Operator Panel Control........................................................................................... 13

3.2 PU (Printer Unit : PX4) ........................................................................... 14

3.2.1 Outline ....................................................................................................................14

3.2.2 CPU, Memory and LSI............................................................................................ 16

3.2.3 Reset Control.......................................................................................................... 18

3.2.4 EEPROM Control ................................................................................................... 19

3.2.5 LED Head Control .................................................................................................. 21

3.2.6 Motor Control.......................................................................................................... 24

3.2.7 Fuser Temperature Control..................................................................................... 30

3.2.8 Fan Motor Control................................................................................................... 33

3.2.9 Sensor Supervision ................................................................................................ 34

3.2.10 Cover Open ............................................................................................................ 35

3.2.11 Power Supply Interface........................................................................................... 36

3.2.12 Option (2nd paper feeder) Interface ....................................................................... 37

3.2.13 Power Supply Board ............................................................................................... 38

3.3 PCR-PX4 I/F........................................................................................... 42

3.3.1 Outline ....................................................................................................................42

3.3.2 Video I/F ................................................................................................................. 43

3.3.3 Command Interface ................................................................................................ 45

4. TROUBLESHOOTING...................................................................................... 48

4.1 Troubleshooting Table............................................................................ 48

4.2 Troubleshooting Flowchart ..................................................................... 60

5. CIRCUIT DIAGRAM ......................................................................................... 66

6. COMPONENT PARTS LIST........................................................................... 104

40985501TH Rev.1 2 /

1. OUTLINE

This manual has been written to provide guidance for troubleshooting of the OKIPAGE 8c Printer (primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the printer. Read the maintenance manual for this printer P/N 40029803TH if necessary.

Notes:

1. The power supply board containing a high voltage power supply is dangerous. From the viewpoint of the safety standards, the local repairing of a defective board is not allowed. Also, pay attention to the fact that a function can be rarely recovered by replacing a fuse when it is burnt.

2. Replacement of CPU(NR4700) and LSIs (IMEM & IIF) on the PCR PCB is not recommended. If these chips are founded to be defective, board replacement is suggested.

2. TOOLS

For troubleshooting the printer, the tools listed below may be needed in addition to general maintenance tools.

Tool Remarks Oscilloscope Soldering iron

Extension Cord Used for drawing PCR PCB out for PX4

Frequency response 100 MHz or higher A slender tip type, 15-20 Watt

PCB evaluation

40985501TH Rev.1 3 /

3. CIRCUIT DESCRIPTION

3.1 CU (controller unit : PCR)

3.1.1 Outline

The PCR PCB controls the reception of data transferred through a host I/F and processes command analysis, bit image development, raster buffer read. It also controls the operator panel. The block diagram of the entire OKIPAGE 8c including PCR PCB and details of PCR PCB are shown in Figure. 3-1 and 3-2.

(1) Reception control

The OKIPAGE 8c has one centronics parallel I/F. The centronics parallel I/F port can specify the following item when set by the control panel:

PARALLEL SPEED: HIGH/MEDIUM BI-DIRECTION : ENABLE/DISABLE I-PRIME : OFF/ON

An interface task stores all data received from the host into a receive buffer first.

(2) Command analysis processing

The OKIPAGE 8c has the following emulation mode. Color Laser Jet : Hewlett Packard

PostScript Level 3 : Adobe An edit task fetches data from the receive buffer, analizes commands, and reconstructs the

data in such a way that print data are aligned from up to down and from right to left; then it writes the resultant data into a page buffer with such control data as print position coordinate, font type, etc. added.

(3) Font Processing

When one page editing is finished, a developing task makes an engine start and fetches data from the page buffer synchronizing with a printing operation; then it developes the fetched data to a bit map as referring to data from a character generator, and writes the resultant data into the raster buffer (of band buffer structure).

(4) Raster buffer read.

As controlling the engine operation, an engine task sends data from the raster buffer to the LED head.

40985501TH Rev.1 4 /

AC-IN AC switch

Crimp-style terminal

PXL board

PXL

Ejection sensor

LED head: Y M C K

Discharging lamp: Y M C K

Heat roller

thermistor

Backup roller

thermistor

Heater unit

SUMi card x 4

PD6 board

Y600 14P

YPOW 12P

M600 14P

MPOW 12P

C600 14P

CPOW 12P

K600 14P

KPOW 12P

HEAD1 13P HEAD2 14P HEADPOW 12P HEAD3 15P

FF form

sensor

Toner sensor x 4

ID sensor x 4

Low-voltage power supply

6P'

JST3P

FAN 1

FAN 2

Oil PAD MSW

motor

Paper supply sensor board

FF Pos MSW

PXM board

40095001YU

REG.POS

sensor

Resist

motor

Y-IDU

motor

M-IDU

motor

C-IDU

motor

K-IDU

motor

Belt

motor

Heat

motor

PXF board

JODEN 8P

FSENS 8P

TONER

14P

PXFIF 30P

OPTION 7P

PENDTNR 6P

PX4 board

2nd tray

(option)

Form end

sensor

Waste toner

sensor

YIDREG

MCKID

12P

HETBELT

HEAD3

15P

HEAD2

14P

HEAD1

13P

HEADPOW

12P

FF 12P

PXFIF 30P

HVOLT 16P COVOPN 2P PSIZE 6P

High-voltage power supply

PXC board

Form size detector

Cover open

MSW

PCR

Operator

panel

PCO

board

PU 40P

72PX2

PS SIMM

72PX2

D-RAM SIMM

64P

OKI HSP

36P

Paralle

CUIF 40P

POWER 30P

THE.RM 6P

RSENS 7P

Interlock switch

UPDOWN

12P

40985501TH Rev.1 5 /

Figure 3-1 Block Diagram

MPU Memory controller ROM, PS SIMM

SysAD

SysCmd

Control

9 5

SysAD SysCmd Control

A D

Control

22 64 11

16244

16245

NMI

INTO

NR4700 LMQ-100

ExtReg

INT1 INT2

Reset

ColdReset

VCCOK

ModeIn

ModeClock

MasterClock

(Not installed)

External Agent

SysAD

SysCmd

Control

INT

REQ

ACK AUX

CLK

RST

1 1

9 5 1 1

1 1 1 1

1 1 2

uPD94704

NMI

S1-001-F6

INT

CLK RST

Interface controller

SysAD SysCmd Control ExtReq INT

ColdReset VCCOK ModeIn ModeClk

uPU66044 GN-014-LMU

BusReq BusAck AUX

Reset

A D

Control

WDATA

FSYNC

Control

PU I/F OP I/F

EEPD EEPCLK EEPCS0

EEPCS1

PCO

PCI

D A C

11 64 25

8 4 4

9 4

1 1 1

8 7

16 18 12

16244

D-RAM Max 80M

16245 16244

Engine WDATA ESYNC Control

244

Operator panel

244

EE-PROM #1

DI CLK DO CS

EE-PROM #2

DI CLK DO CS

74ACT1284 Bi-Centro

74ALS244

OKI HSP

Host I/F(Not installed)

PS -SIMM

OSC

Reset circuit

DIP SW

CLK

RSTIN

(TE6135 (6137), 16550, 53C80)

Figure 3-2 Block Diagram

40985501TH Rev.1 6 /

3.1.2 CPU and Memory

(1) CPU (NR4700LMQ-100) (MIPS R4700)

CPU core : RISC CPU (MIPS R3000 compatible) CPU clock : 100 MHz Data bus clock : 50 MHz Data bus width: Exterior 64 bits, Interior 64 bits

(2) ROM (HP Color LaserJet emulation)

ROM capacity : 8 Mbytes (16-Mbit mask or OTP ROM four pieces) ROM type : 16 Mbits (1M x 16 bits) Access time : 100 ns

(3) PostScript SIMM (Adobe PostScript emulation)

ROM capacity : 8 Mbytes [(16 Mbit ROM two pieces)x 2SIMMs] ROM type : 16 Mbits (1M x 16 bits) Access time : 100 ns

(4) Resident RAM

RAM capacity : 16 Mbytes (16 Mbit D-RAM eight pieces) RAM type : 16 Mbits (1 M x 16 bits) Access time : 60 ns

(5) Option RAM (SIMM: two slots)

RAM capacity : Max. 32 Mbytes (4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes) Access time : 60 ns, 70 ns, 80 ns Note that only the product for ODA has been mounted with 16 Mbytes (8 Mbytes x 2) SIMM as a resident.

The block diagram of CPU and memory circuits is shown in Figure 3-3.

40985501TH Rev.1 7 /

DRAM01~04 (RAS0, CAS7~0)

Resident RAM

(16M Bytes)

Option SIMM

(Resident SIMM:

Only ODA)

Mask ROM (8M Bytes)

Flash ROM (2M Bytes)

PS SIMM

(8M Bytes)

DRAM11~14 (RAS2, CAS7~0)

SIMM0 H, L (RAS4, 5, CAS7~0)

CAS01~04 (CS0)

PSIMMH, L (CS2)

IFL1~4 (CS3)

(NR4700 LMQ-100)

CPU

(Memory Control LSI)

IMEM

(I/F Control LSI)

IIF

Control signals

AD [63 : 0]

CMD [7 : 0]

16244

16245 x 4

16Mbit DRAM x 4

16MbitMask ROM x 4

16MbitMask ROM x 2 x 2

4Mbit Flash ROM x 4

16Mbit DRAM x 4

Figure 3-3 Block Diagram of CPU & Memory

40985501TH Rev.1 8 /

3.1.3 Reset Control

When power is turned on, a RESET-N signal is generated by the reset control IC (7705) which checks +5V power supply.

OKI HSP

IMEM

PD94704)

(

RT1

CT1

+5V

R620

25V

1.5

4.7K

+5V

16V

CP13

C583

Power ON

25V

0.1

7 2 3

8 4

SEN IN CT

V+ GND

IRST1

7705

WRST

RST

VREF

6 5 1

+5V

R590

25V

C586

0.1

(

PD66044)

4.7K

C50

100p 50V

IIF

HWRESET-N

Power OFF

RESET-N

COLDRST-N

Flash ROMs

CPU

(NR4700)

+5V

HWRESET-N

COLDRST-N

RESET-N

+3V

40985501TH Rev.1 9 /

3.1.4 EEPROM Control

The NM93C46LN is an electrical erasable/programmable ROM of 64-bit x 16-bit configuration and the NM93C66N is an electrical erasable/programmable ROM of 256-bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial I/O port (EEPDAT-P) in serial transmission synchronized with a clock signal from the I/F control LSI(IIF).

IIF

(

PD66044)

EEPDAT-P

154

EEPCS0-P

150

EEPCS1-P

165

EEPCLK-P

151

NM93C46LN

DI DO

NM93C66N

DI DO

E2ROM1 (PCR-PCB)

PSIMMH (PS SIMM)

The EEPROM operates in the following instruction modes

Instruction Start Bit

Operation

Code

NM93C46LN

Address

NM93C66N

: Option

Data

Read (READ) Write Enabled (WEN) Write (WRITE) Write All Address (WRAL) Write Disabled (WDS) Erase Chip Erasable (ERAL)

1 1 1 1 1 1 1

10 00 01 00 00 11 00

A5 to A0

11XXXX 11XXXXXX

A5 to A0 A7 to A0

01XXXX 01XXXXXX 00XXXX 00XXXXXX

A5 to A0 A7 to A0

10XXXX 10XXXXXX

A7 to A0

D15 to D0 D15 to D0

40985501TH Rev.1 10 /

CS SK

Write cycle timing (WRITE)

101

HIGH-Z

A5/A7

Read cycle timing (READ)

A4/A6

A1 A0 D15

D14

Min. 450 ns

STATUS

D1 D0

Max. 500 ns

BUSY READY

Max. 10 ms

DI DO

HIGH-Z

11 0

A5/A7 A4/A6

A1 A0

A5/A7

A4/A6

D1 D00

40985501TH Rev.1 11 /

3.1.5 Centronics Parallel Interface

The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (CENTDATA1-P to CENTDATA8-P) from the parallel port at the fall of STB-N signal. Furthermore, it makes the store processing of received data into a receive buffer terminate within a certain fixed time and outputs an ACK-N signal, setting the BUSY-P signal to OFF.

IIF

(

PD66044)

87, 88, 91 to 96

PDATA [7 : 0]

STB-N BSY-P

ACK-N

SEL

FAULT

INIT-N

SELIN-N

AUTOFEED

IC16, 17

IC17

IC16

2 to 9

+5V 14

FU2

CENT

DATA8-P DATA1-P STB-N

BUSY-P

ACK-N PE-P

SEL-P

FAULT-N

IPRIME-N SELIN-N AUTOFEED-N

+5V

PARALLEL DATA (DATA BITs 1 to 8)

0.5 µs min.

nStrobe

0.5 µs min.

0.5 µs max.

Busy

0 min.

nAck

0.5 µs to 10 µs 0 min.

40985501TH Rev.1 12 /

3.1.6 Operator Panel Control

The operator panel consists of the following circuits.

PCR- PCO-

IIF

(µPD66044)

I/F Control LSI

OPCMD-P 146

OPSTS-P 147

OPSCLK-P 149

OPLOAD-N 150

IC19

3 4

CN1PANEL

1 6

Flexible

Cable

(1) BU6152S (LSI)

This LSI is connected to a clock synchronous serial port of the I/F Control LSI (IIF). It controls switch data input, LED data output and LCD data input/output according to the commands given by the I/F Control LSI. The I/F Control LSI sends the 2-byte (16-bit) command (OPCMDP) together with the shift clock signal (OPSCLK-N) to the Operator Panel Control LSI and then makes a predetermined input/output control if the command decoded by the Operator Panel Control LSI is found to be a normal command.

BU6152S

Operator Panel

Control LSI

DB4~DB7

RS R/W

LED

44780 LCD Control Driver

Zebra Rubber

LCD

On receiving a command sent from the I/F Control LSI, the Operator Panel Control LSI, synchronizing with the serial clock of the command, returns a 2-byte command response to the I/F Control LSI.

OPCMD-P

OPSCLK-N

OPSTS-P

OPLOAD-N

bit 0 bit 15

Command

bit 0

bit 15

Command response

40985501TH Rev.1 13 /

3.2 PU (Printer Unit : PX4)

3.2.1 Outline

PU section executes controls such as LED head control, stepping motor control, high-voltage control, video I/F control, command I/F control and fusing control, and performs color image printing. The block diagram is shown in Fig3-4.

(1) The print data stored in the video memory is loaded to the LED head control and transferred

through each line to the LED head to light LEDs. This causes a static latent image to form on the photoconductive drum I.

(2) Stepping motor control: executes ID up/down control for the supply, carriage and ejection of

print media

(3) High-voltage power supply control: executes ON/OFF control for various kinds of power supply

units through serial interface. (4) Fusing control: executes the control of fusing temperature according to the type of media. (5) Video I/F control: receives the print data from the controller section (CU) and stores it to the

video memory. (6) Command I/F control: executes the receiving control of commands from the controller section

(CU) and sending control of status signals.

40985501TH Rev.1 14 /

PD6-PCB

Low Voltage

Power Supply

High Voltage

Power Supply

Belt Unit

Y-ID Unit

M-ID Unit

C-ID Unit B-ID Unit

Second Tray

(option)

Fuser Unit

LED Head Eraser Lamp

M M M

M M

Y-ID M-ID C-ID B-ID BELT HEATER REGIST FRONT

Stepping Motor

PX4-PCB

PXF-PCB

VIDEO I/F

COMMAND I/F

AC 120V/230V

• Outlet sensor

• Inlet sensor1

• Inlet sensor2

• Write sensor

• Paper width sensor

• Humidity sensor

• Temperature sensor

• Paper end sensor

• Toner sensors (Y.M.C.K)

• ID Up/Down sensors (Y.M.C.K)

• Waste toner full sensor

• Waste box sensor

• Paper size sensor

• Oil roller sensor

• FF home sensor

• FF Paper end sensor

• Pinch roller up/down sensor

From CU

40985501TH Rev.1 15 /

Figure 3-4 Block Diagram

3.2.2 CPU, Memory and LSI

(1) CPU (MSM65524)

CPU core : nX8 (Oki original)

CPU clock : 10 MHz

Data bus clock : 50 MHz

Data bus width: 8 bits (2) ROM (27512)

ROM capacity : 64K bytes

ROM type : 512K bits, 8 bits

Access time : 150 ns (3) Resident RAM (62256)

RAM capacity : 32K bytes (Static RAM)

Access time : 70 ns (4) VIDEO RAM (658512)

RAM capacity : 512K bytes (Pseudo Static RAM)

Access time : 70 ns

The block diagram of CPU, memory and LSI circuits is shown in Figure 3-5.

40985501TH Rev.1 16 /

Analogy input (Temperature, Humidity, etc)

CPU BUS

VIDEO I/F

EEPROM

NM93C66N

VIDEO MEM

HM658512

CPU

MSM65524

(include AD Converter)

ROM

27512

Y HEAD I/F (3.3V)

M HEAD I/F (3.3V)

C HEAD I/F (3.3V)

B HEAD I/F (3.3V)

RAM

62296

MT DRIVER

MTD2005F

MT DRIVER

MTD2005F

LSI

(MB87D113)

MT DRIVER

MTD2005F

RESET

CLOCK

High voltage Power Supply Serial I/F (2CH)

Input Port Output Port

Stepping Motor x 8

Figure 3-5 Block Diagram of CPU, Memory & LSI

40985501TH Rev.1 17 /

3.2.3 Reset Control

When power is turned on, a RST-N signal is generated by the rising sequence of +5V power supply.

+5V

C21

25V 0.1

0VL

PST592

VCC GND

IC3

OUT

R61

0.1W 3.3K 2

IC12

LS07

+5V

R63

0.1W 1K 21

Ω

22K

Q11

+5VD

Q12

IC12

+5V

0.1W 3.3K

R60

RST-N

+5V

RST-N

+5VD

LS07

Power OFF

Power ON

Approx. 110ms Approx. 20ms

40985501TH Rev.1 18 /

3.2.4 EEPROM Control

The NM93C66N is an electrical erasable/programmable ROM of 256-bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial I/O port (out DATA-P and IN DATA-P) in serial transmission synchronized with a clock signal from the CPU(IC10).

IC10

(MSM65524)

OUT DATA-P

EEPRMCS0-P

INDATA-P

EEPRMCLK-P

NM93C66N

DI DO

The EEPROM operates in the following instruction modes

Instruction Start Bit

Read (READ) Write Enabled (WEN) Write (WRITE) Write All Address (WRAL) Write Disabled (WDS)

Operation

Code

1 1 1 1 1

10 00 01 00 00

Address

NM93C66N

11XXXXXX

01XXXXXX 00XXXXXX

A7 to A0

IC2 (PX4-PCB)

Data

D15 to D0 D15 to D0

Erase Chip Erasable (ERAL)

1 1

11 00

A7 to A0

10XXXXXX

40985501TH Rev.1 19 /

CS SK

Write cycle timing (WRITE)

101

HIGH-Z

Read cycle timing (READ)

A1 A0 D15

D14

Min. 450 ns

STATUS

D1 D0

Max. 500 ns

BUSY READY

Max. 10 ms

DI DO

HIGH-Z

11 0

A7 A6

A1 A0

D1D14D15 D00

40985501TH Rev.1 20 /

3.2.5 LED Head Control

LSI PIN

LSI IC1

(MB87D113)

PX4-PCB

Signal HDDTY3 HDDTY2 HDDTY1 HDDTY0 STBY3 STBY2 STBY1 STBY0 HDCK0 HDLD0 HDDTM3 HDDTM2 HDDTM1 HDDTM0 STBM3 STBM2 STBM1 STBM0 HDCK1 HDLD1 HDDTC3 HDDTC2 HDDTC1 HDDTC0 STBC3 STBC2 STBC1 STBC0 HDCK2 HDLD2 HDDTK3 HDDTK2 HDDTK1 HDDTK0 STBK3 STBK2 STBK1 STBK0 HDCK3 HDLD3

Lsi Pin IC1-136 IC1-135 IC1-134 IC1-133 IC1-144 IC1-143 IC1-142 IC1-141 IC1-137 IC1-140 IC1-149 IC1-148 IC1-147 IC1-146 IC1-157 IC1-155 IC1-154 IC1-153 IC1-151 IC1-152 IC1-161 IC1-160 IC1-159 IC1-158 IC1-169 IC1-168 IC1-167 IC1-166 IC1-164 IC1-165 IC1-173 IC1-172 IC1-171 IC1-170 IC1-181 IC1-180 IC1-179 IC1-178 IC1-176 IC1-177

CN2CN1 CN3 HEAD CN

PD6-PCB

CN1 HEAD1-4 HEAD1-3 HEAD1-2 HEAD1-1 HEAD1-10 HEAD1-9 HEAD1-8 HEAD1-7 HEAD1-5 HEAD1-6 HEAD2-1 HEAD1-13 HEAD1-12 HEAD1-11 HEAD2-7 HEAD2-6 HEAD2-5 HEAD2-4 HEAD2-2 HEAD2-3 HEAD2-11 HEAD2-10 HEAD2-9 HEAD2-8 HEAD3-3 HEAD3-2 HEAD3-1 HEAD2-14 HEAD2-12 HEAD2-13 HEAD3-9 HEAD3-8 HEAD3-7 HEAD3-6 HEAD3-15 HEAD3-14 HEAD3-13 HEAD3-12 HEAD3-10 HEAD3-11

CN2 HEAD1-4 HEAD1-3 HEAD1-2 HEAD1-1 HEAD1-10 HEAD1-9 HEAD1-8 HEAD1-7 HEAD1-5 HEAD1-6 HEAD2-1 HEAD1-13 HEAD1-12 HEAD1-11 HEAD2-7 HEAD2-6 HEAD2-5 HEAD2-4 HEAD2-2 HEAD2-3 HEAD2-11 HEAD2-10 HEAD2-9 HEAD2-8 HEAD3-3 HEAD3-2 HEAD3-1 HEAD2-14 HEAD2-12 HEAD2-13 HEAD3-9 HEAD3-8 HEAD3-7 HEAD3-6 HEAD3-15 HEAD3-14 HEAD3-13 HEAD3-12 HEAD3-10 HEAD3-11

Y HEAD

M HEAD

C HEAD

K HEAD

CN3 Y600-5 Y600-4 Y600-8 Y600-7 Y600-14 Y600-13 Y600-12 Y600-11 Y600-2 Y600-10 M600-5 M600-4 M600-8 M600-7 M600-14 M600-13 M600-12 M600-11 M600-2 M600-10 C600-5 C600-4 C600-8 C600-7 C600-14 C600-13 C600-12 C600-11 C600-2 C600-10 K600-5 K600-4 K600-8 K600-7 K600-14 K600-13 K600-12 K600-11 K600-2 K600-10

HEAD CN Y-5 Y-4 Y-8 Y-7 Y-14 Y-13 Y-12 Y-11 Y-2 Y-10 M-5 M-4 M-8 M-7 M-14 M-13 M-12 M-11 M-2 M-10 C-5 C-4 C-8 C-7 C-14 C-13 C-12 C-11 C-2 C-10 K-5 K-4 K-8 K-7 K-14 K-13 K-12 K-11 K-2 K-10

40985501TH Rev.1 21 /

PX4-PCB

LED Head

IC1

(MB87D113)

HDDTX0

HDDTX1

HDDTX2

HDDTX3

HDCLKX

HDLDX

STBX0

STBX1

STBX2

STBX3

Head Lsi

with EEPROM

Driver IC

Driver IC Driver IC

Driver IC

X=Y, M, C or B

Data is transferred to the head unit starting with the data at the left end of the paper in the synchronous serial transfer mode using the HDCKX signal as the sync signal.

The total number of LEDs in the head unit is 4992. The data for the driver latches causes the corresponding LEDs to light only during the time when the STBXn signal is output. There are four STBXn signals (STBX0, STBX1, STBX2 and STBX3), each of which controls the corresponding driver for 1248 LEDs (4992/4).

The four STBXn signals must be output within the time when the LEDs for one line continue to emit light. After the data is moved to the latches by the STBXn signal, the transfer of the data of the next line can be started.

40985501TH Rev.1 22 /

The timing chart for the outline of this operation is shown below.

HDCKX HDDTX0 HDDTX1 HDDTX2

59 2 6 10 4986 4990 3

11 4987 4991

4985

4989

✰

The LED lights when the head data is HIGH.

HDDTX3

HDCKX HDDTX0 HDDTX1 HDDTX2 HDDTX3

HDLDX STBX0 STBX1 STBX2 STBX3

4 8 12 4988 4992

Each figure denotes the dot position taking the left end bit position as "1".

Print activation timing for the 1st line

LEDs

1-1248

lit

LEDs

1249-2496

lit

LEDs

2497-3744

lit

Print activation timing for the 2nd line

LEDs

3745-4992

lit

Print activation timing for the final line

40985501TH Rev.1 23 /

3.2.6 Motor Control

OKIPAGE 8c controls the paper flow by eight motors (Four ID Motors, Hopping Motor, Front feed Motor, Belt Motor).

(1) ID motor

The four ID motors for rotate four color IDs are driven by the driver IC according to the control signal from the IC1 (MB87D113). The IC8 (62354) is a Digital to Analogy Converter controlled by CPU (IC10 : MSM65524) and its output voltage controls several ID motor current.

40985501TH Rev.1 24 /

IC1 (MB87D113)

189 188

111

YIDON

190

192 191

MIDON

193

195 194

CIDON

196

200 199

KIDON

201

YIDPHA YIDPHB

IDMOTON-N

MIDPHA MIDPHB

CIDPHA CIDPHB

KIDPHA KIDPHB

26 17

27 16

23 20

26 17

27 16

23 20

26 17

27 16

23 20

26 17

27 16

23 20

IC15

MTD2005F

IC16

MTD2005F

IC17

MTD2005F

IC18

MTD2005F

Y-ID REG 3 7

8 12

3 7

8 12

3 7

8 12

3 7

8 12

1 3

2 4

9 11

10 12

5 7

6 8

1 3

2 4

Y-ID motor

M-ID motor

C-ID motor

K-ID motor

IDREF IDMOTON-N

XIDON

XIDPHA

XIDPHB

Rotation

IC8

(62354)

Power ON

IDREF

Initial process

Stop

T0 T1 T2

T4 T5 T6

Reverse rotation

Forward rotation speed : T0 to T3= (Print operation) Reverse rotation speed : T4 to T7= (ID up operation)

40985501TH Rev.1 25 /

(2) Regist motor

The Regist motor is driven by the driver IC14 according to the control signal from the LSI (IC1: MB87D113). The Regist motor current is controlled by the DAC (IC8 : 62354).

REGON

REGPHA

REGPHB

PX4-PCB

IC1

(MB87D113)

IC8

(62354)

T0 T1 T2 T3

REGPHA

203

REGPHB

202

REGON

204

REGREF

27, 16

23, 20

IC14

(MTD2005F)

YIDREG

T4 T5 T6 T7

Regist

Motor

Rotation

Stop

Forward rotation

Reverse rotation

(Hopping operation) (Regist operation)

Hopping Operation speed: T0 to T3 = Regist Operation speed: T4 to T7 =

40985501TH Rev.1 26 /

(3) Front feed motor

The Front feed motor is driven by the driver IC13 according to the controll signal from the LSI (IC1 : MB87D113). The Regist motor current is controlled by the DAC (IC8 : 62354)

FFON

FFPHA

FFPHB

PX4-PCB

IC1

(MB87D113)

IC8

(62354)

T0 T1 T2 T3

211

208

212

FFPHA

FFPHB

FFON

FFREF

27, 16

23, 20

IC13

(MTD2005F)

Front Feed

Motor

T4 T5 T6 T7

Rotation

Stop

Forward rotation

Reverse rotation

(Paper feed operation) (Pinch roller up/down operation)

Paper feed operation speed: T0 to T3 = Pinch roller up/down operation speed: T4 to T7 =

40985501TH Rev.1 27 /

(4) Belt motor

The Belt motor is driven by the driver IC19 according to the control signal from the LSI (IC1 : MB87D113). The Belt motor current is controlled by the DAC (IC8 : 62354).

BELTON

BELTPHA

BELTPHB

PX4-PCB

IC1

(MB87D113)

IC8

(62354)

T0 T1 T2 T3

BELTPHA

BELTPHB

BELTON

BELTREF

27, 16

23, 20

IC19

(MTD2005F)

HETBELT

Belt Motor

Rotation

Forward rotation

(Belt feed operation)

Belt feed speed: T0 to T3 = µs

Reverse rotationStop

40985501TH Rev.1 28 /

(5) Heat motor

The Heat motor is driven by the driver IC20 according to the control signal from the LSI (IC1 : MB87D113). The Heat motor is controlled by the DAC (IC8 : 62354).

HETON

HETPHA

HETPHB

PX4-PCB

IC1

(MB87D113)

IC8

(62354)

T0 T1 T2 T3

HEATPHA

206

HEATPHB

205

HEATON

207

HEATREF

27, 16

23, 20

IC20

(MTD2005F)

HETBELT

Heat Motor

T4 T5 T6 T7

Rotation

Stop

Forward rotation

(Heating operation)

Heating speed: T0 to T3 = µs

Reverse rotation

40985501TH Rev.1 29 /

3.2.7 Fuser Temperature Control

For the temperature control by heater control, the variation in the resistance of the thermistor is A/ D converted in and the resultant digital value is read and transferred to the CPU. The CPU turns on or off the HEATON-N signal according the value of the signal received from to keep the temperature constant.

Immediately after the power is turned on, the thermistor is checked for shortcircuit and breakdown. If the thermistor is shorted, the A/D converted value shows an extremely high temperature, so that the shortcircuit can be detected. If the breakdown of the thermistor occurs, the A/D converted value shows the normal temperature. In this case, the thermistor breakdown can be detected by the sequence shown at the end of this section. If the heater is overheated, 5V supply is turned off by detecting that the resistance of the thermistor exceeds the predetermined value.

PX4-PCB

Heat roller Thermistor

: TH

Back-up roller

thermistor

: TB

Thermostat

Heater

THERM

+5V

Interlock SW

Thermistor

Thermistor breakdown

detect

circuit

Thermistor breakdown

detect

circuit

IC10

(MSM65524)

AD7

AD6

Low Voltage Power Supply

Bus

IC1

(MB87D113)

+5V

HEATON-N

237

Q13

+5VD

Q10

AC120V/230V

Power SW

40985501TH Rev.1 30 /

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