NXP 74LVC1G08GF, 74LVC1G08GM, 74LVC1G08GN, 74LVC1G08GS, 74LVC1G08GV Schematic [ru]

...

74LVC1G08

Single 2-input AND gate

Rev. 10 — 29 June 2012 Product data sheet

1. General description

The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time. This device is fully specified for partial power-down applications using I

The I the device when it is powered down.

circuitry disables the output, preventing the damaging backflow current through

OFF

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V  High noise immunity  Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)  24 mA output drive (V  CMOS low power consumption  Latch-up performance  250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V  Multiple package options  Specifie d from 40 C to +85 C and 40 C to +125 C

=3.0V)

OFF

NXP Semiconductors

mna113

B A

mna114

mna221

3. Ordering information

74LVC1G08

Single 2-input AND gate

Table 1. Ordering information

Type number Package

T emperature

Name Description Version

range

74LVC1G08GW 40 Cto+125C TSSOP5 plastic thin shrink small outline package; 5 leads;

SOT353-1

body width 1.25 mm 74LVC1G08GV 40 Cto+125C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G08GM 40 Cto+125C XSON6 plastic extremely thin small outline package;

SOT886

no leads; 6 terminals; body 1  1.45  0.5 mm 74LVC1G08GF 40 C to +125 C XSON6 plastic extremely thin small outline package;

SOT891

no leads; 6 terminals; body 1  1  0.5 mm 74LVC1G08GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;

SOT1115

6 terminals; body 0.9  1.0  0.35 mm 74LVC1G08GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;

SOT1202

6 terminals; body 1.0  1.0  0.35 mm 74LVC1G08GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin

SOT1226 small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm

4. Marking

Table 2. Marking

Type number Marking code

74LVC1G08GW VE 74LVC1G08GV V08 74LVC1G08GM VE 74LVC1G08GF VE 74LVC1G08GN VE 74LVC1G08GS VE 74LVC1G08GX VE

[1]

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

Product data sheet Rev. 10 — 29 June 2012 2 of 19

NXP Semiconductors

74LVC1G08

GND Y

001aab638

74LVC1G08

001aab639

GND

n.c.

Transparent top view

74LVC1G08

001aae978

GND

n.c.

Transparent top view

6. Pinning information

6.1 Pinning

Fig 4. Pin configu ration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886

74LVC1G08

Single 2-input AND gate

Fig 6. Pin configu ration SOT891, SOT1115 and

Fig 7. Pin configuration SOT1226 (X2SON5)

SOT1202

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

TSSOP5 and X2SON5 XSON6

B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected V

5 6 supply voltage

74LVC1G08

GND

aaa-003023

Transparent top view

4AY

Product data sheet Rev. 10 — 29 June 2012 3 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

7. Functional description

Table 4. Function table

[1]

Input Output A B Y

LLL LHL HLL HHH

[1] H = HIGH voltage level; L = LOW voltage level

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

GND

tot

stg

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When V [3] For TSSOP5 and SC-74A packages: above 87.5 C the value of P

For XSON6 and X2SON5 package: above 118 C the value of P

supply voltage 0.5 +6.5 V input clamping current VI < 0 V 50 - mA input voltage

[1]

0.5 +6.5 V output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode

Power-down mode

output current VO = 0 V to V

[1][2]

0.5 VCC + 0.5 V

[1][2]

0.5 +6.5 V

- 50 mA supply current - 100 mA ground current 100 - mA total power dissipation T

= 40 C to +125 C

amb

[3]

- 250 mW storage temperature 65 +150 C

= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

derates linearly with 4.0 mW/K.

tot

derates linearly with 7.8 mW/K.

tot

Product data sheet Rev. 10 — 29 June 2012 4 of 19

NXP Semiconductors

9. Recommended operating conditions

74LVC1G08

Single 2-input AND gate

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

amb

t/V input transition rise and fall rate V

supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - V

= 0 V; Power-down mode 0 - 5.5 V

ambient temperature 40 - +125 C

= 1.65 V to 2.7 V - - 20 ns/V

= 2.7 V to 5.5 V - - 10 ns/V

10. Static characteristics

Table 7. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

input leakage current

Min Typ

VCC = 1.65 V to 1.95 V 0.65V

= 2.3 V to 2.7 V 1.7 - - 1.7 - V

= 2.7 V to 3.6 V 2.0 - - 2.0 - V

= 4.5 V to 5.5 V 0.7V

VCC = 1.65 V to 1.95 V - - 0.35V

= 2.3 V to 2.7 V - - 0.7 - 0.7 V

= 2.7 V to 3.6 V - - 0.8 - 0.8 V

= 4.5 V to 5.5 V - - 0.3V

VI=VIHor V

IO= 100 A;

VCC 0.1 - - VCC 0.1 - V

[1]

Max Min Max

- - 0.65V

- - 0.7V

-0.35VCCV

-0.3VCCV

VCC= 1.65 V to 5.5 V

= 4mA; VCC = 1.65 V 1.2 - - 0.95 - V

= 8mA; VCC = 2.3 V 1.9 - - 1.7 - V

= 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V

= 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V

= 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V

VI=VIHor V

IO=100A;

- - 0.10 - 0.10 V

VCC= 1.65 V to 5.5 V

=4mA; VCC = 1.65 V - - 0.45 - 0.70 V

=8mA; VCC = 2.3 V - - 0.30 - 0.45 V

=12mA; VCC = 2.7 V - - 0.40 - 0.60 V

=24mA; VCC = 3.0 V - - 0.55 - 0.80 V

=32mA; VCC = 4.5 V - - 0.55 - 0.80 V

VI = 5.5 V or GND;

=0Vto5.5V

- 0.1 5-100 A

-V

Product data sheet Rev. 10 — 29 June 2012 5 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

Table 7. Static characteristics

…continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

[1]

Max Min Max

OFF

power-off

Min Typ

VCC = 0 V; VIor VO=5.5V - 0.1 10 - 200 A leakage current

I

supply current VI = 5.5 V or GND; IO = 0 A;

= 1.65 V to 5.5 V

additional supply current

input

per pin; VCC = 2.3 V to 5.5 V;

VI=VCC 0.6 V; IO=0 A

VCC= 3.3 V; VI = GND to V

-0.110 - 200A

- 5 500 - 5000 A

-5- - -pF

capacitance

[1] All typical values are measured at VCC= 3.3 V and T

amb

=25C.

11. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

propagation delay A, B to Y; see Figure 8

power dissipation capacitance

VCC= 1.65 V to 1.95 V 1.0 3.4 8.0 1.0 10.5 ns

= 2.3 V to 2.7 V 0.5 2.2 5.5 0.5 7.0 ns

= 2.7 V 0.5 2.5 5.5 0.5 7.0 ns

= 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6.0 ns

= 4.5 V to 5.5 V 0.5 1.7 4.0 0.5 5.5 ns

VI = GND to VCC; VCC= 3.3 V

Min Typ

[2]

[3]

-16- - -pF

[1]

Max Min Max

[1] Typical values are measured at T [2] t

is the same as t

[3] C

Product data sheet Rev. 10 — 29 June 2012 6 of 19

is used to determine the dynamic power dissipation (PDin W).

P f

C V N = number of inputs switching;

(C

 V

D=CPD

= input frequency in MHz;

= output frequency in MHz;

= output load capacitance in pF;

= supply voltage in V;

 V

 fo) = sum of outputs.

and t

PLZ

 fi N+(CL V

PZL

=25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

amb

 fo) where:

NXP Semiconductors

mna614

PHL

PLH

A, B input

Y output

GND

12. AC waveforms

Measurement points are given in Table 9.

and VOH are typical output voltage levels that occur with the output load.

Fig 8. The input A, B to output Y propagation delays

74LVC1G08

Single 2-input AND gate

Table 9. Measurement points

Supply voltage Input Output V

1.65 V to 1.95 V 0.5V

2.3 V to 2.7 V 0.5V

CC CC

0.5V

2.7V 1.5V 1.5V

3.0V to 3.6V 1.5V 1.5V

4.5 V to 5.5 V 0.5V

0.5V

CC CC

Product data sheet Rev. 10 — 29 June 2012 7 of 19

NXP Semiconductors

EXT

mna616

DUT

Test data is given in Table 10. Definitions for test circuit:

= Load resistance.

= Load capacitance including jig and probe capacitance.

= Termination resistance should be equal to the output impedance Zo of the pulse generator.

= External voltage for measuring switching times.

EXT

Fig 9. Test circuit for measuring switching times

74LVC1G08

Single 2-input AND gate

Table 10. Test data

Supply voltage Input Load V V

1.65 V to 1.95 V V

2.3 V to 2.7 V V

EXT

tr=t

PLH

 2.0ns 30pF 1k open  2.0ns 30pF 500 open

2.7V 2.7V  2.5ns 50pF 500 open

3.0V to 3.6V 2.7V  2.5ns 50pF 500 open

4.5 V to 5.5 V V

 2.5ns 50pF 500 open

, t

PHL

Product data sheet Rev. 10 — 29 June 2012 8 of 19

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(1)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.101.0

0.8

0.30

0.15

0.25

0.08

2.25

1.85

1.35

1.15

0.65

1.3

2.25

2.0

0.60

0.15

7° 0°

0.1 0.10.30.425

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.46

0.21

SOT353-1 MO-203 SC-88A

00-09-01 03-02-19

w M

0.15

(A3)

detail X

v M

1.5 3 mm0

scale

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm

SOT353-1

1.1

13. Package outline

74LVC1G08

Single 2-input AND gate

Fig 10. Package outline SOT353-1 (TSSOP5)

Product data sheet Rev. 10 — 29 June 2012 9 of 19

NXP Semiconductors

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT753 SC-74A

wBM

detail X

v M

0 1 2 mm

scale

132

Plastic surface-mounted package; 5 leads SOT753

UNIT

HEL

Qywv

0.100

0.013

0.40

0.25

3.1

2.7

0.26

0.10

1.7

1.3

0.95

3.0

2.5

0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2

0.33

0.23

1.1

0.9

02-04-16 06-03-16

74LVC1G08

Single 2-input AND gate

Fig 11. Package outline SOT753 (SC-74A)

Product data sheet Rev. 10 — 29 June 2012 10 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886

(2)

terminal 1 index area

0 1 2 mm

scale

Dimensions (mm are the original dimensions)

Unit

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes. Outline

version

SOT886

(1)

max

0.5 0.04 1.50

nom

min

A1b

DEee

1.45

1.40

1.05

1.00

0.95

0.25

0.20

0.17

IEC JEDEC JEITA

0.6

MO-252

0.5

References

0.35

0.40

0.30

0.35

0.27

0.32

sot886_po

European projection

Issue date

04-07-22 12-01-05

Fig 12. Package outline SOT886 (XSON6)

Product data sheet Rev. 10 — 29 June 2012 11 of 19

NXP Semiconductors

terminal 1 index area

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT891

05-04-06 07-05-15

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

0.20

0.12

1.05

0.95

0.35

0.27

max

b E

1.05

0.95

ee1L

0.40

0.32

0.350.55

max

0.5 0.04

6×

(1)

4×

(1)

Note

1. Can be visible in some manufacturing processes.

74LVC1G08

Single 2-input AND gate

Fig 13. Package outline SOT891 (XSON6)

Product data sheet Rev. 10 — 29 June 2012 12 of 19

NXP Semiconductors

References

Outline version

European projection

Issue date

IEC JEDEC JEITA

SOT1115

sot1115_po

10-04-02 10-04-07

Unit

max nom

min

0.35 0.04 0.95

0.90

0.85

1.05

1.00

0.95

0.55 0.3

0.40

0.35

0.32

(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm

SOT1115

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1 index area

(4×)

(2)

b 321

6 5 4

(6×)

(2)

74LVC1G08

Single 2-input AND gate

Fig 14. Package outline SOT1115 (XSON6)

Product data sheet Rev. 10 — 29 June 2012 13 of 19

NXP Semiconductors

References

Outline version

European projection

Issue date

IEC JEDEC JEITA

SOT1202

sot1202_po

10-04-02 10-04-06

Unit

max nom

min

0.35 0.04 1.05

1.00

0.95

1.05

1.00

0.95

0.55 0.35

0.40

0.35

0.32

(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm

SOT1202

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1 index area

(4×)

(2)

123

6 5 4

(6×)

(2)

74LVC1G08

Single 2-input AND gate

Fig 15. Package outline SOT1202 (XSON6)

Product data sheet Rev. 10 — 29 June 2012 14 of 19

NXP Semiconductors

X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.35 mm

74LVC1G08

Single 2-input AND gate

SOT1226

terminal 1 index area

Dimensions

Unit

Note

1. Dimension A is including plating thickness.

2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline

version

SOT1226

(1)

A1A

max

0.35 0.85

nom

min

0.04 0.30

0.128

0.040

0.80

0.75

IEC JEDEC EIAJ

Ebe

0.85

0.25

0.80

0.20

0.75

01 mm

kLv

0.27

0.22

0.17

References

0.48

0.20

0.27

0.22

0.17

scale

0.1

0.05

0.05 0.05

detail X

European projection

sot1226_po

Issue date

12-04-10 12-04-25

Fig 16. Package outline SOT1226 (X2SON5)

Product data sheet Rev. 10 — 29 June 2012 15 of 19

NXP Semiconductors

14. Abbreviations

74LVC1G08

Single 2-input AND gate

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC1G08 v. 10 20120629 Product data sheet - 74LVC1G08 v.9 Modifications:

74LVC1G08 v. 9 20111209 Product data sheet - 74LVC1G08 v.8 Modifications: 74LVC1G08 v. 8 20101019 Product data sheet - 74LVC1G08 v.7 74LVC1G08 v. 7 20070717 Product data sheet - 74LVC1G08 v.6 74LVC1G08 v. 6 20060619 Product data sheet - 74LVC1G08 v.5 74LVC1G08 v.5 20040915 Product specification - 74LVC1G08 v.4 74LVC1G08 v.4 20021002 Product specification - 74LVC1G08 v.3 74LVC1G08 v.3 20020517 Product specification - 74LVC1G08 v.2 74LVC1G08 v.2 20010406 Product specification - 74LVC1G08 v.1 74LVC1G08 v.1 20001121 Product specification - -

• Added type number 74LVC1G08GX (SOT1226)

• Pa ckage outline drawing of SOT886 (Figure 12) modified.

• Legal pages updated.

Product data sheet Rev. 10 — 29 June 2012 16 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

16. Legal information

16.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed si nce this d ocument was pub lished and may dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cust omer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 10 — 29 June 2012 17 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 10 — 29 June 2012 18 of 19

NXP Semiconductors

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 5

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17 Contact information. . . . . . . . . . . . . . . . . . . . . 18

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

74LVC1G08

Single 2-input AND gate

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 June 2012

Document identifier: 74LVC1G08

NXP 74LVC1G08GF, 74LVC1G08GM, 74LVC1G08GN, 74LVC1G08GS, 74LVC1G08GV Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Marking

5. Functional diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

8. Limiting values

9. Recommended operating conditions

10. Static characteristics

11. Dynamic characteristics

12. AC waveforms

13. Package outline

14. Abbreviations

15. Revision history

16. Legal information

16.1 Data sheet status

16.2 Definitions

16.3 Disclaimers

16.4 Trademarks

17. Contact information

18. Contents