NXP 74LVC1G00GF, 74LVC1G00GM, 74LVC1G00GV, 74LVC1G00GW Schematic [ru]

74LVC1G00

Single 2-input NAND gate

Rev. 07 — 17 July 2007 Product data sheet

1. General description

The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these

devices in a mixed 3.3 Vand 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

2. Features

This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.

■ Wide supply voltage range from 1.65 V to 5.5 V

■ High noise immunity

■ Complies with JEDEC standard:

■ ±24 mA output drive (VCC= 3.0 V)

■ CMOS low power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options

■ ESD protection:

■ Specified from −40 °Cto+85°C and −40 °C to +125 °C

circuitry disables the output, preventing the damaging backflow current through

OFF

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V)

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

OFF

.

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC1G00GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;

SOT353-1

5 leads; body width 1.25 mm
74LVC1G00GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G00GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package;

SOT886

no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
74LVC1G00GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package;

SOT891

no leads; 6 terminals; body 1 × 1 × 0.5 mm

4. Marking

Table 2. Marking codes

Type number Marking

74LVC1G00GW VA
74LVC1G00GV V00
74LVC1G00GM VA
74LVC1G00GF VA

5. Functional diagram

1

B

2

A

mna097

4

Y

1
2

&

mna098

4

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

B

A

Y

mna099

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 2 of 14

NXP Semiconductors

6. Pinning information

6.1 Pinning

74LVC1G00

Single 2-input NAND gate

74LVC1G00

74LVC1G00

1

BV

2

A

3

GND Y

001aab608

5

CC

4

Fig 4. Pin configuration SOT353-1

Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891

1

B

2

A

3

GND

Transparent top view

6

V

5

n.c.

4

Y

001aab603

CC

and SOT753

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

SOT353-1/SOT753 SOT886/SOT891

B 1 1 data input
A 2 2 data input
GND 3 3 ground (0 V)
Y 4 4 data output
n.c. - 5 not connected
V

CC

5 6 supply voltage

74LVC1G00

1

B

A

2

GND

3

Transparent top view

V

6

n.c.

5

Y

4

001aaf051

CC

7. Functional description

Table 4. Function table

Inputs Outputs
A B Y

LLH
LHH
HLH
HHL

[1] H = HIGH voltage level;

L = LOW voltage level.

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 3 of 14

[1]

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V
I

IK

V
I

OK

V

I

O

I

CC

I

GND

P
T

CC

I

O

tot
stg

supply voltage −0.5 +6.5 V
input clamping current VI < 0 V −50 - mA
input voltage

[1]

−0.5 +6.5 V
output clamping current VO > VCC or VO < 0 V - ±50 mA
output voltage Active mode

Power-down mode

output current VO = 0 V to V

CC

[1][2]

−0.5 VCC + 0.5 V

[1][2]

−0.5 +6.5 V

- ±50 mA
supply current - +100 mA
ground current −100 - mA
total power dissipation T

= −40 °C to +125 °C

amb

[3]

- 250 mW
storage temperature −65 +150 °C

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of P

For XSON6 packages: above 45 °C the value of P

derates linearly with 2.4 mW/K.

tot

derates linearly with 4.0 mW/K.

tot

9. Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

V

CC

V

I

V

O

T

amb

∆t/∆V input transition rise and fall rate V

supply voltage 1.65 - 5.5 V
input voltage 0 - 5.5 V
output voltage Active mode 0 - V

= 0 V; Power-down mode 0 - 5.5 V

V

CC

CC

V

ambient temperature −40 - +125 °C

= 1.65 V to 2.7 V - - 20 ns/V

CC

= 2.7 V to 5.5 V - - 10 ns/V

V

CC

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 4 of 14

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

10. Static characteristics

Table 7. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit

[1]

Max Min Max

- - 0.65V

- - 0.7V

CC

CC

- 0.35VCCV

- 0.3V

CC

CC

-V

-V

V

CC

V

V

V

V

I

I

I

OFF

I

CC

∆I

C

IH

IL

OH

OL

CC

I

HIGH-level
input voltage

LOW-level
input voltage

HIGH-level
output voltage

LOW-level
output voltage

input leakage
current

power-off

VCC = 1.65 V to 1.95 V 0.65V

= 2.3 V to 2.7 V 1.7 - - 1.7 - V

V

CC

= 2.7 V to 3.6 V 2.0 - - 2.0 - V

V

CC

= 4.5 V to 5.5 V 0.7V

V

CC

VCC = 1.65 V to 1.95 V - - 0.35V

= 2.3 V to 2.7 V - - 0.7 - 0.7 V

V

CC

= 2.7 V to 3.6 V - - 0.8 - 0.8 V

V

CC

= 4.5 V to 5.5 V - - 0.3V

V

CC

VI=VIHor V

IL

IO= −100 µA;
V

= 1.65 V to 5.5 V

CC

= −4 mA; VCC = 1.65 V 1.2 - - 0.95 - V

I

O

= −8 mA; VCC = 2.3 V 1.9 - - 1.7 - V

I

O

= −12 mA; VCC = 2.7 V 2.2 - - 1.9 - V

I

O

= −24 mA; VCC = 3.0 V 2.3 - - 2.0 - V

I

O

= −32 mA; VCC = 4.5 V 3.8 - - 3.4 - V

I

O

VI=VIHor V

IL

IO= 100 µA;
V

= 1.65 V to 5.5 V

CC

= 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V

I

O

= 8 mA; VCC = 2.3 V - - 0.3 - 0.45 V

I

O

= 12 mA; VCC = 2.7 V - - 0.4 - 0.60 V

I

O

= 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V

I

O

= 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V

I

O

VI = 5.5 V or GND;
V

= 0 V to 5.5 V

CC

VCC = 0 V; VIor VO= 5.5 V - ±0.1 ±10 - ±200 µA
leakage
current

supply current VI = 5.5 V or GND; IO = 0 A;

V

= 1.65 V to 5.5 V

CC

additional
supply current

VCC = 2.3 V to 5.5 V;

V

I=VCC

− 0.6 V; IO= 0 A;

per pin
input

VCC= 3.3 V; VI = GND to V
capacitance

CC

Min Typ

CC

CC

− 0.1 - - VCC− 0.1 - V

V

CC

- - 0.1 - 0.1 V

- ±0.1 ±5-±100 µA

- 0.1 10 - 200 µA

- 5 500 - 5000 µA

-5- - -pF

[1] All typical values are measured at VCC= 3.3 V and T

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 5 of 14

amb

=25°C.

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

11. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8.

Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ

t

pd

propagation delay A, B to Y; see Figure 7

[2]

VCC= 1.65 V to 1.95 V 1.0 3.3 8.0 1.0 10.5 ns

= 2.3 V to 2.7 V 0.5 2.2 5.5 0.5 7.0 ns

V

CC

= 2.7 V 0.5 2.6 5.8 0.5 7.5 ns

V

CC

= 3.0 V to 3.6 V 0.5 2.2 4.7 0.5 6.0 ns

V

CC

= 4.5 V to 5.5 V 0.5 1.8 4.0 0.5 5.5 ns

V

CC

C

PD

power dissipation
capacitance

VI = GND to VCC;
V

= 3.3 V

CC

[3]

-14- - -pF

[1]

Max Min Max

[1] Typical values are measured at T
[2] tpd is the same as t

PLH

and t

PHL

=25°C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

amb

.

[3] CPDis used to determine the dynamic power dissipation (PDin µW).

PD=CPD× V

2

× fi× N+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in V;
N = number of inputs switching;
∑(CL× V

2

× fo) = sum of outputs.

CC

12. Waveforms

V

I

A, B input

Y output

GND

V

OH

V

OL

V

M

V

M

t

PHL

t

PLH

mna612

Measurement points are given in Table9.
VOL and VOH are typical output voltage levels that occur with the output.

Fig 7. The input (A and B) to output (Y) propagation delay times

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 6 of 14

NXP Semiconductors

Table 9. Measurement points

Supply voltage Input Output
V

CC

1.65 V to 1.95 V 0.5V

2.3 V to 2.7 V 0.5V

2.7 V 1.5 V 1.5 V

3.0 V to 3.6 V 1.5 V 1.5 V

4.5 V to 5.5 V 0.5V

V

M

CC
CC

CC

V

CC

V

I

G

DUT

R

T

V

O

C

L

V

EXT

mna616

V

M

0.5V

0.5V

0.5V

R

L

R

L

74LVC1G00

Single 2-input NAND gate

CC
CC

CC

Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
V

= External voltage for measuring switching times.

EXT

Fig 8. Load circuit for switching times

Table 10. Test data

Supply voltage Input Load V
V

CC

1.65 V to 1.95 V V

2.3 V to 2.7 V V

V

I

CC

CC

tr=t

f

C

L

R

L

≤ 2.0 ns 30 pF 1 kΩ open
≤ 2.0 ns 30 pF 500 Ω open

t

EXT

PLH

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open

4.5 V to 5.5 V V

CC

≤ 2.5 ns 50 pF 500 Ω open

, t

PHL

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 7 of 14

NXP Semiconductors

13. Package outline

74LVC1G00

Single 2-input NAND gate

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm

D

y

Z

5

4

13

e

e

1

w M

b

p

c

A

2

E

H

E

A

1

L

p

L

detail X

SOT353-1

A

X

v M

A

(A3)

A

θ

1.5 3 mm0

scale

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

max.

mm

1.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE
VERSION

SOT353-1 MO-203 SC-88A

A2A3b

1

0.101.0

0.8

p

0.30

0.15

0.15

IEC JEDEC JEITA

ceD

0.25

0.08

(1)E(1)

2.25

1.35

1.85

1.15

REFERENCES

0.65

e

1.3

LH

1

E

2.25

2.0

L

p

0.46

0.21

PROJECTION

EUROPEAN

wyv

0.1 0.10.30.425

(1)

Z

0.60

0.15

ISSUE DATE

00-09-01
03-02-19

θ

7°
0°

Fig 9. Package outline SOT353-1 (TSSOP5)

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 8 of 14

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

Plastic surface-mounted package; 5 leads SOT753

D

y

E

H

E

AB

X

v M

A

45

Q

A

A

1

c

132

e

detail X

b

p

wBM

L

p

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1.1

mm

0.9

OUTLINE
VERSION

SOT753 SC-74A

1

0.100

0.013

b

cD

p

0.40

0.25

IEC JEDEC JEITA

0.26

0.10

3.1

2.7

e

E

1.7

0.95

1.3

REFERENCES

H

3.0

2.5

L

Qywv

p

E

0.6

0.2

0.33

0.23

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

02-04-16
06-03-16

Fig 10. Package outline SOT753 (SC-74A)

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 9 of 14

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

1

L

1

e

6

6×

(2)

2

5

e

1

D

b

3

4×

L

4

e

1

A

A

1

(2)

SOT886

E

terminal 1
index area

0 1 2 mm

0.35

0.27

scale

L

0.40

0.32

1

EUROPEAN

PROJECTION

ISSUE DATE

04-07-15
04-07-22

DIMENSIONS (mm are the original dimensions)

(1)

A

A

UNIT

max

mm

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

OUTLINE
VERSION

SOT886

max

0.5 0.04

1

b E

D

1.5

1.4

1.05

0.95

MO-252

0.25

0.17

IEC JEDEC JEITA

ee1L

0.50.6

REFERENCES

Fig 11. Package outline SOT886 (XSON6)

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 10 of 14

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

1

L

1

e

6

6×

(1)

2

5

e

1

D

b

3

4×

L

4

e

1

A

A

1

(1)

SOT891

E

terminal 1
index area

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

max

mm

Note

1. Can be visible in some manufacturing processes.

OUTLINE
VERSION

SOT891

max

0.5 0.04

1

b E

D

0.20

1.05

0.12

0.95

IEC JEDEC JEITA

ee1L

1.05

0.95

0.35

0.350.55

0.27

REFERENCES

L

0.40

0.32

1

EUROPEAN

PROJECTION

ISSUE DATE

05-04-06
07-05-15

Fig 12. Package outline SOT891 (XSON6)

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 11 of 14

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

14. Abbreviations

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC1G00_7 20070717 Product data sheet - 74LVC1G00_6
Modifications:

74LVC1G00_6 20060915 Product data sheet - 74LVC1G00_5
74LVC1G00_5 20040907 Product specification - 74LVC1G00_4
74LVC1G00_4 20021115 Product specification - 74LVC1G00_3
74LVC1G00_3 20020515 Product specification - 74LVC1G00_2
74LVC1G00_2 20010405 Product specification - 74LVC1G00_1
74LVC1G00_1 20001108 Product specification - -

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 10 “Static characteristics”:

Changed: Conditions for supply current.

• New package outline drawing for XSON6/SOT891.

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 12 of 14

NXP Semiconductors

16. Legal information

16.1 Data sheet status

74LVC1G00

Single 2-input NAND gate

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] Theproduct status of device(s) described in this document may have changed since this document was published and may differ in case of multipledevices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shallhave no liabilityforthe consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product typenumber(s) and title. A short datasheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not giveany representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or

[3]

http://www.nxp.com.

Definition

malfunction of a NXP Semiconductors product can reasonablybe expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device.Limiting valuesare stress ratings only and operationof
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names andtrademarks
are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [e-mail]

74LVC1G00_7 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 07 — 17 July 2007 13 of 14

NXP Semiconductors

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

17 Contact information. . . . . . . . . . . . . . . . . . . . . 13

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

74LVC1G00

Single 2-input NAND gate

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Date of release: 17 July 2007

Document identifier: 74LVC1G00_7