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74HCT595BQ
Schematics
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NXP 74HC595BQ, 74HC595D, 74HC595DB, 74HC595N, 74HC595PW Schematics

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74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Rev. 6 — 12 December 2011 Product data sheet

1. General description

The 74HC595; 74HCT595 are high-speed Si-gate CMOS device s and ar e pin co mpatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset ( active LOW) for all 8 shif t register st ages. The storage register has 8 parallel 3-state bus driver output s. Data in the storage register appears at the output whenever the output enable input (OE

2. Features and benefits

8-bit serial input
8-bit serial or parallel outputStorage register with 3-state outputsShift register with direct clear100 MHz (typical) shift out frequencyESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 VMultiple package optionsSpecified from 40 C to +85 C and from 40 C to +125 C

3. Applications

Serial-to-parallel data conversion
Remote control holding register
) is LOW.
NXP Semiconductors
mna554
3-STATE OUTPUTS
8-BIT STORAGE REGISTER
8-STAGE SHIFT REGISTER
Q
0
Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q7S
14
151234567
9
D
S
SHCP
STCP
OE
11 10
12
13
MR

4. Ordering information

74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC595N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT595N 74HC595D 40 C to +125 C SO16 plastic small outline package; 16 leads; 74HCT595D
body width 3.9 mm
74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; 74HCT595DB
body width 5.3 mm
74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; 74HCT595PW
body width 4.4 mm
74HC595BQ 40C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced 74HCT595BQ
very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm
SOT109-1
SOT338-1
SOT403-1
SOT763-1

5. Functional diagram

Fig 1. Functional diagram
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 2 of 24
NXP Semiconductors
OEMR
9
15
1 2 3 4 5 6 7
1310
14
11 12
mna552
Q1
Q0
Q2 Q3 Q4 Q5 Q6 Q7
Q7S
D
S
STCP
SHCP
mna553
15
9
1 2 3 4 5 6 7
1D 2D
C1/
10 11
14
C2
12
13
EN3
SRG8
R
3
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
DCPQ
R
LATCH
DCPQ
FF7
DCPQ
R
LATCH
DCPQ
mna555
DQ
Q
1 Q2 Q3 Q4 Q5 Q6 Q7
Q7S
Q
0
DS
STCP
SHCP
OE
MR
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
Fig 2. Logic symbol Fig 3. IEC logic symbol
3-state
Fig 4. Logic diagram
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 3 of 24
NXP Semiconductors
74HC595
74HCT595
Q1 V
CC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aao241
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC595
74HCT595
Q1 V
CC
Q2 Q0 Q3 DS Q4 OE Q5 STCP Q6 SHCP Q7 MR
GND Q7S
001aao242
1 2 3 4 5 6 7 8
10
9
12 11
14 13
16 15

6. Pinning information

6.1 Pinning

74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 5. Pin configuration DIP16, SO16 Fig 6. Pin configuration SSOP16, TSSOP16
74HC595
74HCT595
terminal 1
index area
2 15
Q2 Q0
3 14
Q3 DS
4
Q4 OE
5 12
Q5 STCP
6 11
Q6 SHCP
7 10
Q7 MR
Transparent top view
Q1 1
GND
8
GND
CC
V 16
13
(1)
9
001aao243
Q7S
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to GND.
Fig 7. Pin configuration for DHVQFN16
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 4 of 24
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output MR SHCP 11 shift register clock input STCP 12 storage register clock input OE DS 14 serial data input Q0 15 parallel data output 0 V
CC
10 master reset (active LOW)
13 output enable input (active LOW)
16 supply voltage
74HC595; 74HCT595
3-state

7. Functional description

Table 3. Function table
Control Input Output Function SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-level on MR X L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
X L H X NC QnS contents of shift register stages (internal QnS) are transferred to
L H X Q6S QnS contents of shift register shifted throug h ; pre vi o us contents of the
[1] H = HIGH voltage state;
L = LOW voltage state; = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state.
[1]
only affects the shift registers
shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S).
the storage register and parallel output stages
shift register is transferred to the storage register and the parallel output stages
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 5 of 24
NXP Semiconductors
SHCP
DS
STCP
MR
OE
Q0
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Z-state
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
mna556
Fig 8. Timing diagram

8. Limiting values

Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V I
IK
I
OK
I
O
I
CC
I
GND
T P
CC
stg
tot
supply voltage 0.5 +7 V input clamping current VI < 0.5 V or VI>VCC+ 0.5 V - 20 mA output clamping current VO< 0.5 V or VO > VCC + 0.5 V - 20 mA output current VO= 0.5 V to (VCC+0.5V)
supply current - 70 mA ground current 70 - mA storage temperature 65 +150 C total power dissipation
DIP16 package SO16 package SSOP16 package TSSOP16 package DHVQFN16 package
pin Q7S - 25 mA pins Qn - 35 mA
[1]
- 750 mW
[2]
- 500 mW
[3]
- 500 mW
[3]
- 500 mW
[4]
- 500 mW
[1] For DIP16 package: P [2] For SO16 package: P [3] For SSOP16 and TSSOP16 packages: P [4] For DHVQFN16 package: P
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 6 of 24
derates linearly with 12 mW/K above 70 C.
tot
derates linearly with 8 mW/K above 70 C.
tot
derates linearly with 5.5 mW/K above 60 C.
tot
derates linearly with 4.5 mW/K above 60 C.
tot
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;

9. Recommended operating conditions

74HC595; 74HCT595
3-state
Table 5. Recommended operating conditions
Symbol Parameter Conditions 74HC595 74HCT595 Unit
Min Typ Max Min Typ Max
V
CC
V
I
V
O
t/V input transition rise and
T
amb
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - V output voltage 0 - V
= 2.0 V - - 625 - - - ns/V
V
fall rate
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V - - 83 - - - ns/V
V
CC
CC CC
0-VCCV 0-VCCV
ambient temperature 40 +25 +125 40 +25 +125 C

10. Static characteristics

Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
74HC595
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
V
OH
HIGH-level output voltage
Min Typ Max Min Max
VCC= 2.0 V 1.5 1.2 - 1.5 - V
V
= 4.5 V 3.15 2.4 - 3.15 - V
CC
= 6.0 V 4.2 3.2 - 4.2 - V
V
CC
VCC= 2.0 V - 0.8 0.5 - 0.5 V
= 4.5 V - 2.1 1.35 - 1.35 V
V
CC
= 6.0 V - 2.8 1.8 - 1.8 V
V
CC
VI=VIHor V
IL
all outputs
= 20 A; VCC= 2.0 V 1.9 2.0 - 1.9 - V
I
O
= 20 A; VCC= 4.5 V 4.4 4.5 - 4.4 - V
I
O
= 20 A; VCC= 6.0 V 5.9 6.0 - 5.9 - V
I
O
Q7S output
= 4mA; VCC= 4.5 V 3.84 4.32 - 3.7 - V
I
O
= 5.2 mA; VCC= 6.0 V 5.34 5.81 - 5.2 - V
I
O
Qn bus driver outputs
= 6mA; VCC= 4.5 V 3.84 4.32 - 3.7 - V
I
O
= 7.8 mA; VCC= 6.0 V 5.34 5.81 - 5.2 - V
I
O
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 7 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
V
OL
LOW-level output voltage
VI=VIHor V
IL
all outputs
=20A; VCC= 2.0 V - 0 0.1 - 0.1 V
I
O
=20A; VCC= 4.5 V - 0 0.1 - 0.1 V
I
O
=20A; VCC= 6.0 V - 0 0.1 - 0.1 V
I
O
Q7S output
=4mA; VCC= 4.5 V - 0.15 0.33 - 0.4 V
I
O
=5.2mA; VCC= 6.0 V - 0.16 0.33 - 0.4 V
I
O
Qn bus driver outputs
=6mA; VCC= 4.5 V - 0.15 0.33 - 0.4 V
I
O
=7.8mA; VCC= 6.0 V - 0.16 0.33 - 0.4 V
I
O
I
I
input leakage
VI=VCCor GND; VCC=6.0V - - 1.0 - 1.0 A
current
I
OZ
OFF-state output current
I
CC
C
I
supply current VI=VCCor GND; IO=0A;
input
VI=VIHor VIL; VCC=6.0V;
VO=VCCor GND
=6.0V
V
CC
--5.0 - 10 A
- - 80 - 160 A
-3.5- - -pF
capacitance
74HCT595
V
IH
HIGH-level
VCC= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
input voltage
V
IL
LOW-level
VCC= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
input voltage
V
OH
HIGH-level output voltage
VI=VIHor VIL; VCC=4.5V
all outputs
= 20 A 4.4 4.5 - 4.4 - V
I
O
Q7S output
= 4 mA 3.84 4.32 - 3.7 - V
I
O
Qn bus driver outputs
= 6 mA 3.7 4.32 - 3.7 - V
I
O
V
OL
LOW-level output voltage
VI=VIHor VIL; VCC=4.5V
all outputs
=20A - 0 0.1 - 0.1 V
I
O
Q7S output
= 4.0 mA - 0.15 0.33 - 0.4 V
I
O
Qn bus driver outputs
= 6.0 mA - 0.16 0.33 - 0.4 V
I
O
I
I
input leakage
VI=VCCor GND; VCC=5.5V - - 1.0 - 1.0 A
current
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 8 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
I
OZ
I
CC
OFF-state output current
VI=VIHor VIL; VCC=5.5 V;
VO=VCCor GND
supply current VI=VCCor GND; IO=0A;
--5.0 - 10 A
- - 80 - 160 A
VCC=5.5V
I
CC
additional supply current
per input pin; IO=0A; VI=VCC
2.1 V; other inputs at V
or GND;
CC
VCC= 4.5 V to 5.5 V
pins MR
, SHCP, STCP, OE - 150 675 - 735 A
pin DS - 25 113 - 123 A
C
I
input
-3.5- - -pF
capacitance
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 9 of 24
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;

11. Dynamic characteristics

74HC595; 74HCT595
3-state
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
74HC595
t
pd
propagation delay
SHCP to Q7S; see
VCC = 2 V - 52 160 - 200 - 240 ns
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
= 6 V - 15 27 - 34 - 41 ns
V
CC
STCP to Qn; see
Figure 9
Figure 10
[2]
[2]
VCC = 2 V - 55 175 - 220 - 265 ns
= 4.5 V - 20 35 - 44 - 53 ns
V
CC
= 6 V - 16 30 - 37 - 45 ns
V
CC
to Q7S; see Figure 12
MR
[3]
VCC = 2 V - 47 175 - 220 - 265 ns
= 4.5 V - 17 35 - 44 - 53 ns
V
CC
= 6 V - 14 30 - 37 - 45 ns
V
CC
t
en
enable time OE
to Qn; see Figure 13
[4]
VCC = 2 V - 47 150 - 190 - 225 ns V
= 4.5 V - 17 30 - 38 - 45 ns
CC
= 6 V - 14 26 - 33 - 38 ns
V
CC
t
dis
disable time OE
to Qn; see Figure 13
[5]
VCC = 2 V - 41 150 - 190 - 225 ns
= 4.5 V - 15 30 - 38 - 45 ns
V
CC
= 6 V - 12 27 - 33 - 38 ns
V
CC
t
W
pulse width SHCP HIGH or LOW;
Figure 9
see
VCC = 2 V 75 17 - 95 - 110 - ns
= 4.5 V 15 6 - 19 - 22 - ns
V
CC
= 6 V 13 5 - 16 - 19 - ns
V
CC
STCP HIGH or LOW;
Figure 10
see
VCC = 2 V 75 11 - 95 - 110 - ns
= 4.5 V 15 4 - 19 - 22 - ns
V
CC
= 6 V 13 3 - 16 - 19 - ns
V
CC
LOW; see Figure 12
MR
VCC = 2 V 75 17 - 95 - 110 - ns
= 4.5 V 15 6 - 19 - 22 - ns
V
CC
= 6 V 13 5 - 16 - 19 - ns
V
CC
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 10 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
t
su
set-up time DS to SHCP; see Figure 10
[1]
Max Min Max Min Max
VCC = 2 V 50 11 - 65 - 75 - ns
= 4.5 V 10 4 - 13 - 15 - ns
V
CC
= 6 V 9 3 - 11 - 13 - ns
V
CC
SHCP to STCP;
Figure 11
see
VCC = 2 V 75 22 - 95 - 110 - ns
= 4.5 V 15 8 - 19 - 22 - ns
V
CC
= 6 V 13 7 - 16 - 19 - ns
V
CC
t
h
hold time DS to SHCP; see
Figure 11
VCC = 2 V 3 6- 3 - 3 - ns
= 4.5 V 3 2- 3 - 3 - ns
V
CC
= 6 V 3 2- 3 - 3 - ns
V
CC
t
f
rec
max
recovery time
maximum frequency
MR
to SHCP; see Figure 12
VCC = 2 V 50 19 - 65 - 75 - ns
= 4.5 V 10 7- 13 - 15 - ns
V
CC
= 6 V 9 6- 11 - 13 - ns
V
CC
SHCP or STCP; see
Figure 9
and 10
VCC = 2 V 9 30 - 4.8 - 4 - MHz
= 4.5 V 30 91 - 24 - 20 - MHz
V
CC
= 6 V 35 108 - 28 - 24 - MHz
V
CC
[6]
C
PD
power
= 1 MHz; VI=GNDtoV
f
i
CC
[7]
-115- - - - - pF dissipation capacitance
74HCT595; V
t
pd
t
en
t
dis
t
W
t
su
t
h
= 4.5 V to 5.5 V
CC
propagation delay
enable time OE disable time OE
SHCP to Q7S; see STCP to Qn; see
to Q7S; see Figure 12
MR
to Qn; see Figure 13 to Qn; see Figure 13
Figure 9
Figure 10
pulse width SHCP HIGH or LOW;
see
Figure 9
STCP HIGH or LOW;
Figure 10
see
LOW; see Figure 12 20 8 - 25 - 30 - ns
MR
set-up time DS to SHCP; see
Figure 10 16 5 - 20 - 24 - ns
SHCP to STCP;
Figure 11
see
hold time DS to SHCP; see
Figure 11 3 2- 3 - 3 - ns
[2]
-2542- 53 - 63ns
[2]
-2440- 50 - 60ns
[3]
-2340- 50 - 60ns
[4]
-2135- 44 - 53ns
[5]
-1830- 38 - 45ns
16 6 - 20 - 24 - ns
16 5 - 20 - 24 - ns
16 8 - 20 - 24 - ns
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 11 of 24
NXP Semiconductors
mna557
SHCP
input
Q
7S output
t
PLH
t
PHL
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
[1]
Max Min Max Min Max
t
rec
recovery
MR to SHCP; see Figure 12 10 7- 13 - 15 - ns
time
f
C
max
PD
maximum frequency
power
SHCP and STCP;
Figure 9 and 10
see fi = 1 MHz; VI=GNDtoV
CC
dissipation capacitance
[1] Typical values are measured at nominal supply voltage. [2] t
is the same as t
pd
is the same as t
[3] t
pd
is the same as t
[4] t
en
[5] t
is the same as t
dis
[6] C
is used to determine the dynamic power dissipation (PDin W).
PD
P
D=CPD
f
i
f
o
(C C V
CC
V
CC
= input frequency in MHz;
= output frequency in MHz;
2
V
L
= output load capacitance in pF;
L
fo) = sum of outputs;
CC
= supply voltage in V.
[7] All 9 outputs switching.
and t
PHL
only.
PHL
and t
PZL
and t
PLZ
2
fi+ (CL V
PLH
PZH PHZ
.
. .
2
fo) where:
CC
Min Typ
30 52 - 24 - 20 - MHz
[6]
- 130 - - - - - pF
[7]

12. Waveforms

Measurement points are given in Table 8.
and VOH are typical output voltage levels that occur with the output load.
V
OL
Fig 9. Shift clock pulse, maximum frequency and input to output propagation delays
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 12 of 24
NXP Semiconductors
mna558
STCP
input
Q
n output
t
PLH
t
PHL
t
W
t
su
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
SHCP
input
V
I
GND
V
M
mna560
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Q7S output
SH
CP input
D
S input
8-bit serial-in, serial or parallel-out shift register with output latches;
Measurement points are given in Table 8. V
and VOH are typical output voltage levels that occur with the output load.
OL
Fig 10. Storage clock to output propagation delays
74HC595; 74HCT595
3-state
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance.
and VOH are typical output voltage levels that occur with the output load.
V
OL
Fig 11. Data set-up and hold times
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 13 of 24
NXP Semiconductors
mna561
MR input
SH
CP input
Q
7S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
msa697
t
PLZ
t
PHZ
outputs
disabled
outputs enabled
90 %
10 %
outputs
enabled
OE input
V
M
t
PZL
t
PZH
V
M
V
M
Qn output
LOW-to-OFF OFF-to-LOW
Qn output
HIGH-to-OFF OFF-to-HIGH
t
r
t
f
90 %
10 %
8-bit serial-in, serial or parallel-out shift register with output latches;
Measurement points are given in Table 8.
and VOH are typical output voltage levels that occur with the output load.
V
OL
Fig 12. Master reset to output propagation delays
74HC595; 74HCT595
3-state
Measurement points are given in Table 8.
and VOH are typical output voltage levels that occur with the output load.
V
OL
Fig 13. En able and disable times
V
M
CC
V
M
0.5V
CC
Table 8. Measurement points
Type Input Output
74HC595 0.5V 74HCT595 1.3 V 1.3 V
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 14 of 24
NXP Semiconductors
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
RLS1
C
L
open
G
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Test data is given in Table 9. Definitions for test circuit:
= load capacitance including jig and probe capacitance.
C
L
= load resistance.
R
L
R
= termination resistance should be equal to the output impedance Zo of the pulse generator.
T
S1 = test selection switch.
Fig 14. Test circuit for measuring switching times
Table 9. Test data
Type Input Load S1 position
V
I
74HC595 V
CC
74HCT595 3 V 6 ns 50 pF 1k open GND V
tr, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
6 ns 50 pF 1 k open GND V
, t
PHZ
t
PZL
CC CC
, t
PLZ
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 15 of 24
NXP Semiconductors
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT38-4
95-01-14 03-02-13
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
b
2
e
D
A
2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT
A
max.
12
b
1
(1) (1)
(1)
b
2
cD E e M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
0.764.2 0.51 3.2
inches
0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.010.1 0.3
0.32
0.31
0.39
0.33
0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4

13. Package outline

74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 15. Package outline SOT38-4 (DIP16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 16 of 24
NXP Semiconductors
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A2A3b
p
cD
(1)E(1) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8 0
o o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1
99-12-27 03-02-19
076E07 MS-012
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 16. Package outline SOT109-1 (SO16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 17 of 24
NXP Semiconductors
UNIT A1A2A3b
p
cD
(1)E(1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8 0
o o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
99-12-27 03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
8
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
max.
2
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 17. Package outline SOT338-1 (SSOP16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 18 of 24
NXP Semiconductors
UNIT A1A2A
3
b
p
cD
(1)E(2) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8 0
o o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
99-12-27 03-02-18
w M
b
p
D
Z
e
0.25
18
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
A
max.
1.1
pin 1 index
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 18. Package outline SOT403-1 (TSSOP16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 19 of 24
NXP Semiconductors
terminal 1 index area
0.51
A
1
E
h
b
UNIT
ye
0.2
c
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
3.6
3.4
D
h
2.15
1.85
y
1
2.6
2.4
1.15
0.85
e
1
2.5
0.30
0.18
0.05
0.00
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1v0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y
y
1
C
e
L
E
h
D
h
e
e
1
b
27
15
10
9
8
1
16
X
D
E
C
B
A
terminal 1 index area
ACCB
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
02-10-17 03-01-27
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 19. Package outline SOT763-1 (DHVQFN16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 20 of 24
NXP Semiconductors

14. Abbreviations

74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Table 10. Abbreviations
Acronym Abbreviation
CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model

15. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5 Modifications: 74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4 74HC_HCT595 v.4 20030604 Product specification - 74HC_HCT595_CNV v.3 74HC_HCT595_CNV v.3 19980604 Product specification - -
• Legal pages updated.
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 21 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state

16. Legal information

16.1 Data sheet status

Document status
Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s
information is available on the Internet at URL
[1][2]
Product status
http://www.nxp.com.
[3]
Definition

16.2 Definitions

Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
http://www.nxp.com/profile/terms
, unless otherwise
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 22 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 23 of 24
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
17 Contact information. . . . . . . . . . . . . . . . . . . . . 23
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
74HC595; 74HCT595
3-state
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2011
Document identifier: 74HC_HCT595
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