NSC LF298M, LF298H, LF298MX Datasheet

LF198/LF298/LF398, LF198A/LF398A
Monolithic Sample-and-Hold Circuits

General Description

The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is

0.002%typical and acquisition time is as low as 6 µs to

0.01%. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accom­plished with a single pin, and does not degrade input offset
drift. The widebandwidthallowstheLF198 to be included in­side the feedback loop of 1 MHz op amps without having sta­bility problems. Input impedance of 10

10

Ω allows high

source impedances to be used without degrading accuracy.
P-channel junction FET’s are combined with bipolar devices

in the output amplifier to give droop rates as low as 5 mV/min
witha1µFhold capacitor. The JFET’s have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.

Features

n Operates from±5V to±18V supplies
n Less than 10 µs acquisition time
n TTL, PMOS, CMOS compatible logic input
n 0.5 mV typical hold step at C

h

=

0.01 µF

n Low input offset
n 0.002%gain accuracy
n Low output noise in hold mode
n Input characteristics do not change during hold mode
n High supply rejection ratio in sample or hold
n Wide bandwidth
n Space qualified

Logic inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate
from

±

5V to±18V supplies.

An “A” version is available with tightened electrical
specifications.

Typical Connection and Performance Curve

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Acquisition Time

DS005692-16

May 1998

LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits

© 1999 National Semiconductor Corporation DS005692 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage

±

18V

Power Dissipation (Package

Limitation) (Note 2) 500 mW

Operating Ambient Temperature Range

LF198/LF198A −55˚C to +125˚C
LF298 −25˚C to +85˚C

LF398/LF398A 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚C
Input Voltage Equal to Supply Voltage
Logic To Logic Reference

Differential Voltage (Note 3) +7V, −30V
Output Short Circuit Duration Indefinite

Hold Capacitor Short

Circuit Duration 10 sec

Lead Temperature (Note 4)

H package (Soldering, 10 sec.) 260˚C
N package (Soldering, 10 sec.) 260˚C
M package:

Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C

Thermal Resistance (θ

JA

) (typicals)

H package 215˚C/W (Board mount in still air)

85˚C/W (Board mount in

400LF/min air flow)
N package 115˚C/W
M package 106˚C/W

θ

JC

(H package, typical) 20˚C/W

Electrical Characteristics

The following specifcations apply for −VS+ 3.5V ≤ VIN≤ +VS− 3.5V, +V

S

=

+15V, −V

S

=

−15V, T

A

=

T

j

=

25˚C, C

h

=

0.01 µF,

R

L

=

10 kΩ, LOGIC REFERENCE=0V, LOGIC HIGH=2.5V, LOGIC LOW=0V unless otherwise specified.

Parameter Conditions LF198/LF298 LF398 Units

Min Typ Max Min Typ Max

Input Offset Voltage, (Note 5) T

j

=

25˚C 1 3 2 7 mV

Full Temperature Range 5 10 mV

Input Bias Current, (Note 5) T

j

=

25˚C 5 25 10 50 nA

Full Temperature Range 75 100 nA

Input Impedance T

j

=

25˚C 10

10

10

10

Ω

Gain Error T

j

=

25˚C, R

L

=

10k 0.002 0.005 0.004 0.01

%

Full Temperature Range 0.02 0.02

%

Feedthrough Attenuation Ratio T

j

=

25˚C, C

h

=

0.01 µF 86 96 80 90 dB
at 1 kHz
Output Impedance T

j

=

25˚C, “HOLD” mode 0.5 2 0.5 4 Ω

Full Temperature Range 4 6 Ω

“HOLD” Step, (Note 6) T

j

=

25˚C, C

h

=

0.01 µF, V

OUT

=

0 0.5 2.0 1.0 2.5 mV

Supply Current, (Note 5) T

j

≥25˚C 4.5 5.5 4.5 6.5 mA

Logic and Logic Reference Input T

j

=

25˚C 2 10 2 10 µA
Current
Leakage Current into Hold T

j

=

25˚C, (Note 7) 30 100 30 200 pA
Capacitor (Note 5) Hold Mode
Acquisition Time to 0.1

%

∆V

OUT

=

10V, C

h

=

1000 pF 4 4 µs

C

h

=

0.01 µF 20 20 µs

Hold Capacitor Charging Current V

IN−VOUT

=

2V 5 5 mA

Supply Voltage Rejection Ratio V

OUT

=

0 80 110 80 110 dB

Differential Logic Threshold T

j

=

25˚C 0.8 1.4 2.4 0.8 1.4 2.4 V
Input Offset Voltage, (Note 5) T

j

=

25˚C 1 1 2 2 mV

Full Temperature Range 2 3 mV

Input Bias Current, (Note 5) T

j

=

25˚C 5 25 10 25 nA

Full Temperature Range 75 50 nA

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Electrical Characteristics

The following specifcations apply for −VS+ 3.5V ≤ VIN≤ +VS− 3.5V, +V

S

=

+15V, −V

S

=

−15V, T

A

=

T

j

=

25˚C, C

h

=

0.01 µF,

R

L

=

10 kΩ, LOGIC REFERENCE=0V, LOGIC HIGH=2.5V, LOGIC LOW=0V unless otherwise specified.

Parameter Conditions LF198A LF398A Units

Min Typ Max Min Typ Max

Input Impedance T

j

=

25˚C 10

10

10

10

Ω

Gain Error T

j

=

25˚C, R

L

=

10k 0.002 0.005 0.004 0.005

%

Full Temperature Range 0.01 0.01

%

Feedthrough Attenuation Ratio T

j

=

25˚C, C

h

=

0.01 µF 86 96 86 90 dB
at 1 kHz
Output Impedance T

j

=

25˚C, “HOLD” mode 0.5 1 0.5 1 Ω

Full Temperature Range 4 6 Ω

“HOLD” Step, (Note 6) T

j

=

25˚C, C

h

=

0.01µF, V

OUT

=

0 0.5 1 1.0 1 mV

Supply Current, (Note 5) T

j

≥25˚C 4.5 5.5 4.5 6.5 mA

Logic and Logic Reference Input T

j

=

25˚C 2 10 2 10 µA
Current
Leakage Current into Hold T

j

=

25˚C, (Note 7) 30 100 30 100 pA
Capacitor (Note 5) Hold Mode
Acquisition Time to 0.1

%

∆V

OUT

=

10V, C

h

=

1000 pF 4 6 4 6 µs

C

h

=

0.01 µF 20 25 20 25 µs

Hold Capacitor Charging Current V

IN−VOUT

=

2V 5 5 mA

Supply Voltage Rejection Ratio V

OUT

=

0 90 110 90 110 dB

Differential Logic Threshold T

j

=

25˚C 0.8 1.4 2.4 0.8 1.4 2.4 V

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.

Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is P

D

=

(T

JMAX−TA

)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum

junction temperature, T

JMAX

, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C.

Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the nega­tive supply.

Note 4: See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices.
Note 5: These parameters guaranteed over a supply voltage range of

±

5to±18V, and an input range of −VS+ 3.5V ≤ VIN≤ +VS− 3.5V.

Note 6: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF,for instance, will create an additional 0.5 mV step
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.

Note 7: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.

Note 8: Amilitary RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing

#

5962-8760801GA or to

MIL-STD-38510 part ID JM38510/12501SGA.

Typical Performance Characteristics

Note 9: See Definition of Terms

Aperture Time

(Note 9)

DS005692-17

Dielectric Absorption
Error in Hold Capacitor

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Dynamic Sampling Error

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Typical Performance Characteristics (Continued)

Note 10: See Definition

Output Droop Rate

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Hold Step

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“Hold” Settling Time

(Note 10)

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Leakage Current into Hold
Capacitor

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Phase and Gain (Input to
Output, Small Signal)

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Gain Error

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Power Supply Rejection

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Output Short Circuit Current

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Output Noise

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Typical Performance Characteristics (Continued)

Logic Input Configurations

Input Bias Current

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Feedthrough Rejection Ratio
(Hold Mode)

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Hold Step vs Input Voltage

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Output Transient at Start
of Sample Mode

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Output Transient at Start
of Hold Mode

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TTL & CMOS

3V ≤ V

LOGIC

(Hi State) ≤ 7V

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Threshold=1.4V

DS005692-34

Threshold=1.4V

*

Select for 2.8V at pin 8

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