NSC DS90C032TM, DS90C032MDC, DS90C032E-MIL, DS90C032BW-QML, DS90C032TMX Datasheet

DS90C032
LVDS Quad CMOS Differential Line Receiver

General Description

The DS90C032 is a quad CMOS differential line receiver de­signed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support data
rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Volt­age Differential Signaling (LVDS) technology.

The DS90C032 accepts low voltage (350 mV) differential in­put signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE

®

function
that may beusedtomultiplex outputs. The receiver also sup­ports OPEN, shorted and terminated (100Ω) input Fail-safe.
Receiver output will be HIGH for all fail-safe conditions.

The DS90C032 and companion line driver (DS90C031) pro­vide a new alternative to high power psuedo-ECL devices for
high speed point-to-point interface applications.

Features

n

>

155.5 Mbps (77.7 MHz) switching rates

n Accepts small swing (350 mV) differential signal levels
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Military operating temperature range option
n Available in surface mount packaging (SOIC) and (LCC)
n Pin compatible with DS26C32A, MB570 (PECL) and

41LF (PECL)

n Supports OPEN, short and terminated input fail-safe
n Compatible with IEEE 1596.3 SCI LVDS standard
n Conforms to ANSI/TIA/EIA-644 LVDS standard
n Available to Standard Microcircuit Drawing (SMD)

5962-95834

Connection Diagrams

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Dual-In-Line

DS011945-1

Order Number

DS90C032TM

See NS Package Number M16A

LCC Package

DS011945-20

Order Number

DS90C032E-QML

See NS Package Number E20A

For complete Military Specifications,

refer to appropriate SMD or MDS.

June 1998

DS90C032 LVDS Quad CMOS Differential Line Receiver

© 1998 National Semiconductor Corporation DS011945 www.national.com

Functional Diagram and Truth Tables

RECEIVER

ENABLES INPUTS OUTPUT

EN EN

*

R

IN+−RIN−

R

OUT

LH X Z

All other combinations V

ID

≥ 0.1V H

of ENABLE inputs V

ID

≤ −0.1V L

Full Fail-safe

OPEN/SHORT

H

or Terminated

DS011945-2

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.3V to +6V

Input Voltage (R

IN+,RIN−

) −0.3V to (VCC+0.3V)

Enable Input Voltage

(EN, EN

*

) −0.3V to (VCC+0.3V)

Output Voltage (R

OUT

) −0.3V to (VCC+0.3V)

Maximum Package Power Dissipation

@

+25˚C
M Package 1025 mW
E Package 1830 mW
Derate M Package 8.2 mW/˚C above +25˚C
Derate E Package 12.2 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range

Soldering (4 sec.) +260˚C

Maximum Junction

Temperature (DS90C032T) +150˚C

Maximum Junction

Temperature (DS90C032E) +175˚C

ESD Rating (Note 7)

(HBM, 1.5 kΩ, 100 pF) ≥ 3,500V
(EIAJ, 0 Ω, 200 pF) ≥ 250V

Recommended Operating
Conditions

Min Typ Max Units

Supply Voltage (V

CC

) +4.5 +5.0 +5.5 V
Receiver Input Voltage GND 2.4 V
Operating Free Air Temperature (T

A

)
DS90C032T −40 +25 +85 ˚C
DS90C032E −55 +25 +125 ˚C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2)

Symbol Parameter Conditions Pin Min Typ Max Units

V

TH

Differential Input High Threshold V

CM

=

+1.2V R

IN+

,

R

IN−

+100 mV

V

TL

Differential Input Low Threshold −100 mV

I

IN

Input Current V

IN

=

+2.4V V

CC

=

5.5V −10

±

1 +10 µA

V

IN

=

0V −10

±

1 +10 µA

V

OH

Output High Voltage I

OH

=

−0.4 mA, V

ID

=

+200 mV R

OUT

3.8 4.9 V

I

OH

=

−0.4 mA, DS90C032T 3.8 4.9 V

Input terminated

V

OL

Output Low Voltage I

OL

=

2 mA, V

ID

=

−200 mV 0.07 0.3 V

I

OS

Output Short Circuit Current Enabled, V

OUT

=

0V (Note 8) −15 −60 −100 mA

I

OZ

Output TRI-STATE Current Disabled, V

OUT

=

0V or V

CC

−10

±

1 +10 µA

V

IH

Input High Voltage EN,

EN

*

2.0 V

V

IL

Input Low Voltage 0.8 V

I

I

Input Current −10

±

1 +10 µA

V

CL

Input Clamp Voltage I

CL

=

−18 mA −1.5 −0.8 V

I

CC

No Load Supply Current EN, EN

*

=

V

CC

or GND, DS90C032T V

CC

3.5 10 mA

Receivers Enabled Inputs Open DS90C032E 3.5 11 mA

EN, EN

*

=

2.4 or 0.5, Inputs Open 3.7 11 mA

I

CCZ

No Load Supply Current EN=GND, EN

*

=

V

CC

DS90C032T 3.5 10 mA

Receivers Disabled Inputs Open DS90C032E 3.5 11 mA

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Switching Characteristics

V

CC

=

+5.0V, T

A

=

+25˚C DS90C032T (Notes 3, 4, 5, 9)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

Differential Propagation Delay High to Low C

L

=

5 pF 1.5 3.40 5.0 ns

t

PLHD

Differential Propagation Delay Low to High V

ID

=

200 mV 1.5 3.48 5.0 ns

t

SKD

Differential Skew |t

PHLD−tPLHD

|(

Figure 1

and

Figure 2

) 0 80 600 ps

t

SK1

Channel-to-Channel Skew (Note 5) 0 0.6 1.0 ns

t

TLH

Rise Time 0.5 2.0 ns

t

THL

Fall Time 0.5 2.0 ns

t

PHZ

Disable Time High to Z R

L

=

2kΩ 10 15 ns

t

PLZ

Disable Time Low to Z C

L

=

10 pF 10 15 ns

t

PZH

Enable Time Z to High (

Figure 3

and

Figure 4

) 4 10 ns

t

PZL

Enable Time Z to Low 410ns

Switching Characteristics

V

CC

=

+5.0V

±

10%,T

A

=

−40˚C to +85˚C DS90C032T (Notes 3, 4, 5, 6, 9)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

Differential Propagation Delay High to Low C

L

=

5 pF 1.0 3.40 6.0 ns

t

PLHD

Differential Propagation Delay Low to High V

ID

=

200 mV 1.0 3.48 6.0 ns

t

SKD

Differential Skew |t

PHLD−tPLHD

|(

Figure 1

and

Figure 2

) 0 0.08 1.2 ns

t

SK1

Channel-to-Channel Skew (Note 5) 0 0.6 1.5 ns

t

SK2

Chip to Chip Skew (Note 6) 5.0 ns

t

TLH

Rise Time 0.5 2.5 ns

t

THL

Fall Time 0.5 2.5 ns

t

PHZ

Disable Time High to Z R

L

=

2kΩ 10 20 ns

t

PLZ

Disable Time Low to Z C

L

=

10 pF 10 20 ns

t

PZH

Enable Time Z to High (

Figure 3

and

Figure 4

) 4 15 ns

t

PZL

Enable Time Z to Low 415ns

Switching Characteristics

V

CC

=

+5.0V

±

10%,T

A

=

−55˚C to +125˚C DS90C032E (Notes 3, 4, 5, 6, 9, 10)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

Differential Propagation Delay High to Low C

L

=

20 pF 1.0 3.40 8.0 ns

t

PLHD

Differential Propagation Delay Low to High V

ID

=

200 mV 1.0 3.48 8.0 ns

t

SKD

Differential Skew |t

PHLD−tPLHD

|(

Figure 1

and

Figure 2

) 0 0.08 3.0 ns

t

SK1

Channel-to-Channel Skew (Note 5) 0 0.6 3.0 ns

t

SK2

Chip to Chip Skew (Note 6) 7.0 ns

t

PHZ

Disable Time High to Z R

L

=

2kΩ 10 20 ns

t

PLZ

Disable Time Low to Z C

L

=

10 pF 10 20 ns

t

PZH

Enable Time Z to High (

Figure 3

and

Figure 4

) 4 20 ns

t

PZL

Enable Time Z to Low 420ns

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