NSC DP8464BV-23, DP8464BV-2 Datasheet
TL/F/5283
DP8464B Disk Pulse Detector
June 1989
DP8464B Disk Pulse Detector
General Description
The DP8464B Disk Pulse Detector utilizes analog and digital
circuitry to detect amplitude peaks of the signal received
from the read/write amplifier fitted with the heads of disk
drives. The DP8464B produces a TTL compatible output
which, on the positive leading edge, indicates a signal peak.
Electrically, these peaks correspond to flux reversals on the
magnetic medium. The signal from the read/write amplifier
when reading a disk is therefore a series of pulses with
alternating polarity. The Disk Pulse Detector accurately replicates the time position of these peaks.
The DP8464B Disk Pulse Detector has three main sections:
the Amplifier, the time channel and the gate channel. The
Amplifier section consists of a wide bandwidth amplifier, a
full wave rectifier and Automatic Gain Control (AGC). The
time channel is made from the differentiator and its following bi-directional one shot, while the gate channel is made
from the differential comparator with hysteresis, the D flipflop and its following bi-directional one shot.
The Disk Pulse Detector is fabricated using an advanced
oxide isolated Schottky process, and has been designed to
function with data rates up to 15 Megabits/second. The
DP8464B is available in either a 300 mil wide 24-pin dual-inline package or a surface mount 28-pin plastic chip carrier
package. Normally, it will be fitted in the disk drive, and its
output may be directly connected to the DP8461 or the
DP8465 Data Separator.
Features
Y
Wide input signal amplitude rangeÐfrom 20 mVpp to
660 mVpp differential
Y
Data rates up to 15 Megabits/sec 2,7 code
Y
On-chip differential gain controlled amplifier, differentiator, comparator gating circuitry, and output pulse
generator
Y
Input capacitively coupled directly from the disk head
read/write amplifier
Y
Adjustable comparator hysteresis
Y
AGC and differentiator time constants set by external
components
Y
TTL compatible digital Inputs and Outputs
Y
Encoded Data Output may connect directly to the
DP8461 or DP8465 Data Separator
Y
Standard drive supply: 12Vg10%
Y
Available in 300 mil wide 24-pin dual-in-line package, a
surface mount 28-pin plastic chip carrier package, or a
40-pin TapePak
É
package
Block Diagram
Pin 5ÐNo connection
Pin 8ÐNo connection
TL/F/5283– 7
Note: All pin numbers in this data sheet refer to the 24-pin dual-in-line package.
TapePakÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Pins Limit
Supply Voltage 9 14V
TTL Input Voltage 11,13 5.5V
TTL Output Voltage 12,14,15 5.5V
Input Voltage 3,4 5.5V
Minimum Input Voltage 3,4
b
0.5V
Differential Input 6-7, 21-22, 3V or
b
3V
Voltage 2-23
ESD Susceptibility (see Note 5)
Storage Temperature
b
65§Ctoa150§C
Lead Temp. (Soldering, 10 seconds) 300
§
C
Maximum Power Dissipation at 25§C
Molded DIP Package
(derate 15.6 mW/
§
C above 25§C) 1950 mW
Plastic Chip Carrier Package
(derate 12.5 mW/
§
C above 25§C) 1560 mW
Operating Conditions
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage 10.8 12.0 13.2 V
T
A
Ambient Temperature 0 70§C
DC Electrical Characteristics Over Recommended Operating Temperature and Supply Range V
REF
e
0.5V,
Set Hysteresis
e
0.3V. Read/Writee0.3V unless otherwise noted. All Pin Numbers Refer to 24 Pin Dual-In-Line Package.
Symbol Pins Parameter Conditions Min Typ Max Units
AMPLIFIER
Z
IN
AI
6,7 Amp In Impedance T
A
e
25§C 0.75 1.0 1.25 kX
(Note 1)
A
VMIN
18,19 Min Voltage Gain AC Output 4 Vpp 6.0 V/V
Differential
A
VMAX
18,19 Max Voltage Gain AC Output 4 Vpp 200 V/V
Differential
V
C
AGC
16 Voltage on C
AGC
A
V
e
6.0 4.5 5.5 V
A
V
e
200 2.8 3.7 V
GATE CHANNEL
Z
IN
GCI
21,22 Gate Channel Input T
A
e
25§C 1.75 2.5 3.25 kX
Impedance (Note 1)
I
C
AGC
b
16 Pin 16 Current which V
PIN 16
e
3.9V
b
1.5
b
2.5
b
3.5 mA
Charges C
AGC
l
V
PIN 21
b
V
PIN 22
l
e
1.3 V
DC
I
C
AGC
a
16 Pin 16 Current which V
PIN 16
e
5V 1 5 mA
Discharges C
AGC
l
V
PIN 21
b
V
PIN 22
l
e
0.7 V
DC
I
V
REF
4V
REF
Input Bias
b
20
b
100 mA
Current
V
TH
AGC
22,21 AGC Threshold (Note 2) 0.88 1.0 1.12 V
4,16 V
PIN 16
e
4.2V
I
SH
3 Set Hysteresis Input
b
60
b
100 mA
Bias Current
V
TH
SH
22,21 Set Hysteresis (Note 3) 0.48 0.6 0.72 V
3,15 Threshold
TIME CHANNEL
Z
IN
TC
2,23 Time Channel Input T
A
e
25§C 3.5 5.0 6.5 kX
Impedance (Note 1)
I
C
d
24 Current into Pin 1 and 1.4 1.8 2.50 mA
24 that Discharges
C
d
2
DC Electrical Characteristics Over Recommended Operating Temperature and Supply Range V
REF
e
0.5V,
Set Hysteresis
e
0.3V. Read/Writee0.3V unless otherwise noted. All pin numbers refer to the 24 pin dual-in-line package.
(Continued)
Symbol Pins Parameter Conditions Min Typ Max Units
WRITE MODE
Z
IN
AI
6,7 Amp In Impedance V
PIN 11
e
2.0V 50 250 X
in Write Mode
I
C
AGC
b
16 Pin 16 Current V
PIN 11
e
2.0V 1 5 mA
in Write Mode V
PIN 16
e
3.9V
l
V
PIN 21
b
V
PIN 22
l
e
1.3 V
DC
DIGITAL PINS
V
IH
11,13 High Level Input 2 V
Voltage
V
IL
11,13 Low Level Input 0.8 V
Voltage
V
I
11,13 Input Clamp V
CC
e
Min
b
1.5 V
Voltage I
I
eb
18 mA
I
IH
11,13 High Level Input V
CC
e
Max 20 mA
Current V
I
e
2.7V
I
I
11,13 Input Current at V
CC
e
Max 1 mA
Maximum Input V
I
e
5.5V
Voltage
I
IL
11,13 Low Level Input V
CC
e
Max
b
200 mA
Current V
I
e
0.5V
V
OH
12,14, High Level Output V
CC
e
Min 2.7 V
15 Voltage I
OH
eb
40 mA
(Note 4)
V
OL
12,14, Low Level Output V
CC
e
Min 0.5 V
15 Voltage I
OL
e
800 mA
(Note 4)
I
OS
12,14, Output Short V
CC
e
Max
b
100 mA
15 Circuit Current V
O
e
OV
I
CC
9 Supply Current V
CC
e
Max 54 75 mA
AC Electrical Characteristics
Over Recommended Operating Temperature and Supply Range unless otherwise noted
Symbol Pins Parameter Conditions Typ Max Units
DP8464B-2 14 Pulse Pairing (See Pulse Pairing Set Up)
g
1.5
g
3ns
t
pp
DP8464B-3 14 Pulse Pairing (See Pulse Pairing Set Up)
g
2
g
5ns
t
pp
DP8464B-1 14 Pulse Pairing (See Pulse Pairing Set Up)
g
0.5
g
1ns
t
pp
at 25§CV
CC
e
12V only
Note 1: The temperature coefficient of the input impedance is typically 0.05% per degree C.
Note 2: The AGC Threshold is defined as the voltage across the Gate Channel Input (pins 21 and 22) when the voltage on C
AGC
(pin 16) is 4.2V.
Note 3: The Set Hysteresis Threshold is defined as the minimum differential AC signal across the Gate Channel Input (pins 21 and 22) which causes the voltage on
the Channel Alignment Output (pin 15) to change state.
Note 4: To prevent inductive coupling from the digital outputs to Amp In, the TTL outputs should not drive more than one ALS TTL load each.
Note 5: The following pins did not meet the 2000V ESD test with the human body model, 120 pF thru 1.5 kX: Pins 1, 2, 3, 10, 11, 12, 14, 21, 24.
3
Pulse Pairing Set Up
* Transformer (T1) is
Tektronix CT-2 current
probe or equivalent
TL/F/5283– 3
DP8464B
f
e
2.5 MHz
V
IN
e
40 mVppdifferential
V
REF
e
0.50V
C
D
e
50 pF
R
D
e
430X
Filter
R1e240X R2e680X
C1e15 pF C2e100 pF
L1
e
4.7 mH
This is a 3 pole Bessel with the corner frequency at 7.5
MHz.
TL/F/5283– 4
Pulse Pairing Measurement
Connect a scope probe to pin 14 (Encoded Data Out) and
trigger off its positive edge. Adjust the trigger holdoff so the
scope first triggers off the pulse associated with the positive
peak and then off the pulse associated with the negative
peak (as shown in the scope photo below). Pulse pairing is
displayed on the second pair of pulses on the display. If the
second pulses are separated by 4 ns, then the pulse pairing
for this part is
g
2 ns.
Circuit Operation
The output from the read/write amplifier is AC coupled to
the Amp Input of the DP8464B. The amplifier’s output voltage is fed back via an external filter to an internal fullwave
rectifier and compared against the external voltage on the
V
REF
pin. The AGC circuit adjusts the gain of the amplifier
to make the peak to peak differential voltage on the Gate
Channel Input four times the DC voltage on V
REF
. Typically
the signal on Amp Out will be set for 4 Vpp differential.
Since the filter usually hasa6dBloss, the signal on the
Gate Channel Input will be 2 Vpp differential. The user
should therefore set 0.5V on V
REF
which can be done with a
simple voltage divider from the
a
12V supply.
The peak detection is performed by feeding the output of
the Amplifier through an external filter to the differentiator.
The differentiator output changes state when the input pulse
changes direction, generally this will be at the peaks. However, if the signal exhibits shouldering (the tendency to return to the baseline), the differentiator will also respond to
noise near the baseline. To avoid this problem, the signal is
also fed to a gating channel which is used to define a level
either side of the baseline. This gating channel is comprised
4
Circuit Operation (Continued)
of a differential comparator with hysteresis and a D flip-flop.
The hysteresis for this comparator is externally set via the
Set Hysteresis pin. In order to have data out, the input amplitude must first cross the hysteresis level which will
change the logic level on the D input of the flip-flop. The
peak of the input signal will generate a pulse out of the
differentiator and bi-directional one shot. This pulse will
clock the new data at the D input through to the output. In
this way, when the differentiator is responding to noise at
the baseline, the output of the D flop is not changing since
the logic level into the D input has not changed. The comparator circuitry is therefore a gating channel which prevents any noise near the baseline from contaminating the
data. The amount of hysteresis is twice the DC voltage on
the Set Hysteresis pin. For instance, if the voltage on the
Set Hysteresis pin is 0.3V, the differential AC signal across
the Gate Channel Input must be larger than 0.6V before the
output of the comparator will change states. In this case,
the hysteresis is 30% of a 2V peak to peak differential signal at the gate channel input.
Connection Diagrams
Dual-In-Line (DIP) Package
TL/F/5283– 2
Top View
Order Number DP8464BN-3 or DP8464BN-2
See NS Package N24C
Plastic Chip Carrier (PCC) Package
TL/F/5283– 30
Order Number DP8464BV-3, DP8464BV-2 or DP8464BV-1
See NS Package V28A
5
Pin Definitions
(All pin numbers refer to the 24 pin dual-in-line package)
Pin
Ý
Name Function
Power Supply
9V
CC
The supply isa12Vg10%.
17 Digital Digital signals should be referenced
Ground to this pin.
20 Analog Analog signals should be referenced
Ground to this pin.
Analog Signals
6 Amp In
a
These are the differential inputs to
7 Amp In
b
the Amplifier. The output of the read/
write head amplifier should be capacitively coupled to these pins.
18 Amp Out
a
These are the differential outputs of
19 Amp Out
b
the Amplifier. These outputs should
be capacitively coupled to the gating
channel filter (if required) and to the
time channel filter.
22 Gate These are the differential inputs to
21 Channel the AGC block and the gating chan-
Inputs nel. These inputs must be capacitive-
ly coupled from the Amp Out.
2 Time These are the differential inputs to
Channel the differentiator in the time channel.
Input
a
In most applications, a filter between
23 Time the Amp Out (pins 18 and 19) and
Channel these inputs is required to band limit
Input
b
the noise and to correct for any
phase distortion introduced by the
read circuitry. In all cases this input
must be capacitively coupled to prevent disturbing the DC input level.
1C
d
a
The external differentiator network is
24 C
d
b
connected between these two pins.
3 Set The DC voltage on this pin sets the
Hysteresis amount of hysteresis on the differen-
tial comparator. Typically this voltage
can be established by a simple resistive divider from the positive supply.
4V
REF
The AGC circuit adjusts the gain of
the amplifier to make the differential
peak to peak voltage on the Gate
Channel Input equal to four times the
DC voltage on this pin. This voltage
can be established by a simple resistive divider from the positive supply.
5 No connection
8 No connection
16 C
AGC
The external capacitor for the AGC is
connected between this pin and Analog Ground.
Pin
Ý
Name Function
Digital Signals
10 Set Pulse An external capacitor to control the
Width pulse width of the Encoded Data Out
is connected between this pin and
Digital Ground.
11 Read
/Write If this pin is low, the Pulse Detector is
in the read mode and the chip is active. When this pin goes high, the
pulse detector is forced into a standby mode. This is a standard TTL input.
12 Time This is the TTL output from the bi-di-
Pulse rectional one shot following the difOut ferentiator. In most applications this
can be connected directly to the
Time Pulse In.
13 Time This is the TTL input to the clock of
Pulse the D flip-flop. Usually this is conIn nected directly to the Time Pulse Out
pin.
15 Channel This is the buffered output of the dif-
Alignment ferential comparator with hysteresis.
This is usually used in the initial system design and is not used in production.
14 Encoded This is the standard TTL output
Data Out whose leading edge, indicates the
time position of the peaks.
Application Information
GENERAL DESCRIPTION
All pin numbers refer to 24 pin dual-in-line package.
The DP8464B Disk Pulse Detector utilizes analog and digital
circuitry to detect amplitude peaks of the signal received
from the Read/Write Amplifier. The analog signal from a
disk is a series of pulses, the peaks of which correspond to
1’s or flux reversals on the magnetic medium. The pulse
detector must accurately determine the time position of
these peaks. The peaks are indicated by the positive leading edge of a TTL compatible output pulse. This task is complicated by variable pulse amplitudes depending on the media type, head position, head type and read/write amplifier
circuit gain. Additionally, as the bit density on the disk increases, the amplitude decreases and significant bit interaction occurs resulting in pulse distortion and shifting of the
peaks.
The graph in
Figure 1
shows how the pulse amplitude varies
with the number of flux reversals per inch (or recording density) for a given head disk system. The predominant disk
applications are associated with the first two regions on this
graph, Regions 1 and 2. Typical waveforms received by the
pulse detector for these regions are shown next to the
graph.
6
Application Information (Continued)
Region 1 is the high resolution area characterized by a large
spread between flux reversals and a definite return to baseline (no signal) between these peaks. Pulses of this type are
predominantly found in drives which use either thin film
heads or plated media, or in drives which utilize run length
limited codes (like the 2,7 code) which spread the distance
between flux reversals.
A Region 2 waveform will vary from a tendency to return to
the baseline (called shouldering) to almost sinusoidal at the
higher frequencies. These pulses come from drives which
use limited frequency codes (such as MFM). The pulses
may contain shouldering on the outer tracks of the disk and
be nearly sinusoidal on the inner tracks since the flux density increases towards the inner track.
Detecting pulse peaks of waveforms of such variable characteristics requires a means of separating both noise and
shouldering-caused errors from the true peaks. In the past,
mild shoulder-caused errors were blocked by self-gating circuits (such as the ‘‘de-snaker’’). These circuits fail when
shouldering is extensive, hence the need for the DP8464B
which includes a peak sensing circuit and an amplitude sensitive gating channel in parallel.
The main circuit blocks of the DP8464B are shown in
Figure
2
. The output from the read/write amplifier is fed directly to
the Amp Input of the DP8464B. This is the input of a Gain
Controlled Amplifier. The amplifier’s output voltage is fed
back via an external filter to an internal fullwave rectifier and
compared against the external voltage on the V
REF
pin. The
AGC circuit adjusts the gain of the amplifier to make the
peak-to-peak differential Gate Channel input voltage four
times the DC voltage on V
REF
.
The peak detection is performed by feeding the output of
the Gain Controlled Amplifier through an external filter to
the differentiator. The differentiator output changes state
when the input pulse changes direction, generally this will
be at the peaks. However, if the signal exhibits shouldering
(the tendency to return to the baseline) as seen in Region 1
and the upper part of Region 2, the differentiator will also
respond to noise near the baseline. To avoid this, the signal
is also fed to a gating channel which is used to define a
level either side of the baseline. This gating channel comprises a differential comparator with hysteresis and a D flipflop. The hysteresis for this comparator is externally set via
the Set Hysteresis pin. In order to have valid data out, the
input amplitude must first cross the hysteresis level. This will
change the logic level on the D input of the flip-flop. The
peak of the input signal will generate a pulse out of the
differentiator and bi-directional one shot. This pulse will
clock in the new data on the D input, which will appear at
the Q output. In this way, when the differentiator is responding to noise at the baseline, the output of the D flop is not
changing since the logic level into the D input has not yet
changed. The comparator circuitry is therefore a gating
channel to prevent any noise near the baseline from contaminating the data.
The amount of hysteresis is twice the DC voltage on the Set
Hysteresis pin. For instance, if the voltage on the Set Hysteresis pin is 0.3V, the differential Gate Channel Input must
be larger than 0.6V (
g
0.3V) before the output of the comparator will change states. The Time Pulse Out, Encoded
Data, and Channel Alignment Output are designed to drive 1
standard TTL gate.
TL/F/5283– 5
TL/F/5283– 6
FIGURE 1. Pulse Amplitude vs. Bit Density with Typical Waveforms
7
Block Diagram
Pin 5ÐNo connection
Pin 8ÐNo connection
TL/F/5283– 7
FIGURE 2. DP8464B Block Diagram, Region 1 Connection
8
Loading...