NSC DP8459V-10 Datasheet

DP8459 All-Code Data Synchronizer

General Description

The DP8459 Data Synchronizer is an integrated phase locked loop circuit which has been designed for application in magnetic hard disk, ﬂexible (ﬂoppy) disk, optical disk, and tape drive memory systems for data re-synchronization and clock recovery with any standard recording code, operating to 25 Mb/s. The DP8459 is provided in a 28-pin PCC package. Zero phase start is employed during both data and reference clock lock sequences for rapid acquisition. An optional (Customer-controlled) synchronization ﬁeld frequency-acquisition feature guarantees lock, accommodating the preamble types used with GCR (Group Code Recording), MFM (Modiﬁed Frequency Modulation), the [1,N] run length limited (RLL) codes, and either of the standard 2,7 RLL codes. Precise synchronization window generation is achieved via an internal, self-aligning delay line which remains accurate independent of temperature, power supply, external component and IC process variations. The DP8459 also incorporates a digitally controlled ( MICROW-

™

IRE

bus compatible) strobe function with 5-bit resolution which allows for margin testing, error recovery routines, and precise window calibration. The PLL ﬁlter resides external to the chip, with two ports provided to allow signiﬁcant design ﬂexibility.Synchronizationpattern detection circuitry issues a

PREAMBLE DETECTED signal when a pre-determined length of the user-selected pattern is encountered. All digital input and output signals are TTL compatible and a single, +5V power supply is required. The DP8459V is offered as a DP8459V-10 (250 Kbit/sec thru 10 Mbits/sec) or DP8459V-25 (250 Kbits/sec thru 25 Mbit/sec), see AC Electrical Characteristics.

Features

n Fully integrated dual-gain PLL n Zero phase start lock sequence n 250 Kbit/sec–25 Mbit/sec data rate range n Frequency lock capability (optional) for all standard

recording codes

n Digital window strobe control, 5-bit resolution n Two-port PLL ﬁlter network n PLL free-run (Coast) control for optical disk defects n Synchronization pattern (preamble lock) detection n Non-glitching multiplexed read/write clock output n +5V supply n DP8459 supplied in 28-pin plastic chip carrier (PCC)

and 40-pin TapePak packages

ADVANCED

December 1995

DP8459 All-Code Data Synchronizer

DP8459

Connection Diagrams

TL/F/9322-6

FIGURE 1. DP8459 in 28-Pin Plastic Chip Carrier (PCC) V-Type Package Order Number DP8459V-10 or DP8459V-25

TapePak®is a registered trademark of National Semiconductor Corporation.

™

MICROWIRE

is a trademark of National Semiconductor Corporation.

PrintDate=1996/07/31 PrintTime=11:05:38 ds009322 Rev. No. 1 Proof 1

Connection Diagrams

TapePak

Top ViewOrder Number DP8459TP-10 or DP8459TP-25See NS Package TP40A

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System Diagram

TL/F/9322-8

FIGURE 2. DP8459 System Block Diagram

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1.0 Pin Descriptions

DP8459 28-pin PCC package

POWER SUPPLY

16 DIGITAL V

4 ANALOG V

13 DIGITAL GROUND.

3 ANALOG GROUND.

TTL LEVEL LOGIC INPUTS

5 READ GATE (RG): Read mode control input, active high (logical-one). Assertion causes the PLL to lock to

the ENCODED READ DATA, employing a zero phase start routine. Deassertion causes the PLL to lock the REFERENCE CLOCK input, also employing a zero phase start routine. READ GATE timing is allowed to be fully asynchronous.

6, 7, 8 RANGE SELECT 0, 1, 2 (RS0, RS1, RS2): Control the operating frequency range of the VCO. A 2:1

continuously variable sub-range is available within each of 6 allowed selections, enabling the VCO to operate at any frequency within a 96:1 range from 500 kHz to 50 MHz.

9 CONTROL REGISTER ENABLE (CRE): A logical Low level allows the CONTROL REGISTER CLOCK to

clock data into the Control Register via the CONTROL REGISTER DATA input; a logical HIGH level

latches the register data and issues the information to the appropriate circuitry. 10 CONTROL REGISTER DATA (CRD): Control Register data input. 11 CONTROL REGISTER CLOCK (CRC): Negative edge triggered Control Register clock input. 12 ENCODED READ DATA (ERD): Incoming TTL-level data derived from the storage media; issued from a

pulse detector circuit. Each positive edge represents a single recorded code bit. 14 REFERENCE CLOCK (RFC): A reference frequency input required for DP8459 operation. The RFC

frequency must be accurate and highly stable (crystal or servo derived) and equivalent to the 2F frequency

for the MFM or [2,7] codes (i.e., equal to, but not derived from the VCO frequency). 18 FREQUENCY LOCK CONTROL (FLC): Selects or de-selects the frequency lock function during a READ

operation. Has no effect with READ GATE deasserted; frequency lock is automatically employed for the full

duration of time READ GATE is deasserted regardless of the level of the FLC input. With READ GATE

high and FLC low (logical-zero) the PLL is forced to lock to the pattern frequency selected via the SYNC

PATTERN SELECT inputs. When high (logical-one) frequency lock action is terminated and the PLL

employs a pulse gate to accommodate random disk data patterns. FLC may be tied to PREAMBLE

DETECTED output pin for self-regulated frequency lock control. FLC timing is allowed to be fully

asynchronous.

20, 19 SYNC PATTERN SELECT 0, 1 (SP0, SP1): Control inputs for selection of the preamble type being

employed. These inputs determine the pattern to which the PLL will frequency-lock during preamble

acquisition (if frequency lock is employed) and for which the PREAMBLE DETECTED circuitry searches. 24 COAST (CST): Control for Coast function. The Coast function may be activated when READ GATE is

either high or low. When the COAST input is low (logical-zero), the phase comparator is disabled and held

in a cleared state, allowing the VCO to coast regardless of ENCODED READ DATA input activity (READ

GATE high) or REFERENCE CLOCK input activity (READ GATE low). No other circuit functions are

disturbed. When high (logical-one), the phase comparator operates normally. 27 HIGH-GAIN DISABLE (HGD): Charge Pump gain switch control. When low (logical-zero), the charge pump

input current is the combined value of the currents at both R

(logical-one), charge pump input current is taken from the R

READ GATE or PREAMBLE DETECTED for self-regulated gain control.

TTL LEVEL LOGIC OUTPUTS

15 SYNCHRONIZED CLOCK (SCK): Issues the VCO signal following READ GATE assertion and completion

of zero phase start sequence; issues REFERENCE CLOCK input signal when READ GATE is deasserted.

Multiplexer switching is achieved without glitches. 17 PREAMBLE DETECTED (PDT): Issues a high level (logical-one) following assertion of READ GATE,

completion of the zero phase start sequence, and the detection of approximately 32 sequential pulses of

1T, 2T or 3T period preamble, or 16 sequential pulses of 4T period preamble, depending on state of SYNC

PATTERN SELECT inputs (T=VCO period). Following preamble detection, the output remains latched

high until de-assertion of READ GATE. The PDT output will be at a logical zero state whenever READ

GATE is inactive.

: 5.0V±5%. (Note 1 )

and R

BOOST

pin only. HGD may be tied either to

NOMINAL

pins. When high

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1.0 Pin Descriptions (Continued)

TTL LEVEL LOGIC OUTPUTS

21 SYNCHRONIZED DATA (SD): A reconstructed replica of the ENCODED READ DATA signal,

22 PUMP UP (PU): Active HIGH whenever the phase comparator issues a pump-up signal to the charge

23 PUMP DOWN (PD): Active HIGH whenever the phase comparator issues a pump-down signal to the

ANALOG SIGNAL PINS

28 CHARGE PUMP OUTPUT: The output of the high-speed, switching bi-directional current source circuitry of

1 VCO INPUT: The high-impedance control voltage input to the voltage controlled oscillator (VCO). The

2 TIMING EXTRACTOR FILTER: A pin for the connection of external, passive components employed to

25 R

26 R

Note 1: These pins should always be tied together; they are not intended to be used with separate power supplies.

time-stabilized and synchronized to the SYNCHRONIZED CLOCK output.

pump. The PU pin is an open-emitter output requiring an external passive pull down resistor whenever in active use. The output should be allowed to ﬂoat when not needed.

charge pump. The PD pin is an open-emitter output requiring an external passive pull down resistor whenever in active use. The output should be allowed to ﬂoat when not needed.

the charge pump. The external, passive PLL ﬁlter network is established between this pin, the VCO INPUT pin, and ground.

external, passive PLL ﬁlter network is established between this pin, the CHARGE PUMP OUTPUT pin, and ground.

stabilize the delay line timing extraction circuitry. Delay accuracy is not a function of external component values or tolerances.

: A resistor is tied between this pin and VCCto set the charge pump

NOMINAL

The current is internally multiplied by 2 for charge pump use.

: A resistor is tied between this pin and VCCto set the charge pump

BOOST

resistor is effectively paralleled with the R

BOOST

inactive (logical-zero); thus the sum of the resistor currents sets the total input current. The input current is

resistor when the HIGH GAIN DISABLE input is

NOMINAL

nominal

operating current.

boost

(or adder) current. The

multiplied by 2 within the charge pump circuitry.

2.0 Circuit Operation

In the non-Read mode, the DP8459 PLL is locked to the REFERENCE CLOCK signal. This permits the VCO to remain at a frequency very close to the encoded data clock rate while the PLL is “idling” and thus will minimize the frequency step and associated lock time encountered at the initiation of lock to ENCODED READ DATA. Frequency acquisition is employed in the non-Read mode to ensure lock.

Note: The REFERENCE CLOCK signal is employed bycircuitrywhich sets the time delay of the internal delay line. This requires the REFERENCE CLOCK signal to be present DP8459 operation.

at all times

at a stable and accurate frequency for proper

At the assertion of READ GATE, which is allowed to be done asynchronously (no timing requirements), and following the completion of two subsequent VCO cycles, the DP8459 VCO is stopped momentarily and restarted in accurate phase alignment with the second data bit which arrives following the VCO pause. This minimization of phase misalignment between the ENCODED READ DATAand the VCO (referred to as zero phase start, or ZPS) signiﬁcantly reduces data lock acquisition time.

The DP8459 incorporates a preamble-speciﬁc frequency acquisition feature which may be employed at the user’s option. The frequency acquisition feature is intended speciﬁcally for use within hard or pseudo-hard sectored systems where READ GATE is asserted only within a preamble. With the READ GATE active (logical-one) and the FREQUENCY LOCK CONTROL (FLC) input active (logical-zero), the DP8459 will be forced to lock to the exact preamble frequency selected at the SYNC PATTERN SELECT inputs. The frequency discriminating action of the PLL

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provided in this mode produces a lock-in range equivalent to the available VCO operating range and thus eliminates the possibility of fractional-harmonic lock. Windowing (pulse gate action; see Pulse Gate, Section 2.1) is not employed in the frequency acquisition mode and thus quadrature lock is prevented (see National Semiconductor Application Note AN-414, APPS Mass Storage Handbook

1, 1986, for an explanation of typical false lock modes). The DP8459 will remain in the frequency acquisition mode until the FLC input is deactivated (logical-one). In ordinary hard sectored or pseudo-hard sectored operation, the PREAMBLE DETECTED (PDT) output is tied to the FLC input for automatic switching from frequency acquisition to phase lock following internal detection of the selected preamble by the DP8459. The Customer may choose to intervene in this path and extend the frequency lock period. However, the DP8459

must

be placed in the phase lock mode (FLC deactivated—logical-one) prior to encountering the end of the preamble, or loss of lock will result. Switching of the FLC input may be done asynchronously (no set-up or hold timing requirements).

The PREAMBLE DETECTED (PDT) output will become active (logical-one) following READ GATE assertion, completion of the ZPS sequence and the subsequent detection of approximately 32 ENCODED READ DATA(ERD) pulses of the 1T, 2T or 3T preamble types, or 16 ENCODED READ DATA (ERD) pulses of the 4T preamble type (see speciﬁcation tables), and will remain active (logical-one) until deassertion of READ GATE.

The Customer has the option of employing an elevated PLL bandwidth during preamble acquisition (or at any other time) for an extended capture range. An R

pin is provided to

BOOST

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allow for an increase in charge pump gain above the level set by the R (HGD) is inactive (logical-zero), the R electrically paralleled with the R charge pump gain. When HIGH GAIN DISABLE is active (logical-one), only the R pump current. The Charge Pump throughput gain is I I

where I

NOM

to conﬁgure the system for high gain prior to DP8459 preamble

pin. When the HIGH GAIN DISABLE pin

NOMINAL

resistor is employed to set the

NOMINAL

0.25V

||R

CC/Rp,Rp

with HGD low.The Customer may choose

BOOST

NOM

resistor is

BOOST

for an elevated

with HGD high, and

CPO

detection by tying the HGD pin to the PDT output pin, or for high gain only during REFERENCE CLOCK lock by tying the HGD pin to the READ GATE pin. Other conﬁgurations may be employed, if desired.

The DP8459 issues a clock waveform from the SYNCHRONIZED CLOCK output which is derived from the REFERENCE CLOCK input when the READ GATE is inactive (logical-zero), and from the VCO signal following READ GATE assertion (logical-one) and completion of the zero phase start sequence. The REFERENCE CLOCK signal is issued from the SYNCHRONIZED CLOCK output during non-Read activity and may be used as a write clock, if desired. Once data lock is achieved and the SYNCHRONIZED CLOCK output is issuing VCO, the SYNCHRONIZED DATA output and the SYNCHRONIZED CLOCK output are held in a ﬁxed, speciﬁed timing relationship for use by decoding/deserializing circuitry. The SYNCHRONIZED CLOCK output multiplexer switching is achieved without glitches, i.e., no pulse is narrower than 50 of the VCO or REFERENCE CLOCK period.

The DP8459 provides a COAST control input which serves to clear the phase comparator and disable charge pump action whenever taken to an active, logical-zero level. This function is made available to allow the PLL to be set to free-run, undisturbed, while a detectable defect is being read from the media in a region where re-initiation of the lock procedure is impractical (e.g., data ﬁeld). External data controller circuitry is responsible for the detection of the defect and issuance of the COAST command. The primary application of this feature is expected to be optical disk bright-spot avoidance, though it will lend itself to other applications as well.

As in the previous family of National Semiconductor data separators/synchronizers, the DP8459 provides phase comparator activity information to the Customer. The phase comparator’s pump-up and pump-down outputs are brought out to separate pins, PUMP UP (PU) and PUMP DOWN (PD). The outputs are of the open-emitter type, requiring an external “pull-down” resistor when in active use. These outputs serve to indicate the relative displacement of the current data bit with respect to the internal VCO phase (window center). When in completely stabilized lock with no bit displacement, the output(s) will issue a pulse of a ﬁnite, minimum-valued width for each arriving data pulse. If any data pulse is displaced with respect to the VCO phase, the corresponding output pulse will widen by an amount equivalent to the bit displacement. These output signals may be integrated over time and employed to

determine the average magnitude of media bit shift. Additionally, the pulse widening/narrowing effect bit displacement has on the PU/PD outputs produces an amplitude modulation of the output’s waveform. The waveform envelope, when observed with a relatively slow oscilloscope time base, can be employed for observation of PLL dynamics. This is particularly useful if intrusive probing of the PLL ﬁlter nodes is not desirable.

It is strongly recommended that the PU/PD outputs be left “ﬂoating” (unconnected to any net or circuit element, including the output pull-down resistor) in any application where they are not speciﬁcally needed. This will serve to minimize unnecessary, spurious digital switching transients in the vicinity of the DP8459, and thus improve noise performance.

The DP8459 provides a wide operating data rate range to facilitate use within a broad base of applications, including multiple data rate systems or constant density recording (CDR). In order to achieve the speciﬁed 250 kbit /sec to 25 Mbit/sec span, the operation of the VCO has been divided into 6 contiguous frequency sub-ranges, with approximately a 2:1 ratio between adjacent range selections. Three inputs are provided for selecting of the sub-ranges, RANGE SELECT 0, 1 and 2. Some code type restrictions have been placed on the higher ranges of operating VCO frequency. See the operating data rate truth table and allowed code type versus VCO range selection.

The DP8459 allows for ﬂexible synchronization window strobe

control. The inputs CONTROL REGISTER DATA (CRD), CONTROL REGISTER CLOCK (CRC), and CONTROL REGISTER ENABLE (CRE) are conﬁgured to permit interfacing of the DP8459 to the MICROWIRE™(or equivalent) bus for entry of strobe information. Information is serially shifted into the CONTROL REGISTER via the CRD and CRC pins whenever the CRE pin is active (logical-zero). When the CRE pin is inactive (logical-one), CRD and CRC are ignored. The strobe function allows the Customer to shift the synchronization window in 31 equal steps of magnitude t x [1.8%x τ respect to nominal window position. This function may be

] from approximately 27%early to 27%late with

VCO

employed for margin testing (eg., approximately error recovery read re-try operations (eg., approximately

3%). Additionally, this feature allows the Customer to align the center of the synchronization window to within one half strobe step of ideal, regardless of the initial performance or speciﬁcation of the DP8459. This window centering function may be performed completely within the drive system itself (auto-alignment) given the employment of an intelligent window alignment routine. Such a routine would be conﬁgured to determine the maximum error free early and late window positions via the strobe function, and then would ﬁx the DP8459 window in the arithmetic mean position (Section

4.3.3). See

Note: In all DP8459 applications, provision must be made to load the appropriate information into the Control Register.

Figure 4

for a window strobe truth table.

Figure 3

12%)or

for

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RANGE SELECT Input Equivalent Minimum N (Allowed Code Type)

( Note 1 ) VCO Range NRZ Data Rate

2 1 0 MHz MFM or 2,7 1 2 3 4

(Mbit/sec) (GCR) (MFM; 1, N) (2,7) (2,7)

1 1 X 0.50 ≤ Fvco ≤ 1.25 0.250≤ Fnrz ≤ 0.625 1 0 1 1.25<Fvco ≤ 2.5 0.625<Fnrz ≤ 1.25 1 0 0 2.5<Fvco ≤ 5 1.25<Fnrz ≤ 2.5 01 1 5 01 010 00X20

Fvco ≤ 10 2.5<Fnrz ≤ 5

Fvco ≤ 20 5<Fnrz ≤ 10 N/A

Fvco ≤ 50 10<Fnrz ≤ 25 N/A

√√√√ √√√√ √√√√ √√√√

√√√ √√√

(Note3)

Note 1: N/A—Not Allowed. Note 2: Operation slightly beyond listed range boundaries may be acceptable in some applications.At or near range boundaries, range selection should be made

to place the operating frequency near the UPPER boundary; e.g., use RS2=0, RS1=1, and RS0=0 for 10 Mb/s. Note 3: 20 MHz

Fvco ≤ 38 MHz for 1, N codes.

FIGURE 3. Code Type Allowance Versus VCO Frequency Range

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Strobe Bit Strobe Window Strobe

43210Word M T

01111 −15 −0.270 x τ 01110 −14 −0.252 x τ 01101 −13 −0.234 x τ 01100 −12 −0.216 x τ 01011 −11 −0.198 x τ 01010 −10 −0.180 x τ 01001 −9 −0.162 x τ 01000 −8 −0.144 x τ 00111 −7 −0.126 x τ 00110 −6 −0.108 x τ 00101 −5 −0.090 x τ 00100 −4 −0.072 x τ 00011 −3 −0.054 x τ 00010 −2 −0.036 x τ 00001 −1 −0.018 x τ 00000 0 0 10000 0 0 10001 1 0.018 x τ 10010 2 0.036 x τ 10011 3 0.054 x τ 10100 4 0.072 x τ 10101 5 0.090 x τ 10110 6 0.108 x τ 10111 7 0.126 x τ 11000 8 0.144 x τ 11001 9 0.162 x τ 11010 10 0.180 x τ 11011 11 0.198 x τ 11100 12 0.216 x τ 11101 13 0.234 x τ 11110 14 0.252 x τ 11111 15 0.270 x τ

FIGURE 4. Window Strobe Truth Table

Customers who employ the DP8459 in a system without a MICROWIRE

™

(or functionally equivalent) bus conﬁguration and who wish to ﬁx the synchronization window in the nominal position while deselecting the test mode need only load all-zero’s into the Control Register following power-up; this may be easily achieved in some system conﬁgurations (requiring no additional hardware) by tying CRE to RG, tying CRC to ERD and tying CRD to ground, providing the necessary waveforms are present for register loading prior to the ﬁrst read operation.

The DP8459 provides two pins for PLL ﬁltering purposes, CHARGE PUMP OUTPUT (CPO) and VCO INPUT (VCOI). These provide the Customer with great ﬂexibility in ﬂiter design, permitting high-order ﬁlter functions for optimization of PLL lock characteristics and bit jitter rejection. For basic 3rd order applications, CPO and VCOI may be tied together

(Typical)

VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO VCO

(single-node) with a simple lead-lag, C||(R+C) ﬁlter tied between these pins and ground. More esoteric ﬁlter designs may be implemented if the pins are electrically separated and a two-port ﬁlter network is established between CPO, VCOI, and ground. National Semiconductor supplies initial PLL ﬁlter recommendations for the single-node conﬁguration within this data sheet with the qualifying statement that they are very general in nature, intended primarily for production testing of static window margin, and are NOT optimized for any particular disk system. For optimum performance, the Customer should pursue a ﬁlter design which is individualized and tailored to the requirements of the speciﬁc system involved. This is particularly true for the two-port ﬁltering technique. See

Figure 5

for initial single-node ﬁlter design

recommendations.

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Code MFM MFM MFM 2,7 2,7 Units

Rate 0.500 2 5 10 20 Mbit/sec

VCO freq. 1 4 10 20 40 MHz Sync bytes 12 12 12 12 12 bytes pulses/byte 8 8 8 4 4 ﬂux tran’s sync length 192 48 19.2 9.6 4.8 µs

sync freq 0.500 2 5 5 10 MHz

sync

max/Nmin

min

max

sync

C1 0.5 0.12 0.05 0.018 8200 pF µF

2 2 2 4 4 none

4/2 4/2 4/2 8/3 8/3 none

0.5 0.5 0.5 0.5 0.5 none

0.7 0.7 0.7 0.8 0.8 none

0.7 0.7 0.7 0.7 0.7 none 35 144 353 606 1230 Krad/sec

R1 82 82 82 150 150 Ω C2 0.01 µF 2700 1000 510 200 pF

Note 1: Preamble (sync) natural frequency chosen yields phase error ≤ 0.01 radians at sync ﬁeld end, given a 1%frequency step at READ GATE assertion. Rnom =

Rboost=2.4k for all above loop ﬁlter selections. HGD is tied to RG, FLC is tied to PD and CPO is tied to VCOI as well as to the loop ﬂter components.

Note 2: Component values are listed for purposes of window speciﬁcation testing and correlation. These values do not necessarily yield optimum performance in actual system applications. PLL dynamics and code characteristics are presented for Customer information and convenience only. See Section 3.1.

Unless otherwise noted.

FIGURE 5. Test Conditions and Component Values for Static Window Truncation Testing

The DP8459 VCO is constrained at all times to operate within a frequency swing of approximately

50%of the frequency present at the REFERENCE CLOCK input. Internal frequency detector/comparator circuitry senses when the VCO overruns the 50%boundary and forces the charge pump to move the VCO back toward the REFERENCE CLOCK frequency until the 50%constraint is again satisﬁed—thus preventing VCO runaway in the event of loss of lock or during extended periods where ENCODED READ DATAis not present.Additionally, this technique causes the ﬁlter node voltage to behave as if a voltage clamp were present at the Charge Pump Output, preventing the control voltage, in the event of loss of lock, from drifting outside of its operating range and inadvertently extending lock recovery time.

A special test mode feature has been incorporated into the DP8459 which allows a speciﬁc input pin to change function and act as an excitation source (substitute VCO) for clocking internal logic circuitry. When the last bit in the CONTROL REGISTER is taken to a logical ONE, the VCO is stopped, and the HGD input is redirected to act as a clock source for the VCO divider circuitry. Additionally, the Delay Line and Timing Extractor blocks are disabled when the Test Mode is entered, and thus the device will not function normally and should not

2.1 Functional Block Description PULSE GATE

The function of the Pulse Gate within the DP8459 is twofold. First, the block contains the ECL ﬂip-ﬂop which captures each arriving ENCODED READ DATAbit and transmits the bit to the SYNCHRONIZED DATA output. The very high switching speed of the bit-capture ECL ﬂip-ﬂop minimizes the portion of window margin loss caused by ﬂip-ﬂop metastability at window boundaries. Second, the Pulse Gate regulates the transmission of the VCO waveform into the Phase Comparator, allowing only one VCO pulse to pass with each arriving ENCODED READ DATA pulse. See

Figure 6

for a simpliﬁed logical representation of the Pulse Gate block. The one-to-one data/VCO pulse ratio produced by the Pulse Gate permits the multiple-harmonic nature of encoded data to be accommodated by the phase/frequency comparator. During the non-Read mode or during the portion of the Read mode within which the Customer has set the FREQUENCY LOCK CONTROL pin to a logical-zero (low), the Pulse Gate is inactive (bypassed) and the VCO frequency is divided as appropriate to match the incoming frequency source (ENCODED READ DATAor the REFERENCE CLOCK input).

be operated in this mode for purposes other than internal gate exercising. Further information regarding application of the Test Mode will be furnished at the Customer’s request: contact National Semiconductor Logic Marketing Group or Logic Applications Group.

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FIGURE 6. Simpliﬁed Diagram of Window Generation Circuitry

FIGURE 7. Capture of Nominally Positioned ENCODED READ DATA Pulse

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FIGURE 8. Capture of Early-Shifted ENCODED READ DATA Pulse

FIGURE 9. Capture of Late-Shifted ENCODED READ DATA Pulse

DELAY LINE

The DP8459 employs an internal silicon delay line to establish synchronization window alignment. The delay is nominally equivalent to one half of the period of the REFERENCE CLOCK waveform, and is variable in ﬁne increments via the

TL/F/9322-13

TL/F/9322-14

Control Register in order to achieve the window strobe function. The Timing Extractor circuitry derives realtive timing information soley from the REFERENCE CLOCK signal and regulates the magnitude of the delay within the Delay Line.

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