NSC DM54LS373J-883 Datasheet

TL/F/6431

DM54LS373/DM74LS373, DM54LS374/DM74LS374

TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

May 1992

DM54LS373/DM74LS373,
DM54LS374/DM74LS374
TRI-STATE

É

Octal D-Type Transparent

Latches and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relative­ly low-impedance loads. The high-impedance state and in­creased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter­face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. (Continued)

Features

Y

Choice of 8 latches or 8 D-type flip-flops in a single
package

Y

TRI-STATE bus-driving outputs

Y

Full parallel-access for loading

Y

Buffered control inputs

Y

P-N-P inputs reduce D-C loading on data lines

Connection Diagrams

Dual-In-Line Packages

’LS373

TL/F/6431– 1

Order Number

DM54LS373J,

DM54LS373W,
DM74LS373N or
DM74LS373WM

See NS Package Number

J20A, M20B, N20A or

W20A

’LS374

TL/F/6431– 2

Order Number

DM54LS374J,

DM54LS374W,

DM74LS374WM or

DM74LS374N

See NS Package Number

J20A, M20B, N20A or

W20A

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

General Description (Continued)

The eight latches of the DM54/74LS373 are transparent D­type latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.

The eight flip-flops of the DM54/74LS374 are edge-trig­gered D-type flip flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were
set up at the D inputs.

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines signifi­cantly.

The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be retained
or new data can be entered even while the outputs are off.

Function Tables

DM54/74LS373

Output Enable

D Output

Control G

LHHH
LHLL
LLXQ

0

HXXZ

DM54/74LS374

Output

Clock D Output

Control

L

u

HH

L

u

LL

LLXQ

0

HXXZ

H

e

High Level (Steady State), LeLow Level (Steady State), XeDon’t Care

u

e

Transition from low-to-high level, ZeHigh Impedance State

Q

0

e

The level of the output before steady-state input conditions were established.

Logic Diagrams

DM54/74LS373

Transparent Latches

TL/F/6431– 3

DM54/74LS374

Positive-Edge-Triggered Flip-Flops

TL/F/6431– 4

2

Absolute Maximum Ratings (See Note)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 7V

Storage Temperature Range

b

65§Ctoa150§C

Operating Free Air Temperature Range

DM54LS

b

55§Ctoa125§C

DM74LS 0

§

Ctoa70§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran­teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter

DM54LS373 DM74LS373

Units

Min Nom Max Min Nom Max

V

CC

Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

V

IH

High Level Input Votage 2 2 V

V

IL

Low Level Input Voltage 0.7 0.8 V

I

OH

High Level Output Current

b

1

b

2.6 mA

I

OL

Low Level Output Current 12 24 mA

t

W

Pulse Width Enable High 15 15

ns

(Note 2)

Enable Low 15 15

t

SU

Data Setup Time (Notes1&2) 5

v

5

v

ns

t

H

Data Hold Time (Notes1&2) 20

v

20

v

ns

T

A

Free Air Operating Temperature

b

55 125 0 70

§

C

Note 1: The symbol (v) indicates the falling edge of the clock pulse is used for reference.

Note 2: T

A

e

25§C and V

CC

e

5V.

’LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min

Typ

Max Units

(Note 1)

V

I

Input Clamp Voltage V

CC

e

Min, I

I

eb

18 mA

b

1.5 V

V

OH

High Level Output Voltage V

CC

e

Min DM54

2.4 3.4

I

OH

e

Max

V

V

IL

e

Max

DM74

2.4 3.1

V

IH

e

Min

V

OL

Low Level Output Voltage V

CC

e

Min DM54

0.25 0.4

I

OL

e

Max

V

IL

e

Max

DM74

0.35 0.5 V

V

IH

e

Min

I

OL

e

12 mA DM74

0.4

V

CC

e

Min

I

I

Input Current@Max V

CC

e

Max, V

I

e

7V

0.1 mA

Input Voltage

I

IH

High Level Input Current V

CC

e

Max, V

I

e

2.7V 20 mA

I

IL

Low Level Input Current V

CC

e

Max, V

I

e

0.4V

b

0.4 mA

I

OZH

Off-State Output Current V

CC

e

Max, V

O

e

2.7V

with High Level Output V

IH

e

Min, V

IL

e

Max

20 mA

Voltage Applied

I

OZL

Off-State Output Current V

CC

e

Max, V

O

e

0.4V

with Low Level Output V

IH

e

Min, V

IL

e

Max

b

20 mA

Voltage Applied

I

OS

Short Circuit V

CC

e

Max DM54

b

20

b

100

mA

Output Current (Note 2)

DM74

b

50

b

225

I

CC

Supply Current V

CC

e

Max, OCe4.5V,

24 40 mA

D

n

, EnableeGND

3