TL/F/9827
DM54LS299/DM74LS299 8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
June 1992
DM54LS299/DM74LS299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The ’LS299 is an 8-bit universal shift/storage register with
TRI-STATE
É
outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs
are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset
the register.
Features
Y
Common I/O for reduced pin count
Y
Four operation modes: shift left, shift right, load and
store
Y
Separate shift right serial input and shift left serial input
for easy cascading
Y
TRI-STATE outputs for bus oriented applications
Connection Diagram
Dual-In-Line Package
TL/F/9827– 1
Order Number DM54LS299E, DM54LS299J, DM54LS299W,
DM74LS299WM or DM74LS299N
See NS Package Number E20A, J20A, M20B, N20A or W20A
Pin Names Description
CP Clock Pulse Input (Active Rising Edge)
D
S0
Serial Data Input for Right Shift
D
S7
Serial Data Input for Left Shift
S0, S1 Mode Select Inputs
MR
Asynchronous Master Reset Input
(Active LOW)
OE1, OE2 TRI-STATE Output Enable Inputs
(Active LOW)
I/O0–I/O7 Parallel Data Inputs or TRI-STATE
Parallel Outputs
Q0–Q7 Serial Outputs
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.