TL/F/6638
DM54L95 4-Bit Parallel Access Shift Registers
June 1989
DM54L95 4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs, parallel output, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction Q
A
toward QD)
Shift left (the direction Q
D
toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock 2 when the
mode control is high by connecting the output of each flipflop to the parallel input of the previous flip-flop (Q
D
to input
C, etc.) and serial data is entered at input D. The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source.
Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensure that register contents are protected.
Features
Y
Typical maximum clock frequency 14 MHz
Y
Typical power dissipation mW
Connection Diagram
Dual-In-Line Package
TL/F/6638– 1
Order Number DM54L95J
or DM54L95W
See NS Package Number
J14A or W14B
Function Table
Inputs Outputs
Mode
Clocks
Serial
Parallel
Q
AQBQCQD
Control
2 (L) 1 (R) A B C D
HHXXXXXXQAOQBOQCOQ
DO
H
v
XXabcdabcd
H
v
XXQ
B
²
Q
C
²
Q
D
²
dQBnQCnQ
Dn
d
LLHXXXXXQ
AOQBOQCOQDO
LX
v
HXXXXHQAnQBnQ
Cn
LX
v
LXXXXLQAnQBnQ
Cn
u
LL XXXXXQAOQBnQCOQ
DO
v
LL XXXXXQAOQBOQCOQ
DO
v
LH X XXXXQAOQBOQCOQ
DO
u
HL X XXXXQAOQBOQCOQ
DO
u
HH X XXXXQAOQBOQCOQ
DO
²
Shifting left requires external connection of QBto A, QCto B, QDto C. Serial data is entered at input D.
H
e
High Level (Steady State), LeLow Level (Steady State), XeDon’t Care (Any input, including transitions).
v
e
Transition from high to low level.
u
e
Transition from low to high level.
a, b, c, d,
e
The level of steady state input at inputs A, B, C, or D, respectively.
Q
AO,QBO,QCO,QDO
e
The level of QA,QB,QC,orQD, respectively, before the indicated steady state input conditions were established.
Q
An,QBn,QCn,QDn
e
The level of QA,QB,QC,orQD, respectively, before the most recentvtransition of the clock.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.