NSC DAC1219LCJ-1, DAC1219LCJ Datasheet

TL/H/5691

DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter

December 1994

DAC1218/DAC1219
12-Bit Binary Multiplying D/A Converter

General Description

The DAC1218 and the DAC1219 are 12-bit binary, 4-quad­rant multiplying D to A converters. The linearity, differential
non-linearity and monotonicity specifications for these con­verters are all guaranteed over temperature. In addition,
these parameters are specified with standard zero and full­scale adjustment procedures as opposed to the impractical
best fit straight line guarantee.

This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder net­work. This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and al­lows the applied reference voltage to range from

b

25V to

25V, independent of the logic supply voltage.

CMOS current switches and drive circuitry are used to
achieve low power consumption (20 mW typical) and mini­mize output leakage current errors (10 nA maximum).
Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range.

The DAC1218 and DAC1219 are direct replacements for
the AD7541 series, AD7521 series, and AD7531 series with
a significant improvement in the linearity specification. In
applications where direct interface of the D to A converter to

a microprocessor bus is desirable, the DAC1208 and
DAC1230 series eliminate the need for additional interface
logic.

Features

Y

Linearity specified with zero and full-scale adjust only

Y

Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)

Y

Works withg10V referenceÐfull 4-quadrant
multiplication

Y

All parts guaranteed 12-bit monotonic

Key Specifications

Y

Current Settling Time 1 ms

Y

Resolution 12 Bits

Y

Linearity (Guaranteed 12 Bits (DAC1218)
over temperature) 11 Bits (DAC1219)

Y

Gain Tempco 1.5 ppm/§C

Y

Low Power Dissipation 20 mW

Y

Single Power Supply 5 VDCto 15 V

DC

Typical Application

TL/H/5691– 1

V

OUT

eb

V

REF

#

A1

2

a

A2

4

a

A3

8

a

...

A12

4096

J

where: ANe1 if digital input is high

AN

e

0 if digital input is low

Connection Diagram

Dual-In-Line Package

TL/H/5691– 15

Top View

Ordering Information

Temperature Range 0§Ctoa70§C

b

40§Ctoa85§C Package Outline

Non 0.012% DAC1218LCJ-1 DAC1218LCJ J18A Cerdip

Linearity

0.024% DAC1219LCJ J18A Cerdip

BI-FETTMis a trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

)17V

DC

Voltage at Any Digital Input VCCto GND

Voltage at V

REF

Input

g

25V

Storage Temperature Range

b

65§Ctoa150§C

Package Dissipation at T

A

e

25§C (Note 3) 500 mW

DC Voltage Applied to I

OUT1

or I

OUT2

b

100 mV to V

CC

(Note 4)

Lead Temp. (Soldering, 10 seconds) 300§C

ESD Susceptibility (Note 11) 800V

Operating Conditions

Temperature Range T

MIN

s

T

A

s

T

MAX

DAC1218LCJ, DAC1219LCJ

b

40§CsT

A

s

a

85§C

DAC1218LCJ-1 0

§

CsT

A

s

70§C

Range of V

CC

5VDCto 16 V

DC

Voltage at Any Digital Input VCCto GND

Electrical Characteristics

V

REF

e

10.000 VDC,V

CC

e

11.4 VDCto 15.75 VDCunless otherwise noted. Boldface limits apply from T

MIN

to T

MAX

(see

Note 9); all other limits T

A

e

T

J

e

25§C.

Typ

Tested Design

Parameter Conditions Notes

(Note 10)

Limit Limit Units

(Note 11) (Note 12)

Resolution 12 12 12 Bits

Linearity Error Zero and Full-Scale 4, 5, 9
(End Point Linearity) Adjusted

DAC1218

g

0.018g0.018 %ofFSR

DAC1219

g

0.024g0.024 %ofFSR

Differential Non-Linearity Zero and Full-Scale 4, 5, 9

Adjusted
DAC1218

g

0.018g0.018 %ofFSR

DAC1219

g

0.024g0.024 %ofFSR

Monotonicity 4 12 12 12 Bits

Gain Error (Min) Using Internal RFb,5

b

0.1 0.0 % of FSR

Gain Error (Max)

V

REF

e

g

10V,g1V

5

b

0.1

b

0.2 % of FSR

Gain Error Tempco 5

g

1.3

g

6.0 ppm of FS/§C

Power Supply Rejection All Digital Inputs High 5

g

3.0

g

30 ppm of FSR/V

Reference Input Resistance (Min) 9 15 10 10 kX

(Max) 9 15 20 20 kX

Output Feedthrough Error V

REF

e

120 Vp-p, fe100 kHz 6 3.0 mVp-p

All Data Inputs Low

Output Capacitance All Data Inputs I

OUT1

200 pF

High I

OUT2

70 pF

All Data Inputs I

OUT1

70 pF

Low I

OUT2

200 pF

Supply Current Drain 9 2.0 2.5 mA

Output Leakage Current 7, 9

I

OUT1

All Data Inputs Low 10 10 nA

I

OUT2

All Data Inputs High 10 10 nA

Digital Input Threshold Low Threshold 9 0.8 0.8 V

DC

High Threshold 2.2 2.2 V

DC

Digital Input Currents Digital Inputsk0.8V 9

b

200

b

200 mA

DC

Digital Inputsl2.2V 10 10 mA

DC

tsCurrent Settling Time R

L

e

100X, Output Settled
to 0.01%, All Digital Inputs 1 ms
Switched Simultaneously

2

Electrical Characteristics Notes

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify

the power dissipation) removes concern for heat sinking.

Note 4: Both I

OUT1

and I

OUT2

must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately V

OS

d

V

REF

. For

example, if V

REF

e

10Vthena1mVoffset, VOS,onI

OUT1

or I

OUT2

will introduce an additional 0.01% linearity error.

Note 5: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular
V

REF

value to indicate the true performance of the part. The Linearity Error specification of the DAC1218 is 0.012% of FSR. This guarantees that after performing a

zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012%

c

V

REF

of a straight line which passes through zero and full­scale. The unit ppm of FSR (parts per million of full-scale range) and ppm of FS (parts per million of full-scale) are used for convenience to define specs of very
small percentage values, typical of higher accuracy converters. 1 ppm of FSR

e

V

REF

/106is the conversion factor to provide an actual output voltage quantity. For

example, the gain error tempco spec of

g

6 ppm of FS/§C represents a worst-case full-scale gain error change with temperature fromb40§Ctoa85§Cof

g

(6)(V

REF

/106)(125§C) org0.75 (10

b

3

)V

REF

which isg0.075% of V

REF

.

Note 6: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV.

Note 7: A 10 nA leakage current with R

Fb

e

20k and V

REF

e

10V corresponds to a zero error of (10c10

b

9

c

20c103)c100% 10V or 0.002% of FS.

Note 8: Human body model, 100 pF discharged through 1.5 kX resistor.

Note 9: Tested limit for

b

1 suffix parts applies only at 25§C.

Note 10: Typicals are at 25

§

C and represent the most likely parametric norm.

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Typical Performance Characteristics

Digital Input Threshold
vs V

CC

Digital Input Threshold
vs Temperature

Gain and Linearity Error
Variation vs Temperature

Gain and Linearity Error
Variation vs Supply Voltage

TL/H/5691– 2

3

Definition of Package Pinouts

(A1–A12): Digital Inputs. A12 is the least significant digital

input (LSB) and A1 is the most significant digital input
(MSB).

I

OUT1

: DAC Current Output 1. I

OUT1

is a maximum for a

digital input of all 1s, and is zero for a digital input of all 0s.

I

OUT2

: DAC Current Output 2. I

OUT2

is a constant minus

I

OUT1

,orI

OUT1

a

I

OUT2

e

constant (for a fixed reference

voltage).

R

Fb

: Feedback Resistor. The feedback resistor is provided

on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature.

V

REF

: Reference Voltage Input. This input connects to an

external precision voltage source to the internal R-2R lad­der. V

REF

can be selected over the range of 10V tob10V.
This is also the analog voltage input for a 4-quadrant multi­plying DAC application.

V

CC

: Digital Supply Voltage. This is the power supply pin for

the part. V

CC

can be from 5 VDCto 15 VDC. Operation is

optimum for 15 V

DC

.

GND: Ground. This is the ground for the circuit.

Definition of Terms

Resolution: Resolution is defined as the reciprocal of the

number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC1218 has 2

12

or 4096 steps and therefore

has 12-bit resolution.

Linearity Error: Linearity error in the maximum deviation
from a

straight line passing through the endpoints of the

DAC transfer characteristic.

It is measured after adjusting
for zero and full scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.

National’s linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, which is almost impossible for the user to
determine. The end point test uses a standard zero FS ad­justment procedure and is a much more stringent test for
DAC linearity.

Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.

Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is the time required from a code transition until the DAC
output reaches within

g

1/2 LSB of the final output value.

Full-scale Error: Full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1218 full-scale is V

REF

b

1 LSB. For

V

REF

e

10V and unipolar operation, V

FULL-

SCALE

e

10.0000Vb2.44 mVe9.9976V. Full-scale error is

adjustable to zero.

Differential Non-Linearity: The difference between any
two consecutive codes in the transfer curve from the theo­retical 1 LSB is differential non-linearity.

Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input in­creasing digital input codes will produce an increasing ana­log output.

a) End point test after zero and FS adjust b) Shifting FS adjust to pass best straight line test

TL/H/5691– 3

4