NSC 5962-9459101VYA, 5962-9459101VXA, 5962-9459101MYA, 5962-9459101MXA, 100341MW8 Datasheet
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100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n
) and outputs (Qn) for parallel op-
eration, and with serial inputs (D
n
) and steering logic for bidirectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this rising clock edge.
The circuit operating mode is determined by the Select inputs S
0
and S1, which are internally decoded to select either
“parallel entry”, “hold”, “shift left” or “shift right” as described
in the Truth Table.All inputs have 50 kΩ pull-down resistors.
Features
n 35%power reduction of the 100141
n 2000V ESD protection
n Pin/function compatible with 100141
n Voltage compensated operating range=−4.2V to −5.7V
n Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
Pin Names Description
CP Clock Input
S
0,S1
Select Inputs
D
0,D7
Serial Inputs
P
0–P7
Parallel Inputs
Q
0–Q7
Data Outputs
DS100315-1
August 1998
100341 Low Power 8-Bit Shift Register
© 1998 National Semiconductor Corporation DS100315 www.national.com
Connection Diagrams
24-Pin DIP
DS100315-2
24-Pin Quad Cerpak
DS100315-3
www.national.com 2
Logic Diagram
Truth Table
Function Inputs Outputs
D
7
D
0
S
1
S
0
CP Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Load Register X X L L
N
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
Shift Left X L L H
N
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
L
Shift Left X H L H
N
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
H
Shift Right L X H L
N
LQ7Q6Q5Q4Q3Q2Q
1
Shift Right H X H L
N
HQ7Q6Q5Q4Q3Q2Q
1
Hold X X H H X
Hold XXXXH NoChange
Hold XXXXL
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
N
=
LOW-to-HIGH Transition
DS100315-5
3 www.national.com
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