100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both Enable (E
n
) inputs are LOW, the data that appears at an output
is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D
0
or
D
1
, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
0
or D1to an output.
The Select inputs can be tied together for applications requiring only that data be steered from either D
0
or D1.A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩ pulldown resistors.
Features
n Greater than 40%power reduction of the 100155
n 2000V ESD protection
n Pin/function compatible with 100155
n Voltage compensated operating range=−4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names Description
E
1,E2
Enable Inputs (Active LOW)
S
0,S1
Select Inputs
MR Master Reset
D
na–Dnd
Data Inputs
Q
a–Qd
Data Outputs
Q
a–Qd
Complementary Data Outputs
Connection Diagrams
DS100294-1
24-Pin DIP
DS100294-2
24-Pin Quad Cerpak
DS100294-3
August 1998
100355 Low Power Quad Multiplexer/Latch
© 1998 National Semiconductor Corporation DS100294 www.national.com
Operating Mode Table
Controls Outputs
E
1E2S1S0
Q
n
H X X X Latched (Note 1)
X H X X Latched (Note 1)
LLLL D
0x
LLHL D0x+D
1x
LLLH L
LLHH D
1x
H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
Note 1: Stores data present before E went HIGH
Truth Table
Inputs Outputs
MR E
1E2S1S0D1xD0xQx
Q
x
HXXXXXX H L
LLLHHHX L H
LLLHHLXH L
LLLLLXH L H
LLLLLXL H L
LLLLHXX H L
LLLHLHX L H
LLLHLXH L H
LLLHLL L H L
L H X X X X X Latched (Note 1)
L X H X X X X Latched (Note 1)
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