NSC 5962-8762701SA, 5962-8762701RA, 5962-87627012A Datasheet
54FCT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’FCT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loadsallflip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’FCT273 for master reset version
n See ’FCT373 for transparent latch version
n See ’FCT374 for TRI-STATE
®
version
n TTL input and output level compatible
n CMOS power consumption
n Output sink capability of 32 mA, source capability of
12 mA
n Standard Microcircuit Drawing (SMD) 5962-8762701
Ordering Code
Military Package Package Description
Number
54FCT377DMQB J20A 20-Lead Ceramic Dual-In-Line
54FCT377FMQB W20A 20-Lead Cerpack
54FCT377LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names
Description
D
0–D7
Data Inputs
CE
Clock Enable (Active LOW)
CP Clock Pulse Input
Q
0–Q7
Data Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
Pin Assignment for
DIP and Cerpack
DS100952-1
Pin Assignment for LCC
DS100952-11
October 1999
54FCT377 Octal D-Type Flip-Flop with Clock Enable
© 1999 National Semiconductor Corporation DS100952 www.national.com
Truth Table
Mode Select-Function Table
Operating Mode Inputs Output
CP CE
D
n
Q
n
Load “1” I h H
Load “0” I I L
Hold h X No Change
(Do Nothing) X H X No Change
H=HIGH Voltage Level
h=HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L=LOW Voltage Level
I=LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X=Immaterial
=
LOW-to-HIGH Clock Transition
Logic Diagram
DS100952-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
54FCT377
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to +4.75V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) Twice the rated I
OL
(mA)
DC Latchup Source Current −500 mA
(Across Comm Operating Range)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
DC Electrical Characteristics
Symbol Parameter FCT377 Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
=
−18 mA
V
OH
Output HIGH Voltage 54FCT 4.3 V Min I
OH
=
−300 uA
54FCT 2.4 I
OH
=
−12 mA
V
OL
Output LOW Voltage 54FCT 0.2 V Min I
OL
=
300 uA
54FCT 0.5 I
OL
= 32mA
I
IH
Input HIGH Current 5 µA Max V
IN
=
V
CC
I
IL
Input LOW Current −5 µA Max V
IN
=
0.5V
I
OS
Output Short-Circuit Current −60 mA Max V
OUT
=
0.0V
I
CCQ
Quiescent Power
Supply Current
1.5 mA Max V
I
=
0.2V or V
I
= 5.3V, VCC= 5.5V
∆I
CC
Maximum ICC/Input V
I
=
V
CC
− 2.1V
2.0 mA Max Data Input V
I
=
V
CC
− 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
0.4 mA/ Max Outputs Open
MHz One bit Toggling, 50%Duty Cycle
I
CC
Total Power Supply
Current
6.0 mA Max VCC= 5.5V, Outputs Open, fCP=
10MHz, 50%Duty Cycle, One bit
Toggling at f
I
= 5 MHz, 50%Duty
Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
54FCT377
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