NOVATEK NT7703H-BDT, NT7703H-TAB18 Datasheet

160 Output LCD Segment/Common Driver

Features

(Segment mode)

Shift Clock frequency:

!

14 MHz (Max.) (VDD = 5V ± 10%)
8 MHz (Max.) (VDD = 2.5V - 4.5V)

Adopts a data bus system

!

4-bit / 8-bit parallel input modes are selectable with a

!

mode (MD) pin

Automatic transfer function with an enable signal

!

Automatic coun ting funct ion when in “c hip sele ct” mode,

!

which causes the internal clock to be stopped by
automatically counting 160 bits of input data

(Common mode)

Shift clock frequency:

!

4.0MHz (Max.)

Built-in 160-bits bidirectional shift register (divisible into

!

80-bits x 2)

General Description

The NT7703 is a 160-bit output segment/common driver LSI
suitable for driving the large scale dot matrix LCD panels
used by PDA's, personal computers and work stations for
example. Through the use of COG technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7703 is good as both a segment driver
and a common driver, and a low power consuming, high-

Available in a single mode (160-bits shift register) or in a

!

NT7703

dual mode (80-bits shift register x 2)

1. Y1 → Y160 Single mode

2. Y160 → Y1 Single mode

3. Y1 → Y80, Y81 → Y160 Dual mode

4. Y160 → Y81, Y80 → Y1 Dual mode
The above 4 shift directions are pin-selectable

(Both segment mode and common mode)

Supply voltage for LCD drive: 15.0 to 30.0V

!

Number of LCD driver outputs: 160

!

Low output impedance

!

Low power consumption

!

Supply voltage for the logic system: +2.5 to +5.5V

!

COMS process

!

Package: Gold bump die / 186 Pin TCP (Tape Carrier

!

Package)

Not designed or rated as radiation hardened

!

precision LCD panel display can be assembled using the
NT7703. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In com mon mo de, the data input/output pin s
are bi-directional and the four data shift directions are pin­selectable.

Pin Configuration

D

D

D

D

D

U

U

U

U

Y

M

M

M

M

1

M

M

M

M

6

Y

Y

Y

Y

0

Y

Y

Y

Y

Y

1

1

1

1

1

5

5

5

5

5

5

6

7

8

9

184 183 182 181186

Y

Y

Y

Y

Y

8

8

3

2

Y

8

8

7

7

1

0

9

8

105

106107108109 104 28

Y6Y5Y4Y3Y2Y

29303132185

D

D

D

U

U

U

U

M

M

M

M

M

M

M

M

Y

Y

Y

Y

1

27

NT7703

1

234567891011121314151617181920212223242526

V

V

V

V

L

V

S

E

/

D

/

I

R

D

C

O
2

D0D1D2D3D4D5D6D7X

0

1

4

S

L

2

3

S

L

L

/
V
5
L

LPE

FRMDV

V

V

D

C

I

K

S
P
O
F
F

V

I

4

1

0

S

O

3

2

R

S

1

R

R

/
V
5
R

1V1.0

Pad Configuration

x

x

273

288

ALK_L

x

1

Block Diagram

NT7703

x

Dummy Pad

NT7703

145272

x

x

ALK_R

x

128

144

129

DISPOFF

EIO

EIO

XCK

L/R

MD

S/C

V

0R

FR

1

2

LP

Level

Shifter

Active

Control

Control

Logic

V

5R

12R

43R

V

V

Y1 Y2 Y159 Y160

V

5R

160 Bits 4 Level Driver

/160

160 Bits Level Shifter

/160

160 Bits Line Latch/Shift Register

8Bits x 2
Data
Latch

V

5L

V

43L

V

12L

V

0L

/16/16 /16 /16 /16 /16 /16 /16 /16 /16

Data Latch Control

/8

SP Conversion & Data Control

(4 to 8 or 8 to 8)

VSSV

V

DI0DI1DI2DI3DI4DI5DI6DI

7

DD

SS

2

Pad Description

Pad No. Designation I/O Description

NT7703

1 - 7 V

8 - 12 V
13 - 17 V
18 - 22 V
23 - 39 V

0L

12L

43L

5L

SS

P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver

P Ground (0V), these two pads must be connected to each other
40 - 41 L/R I Display data shift direction selection
42 - 57 V

DD

P Power supply for the logic system (+2.5 to + 5.5V)
58 - 59 S/C I Segment mode / common mode selection
60 - 61 EIO

2

I/O Input / output for chip select or data of shift register

62, 63 - 74, 75 D0 - D6 I Display data input for segment mode

76 - 77 D7 I Display data input for Segment mode / Dual mode data input
78 - 79 XCK I Display data shift clock input for segment mode
80 - 81

DISPOFF

I Control input for deselect output level
82 - 83 LP I Latch pulse input / shift clock input for the shift register
84 - 85 EIO

1

I/O Input / output for chip select or data of the shift register
86 - 87 FR I AC-converting signal input for LCD driver waveform
88 - 89 MD I Mode selection input

90 - 106 V
107 - 111 V
112 - 116 V
117 - 121 V
122 - 128 V

SS

5R

43R

12R

0R

P Ground (0V), these two pads must be connected to each other
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver

129 - 288 Y1 - Y160 O LCD driver output

3

Input / Output Circuits

NT7703

V

DD

I

Input Signal

Applicable Pins
L/R, S/C, D0 - D6,
, LP, FR, MD

V

SS

Input Circuit (1)

V

DD

I

Control Signal

V

SS

SS

V

DISPOFF

Input Signal

Applicable Pins
D7, XCK

Input Circuit (2)

4

I/O

NT7703

V

DD

Input Signal

Control Signal

V

SS

V

V

DD

SS

V

SS

Output Signal

Control Signal

Applicable Pins
EIO1, EIO2

Control Signal 1

O

Control Signal 3

Input / Output Circuit

V0 V12

V43

SS

LCD Driver Output circuit

Control Signal 2

Control Signal 4

Applicable Pins
Y1 to Y160

V5V

5

Pad Description

Segment mode

Symbol Function

V

DD

V

SS

VOR, V

V

, V

12R

V

, V

43R

V5R, V

D0 - D

XCK

LP

L/R

DISPOFF

FR

MD

Logic system power supply pin connects from +2.5 to +5.5V
Ground pin connects to 0V
Power supply pin for LCD driver voltage bias

OL

Normally, the bias voltage used is set by a resistor divider

"

12L

Ensure that the voltages are set such that V

"

43L

To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y

"

5L

externally connect ViR and V

(I = 0, 12, 43)

iL

SS

< V

V

≤

5

Input pin for display data

In 4-bit parallel input mode, input data into the 4 pins D

"

7

In 8-bit parallel input mode, input data into the 8 pins D0 - D

"

Clock input pin for taking display data

Data is read on the falling edge of the clock pulse

"

Latch pulse input pin for display data

Data is latched on the falling edge of the clock pulse

"

Direction selection pin for reading display data

When set to V

"

When set to V

"

level "L", data is read sequentially from Y160 to Y1

SS

level "H", data is read sequentially from Y1 to Y160

DD

Control input pin for output deselect level

The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the

"

LCD driver circuit

When set to V

"

When DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch

"

are read regardless of the condition of
outputs the deselect level (V

level “L”, the LCD driver output pins (Y1 - Yl60) are set to level V

SS

DISPOFF. When the DISPOFF function is canceled, the driver

or V43), then outputs the contents of the date latch onto the next falling edge

12

of the LP
At that time, if the

DISPOFF removal time can not keep in regulation with what is shown on the AC

characteristics, then it can not output the reading data correctly

AC signal input for LCD driving waveform

The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD

"

driver circuit

It normally inputs a frame inversion signal

"

The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal

Mode selection pin

When set to VSS level “L”, 4-bit parallel input mode is set

"

When set to V

"

level “H", 8-bit parallel input mode is set

DD

< V

43

0 - D3

< V

12

0

. Connect D4 - D7 to VSS or V

7

NT7703

160,

DD

5

6

Segment mode continued

Symbol Function

Segment mode/common mode sele ctio n pin

S/C

When set to V

"

When set to V

"

level "H", segment mode is set

DD

level "L", common mode is set

SS

Input/output pin for chip selection

level “L”, EIO1 is set for output, and EIO2 is set for input

SS

XCK is “H” and then after 160-bits of data have been read, it is

EIO1, EIO

When L/R input is at V

"

When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output

"

2

During output, it is set to “H” when LP*

"

set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”

During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of

"

data have been read, the chip is deselected

Y1 - Y

160

LCD driver output pins
These correspond direct ly to ea ch bit of the data latch, o ne level (V

Common mode

Symbol Function

NT7703

, V12, V43, or V5) is selected and output

0

V
V

V0R, V

V

12R

V

43R

V5R, V

EIO

EIO

DD

SS

, V
, V

LP

L/R

1

2

0L
12L
43L
5L

Logic system power supply pin connects from +2.5 to +5.5V
Ground pin connects to 0V
Power supply pin for LCD driver voltage bias.

Normally, the bias voltage used is set by a resistor divider

"

< V

Ensure that the voltages are set such that V

"

To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and

"

Y

externally connect ViR and V

160,

(I = 0, 12, 43)

iL

SS

≤

V

5 <V43

12

< V

0

Bi-directional shift register shift data input/output pin

Is an Output pin when L/R is at V

"

When EIO

"

When EIO1 is used as an output pin, it won’t be pulled-down

"

is used as an input pin, it will be pulled-down

1

level “L” and is an input pin when L/R is at VDD level “H”

SS

Bi-directional shift register shift data input/output pin

Is an Input pin when L/R is at V

"

When EIO2 is used as an input pin, it will be pulled-down

"

When EIO

"

is used as an output pin, it won’t be pulled-down

2

level “L” and is an output pin when L/R is at VDD level “H”

SS

Bi-directional shift register shift clock pulse input pin

Data is shifted on the falling edge of the clock pulse

"

Bi-directional shift register shift direction selection pin

Data is shifted from Y

"

it is to V

level “H”

DD

to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y

160

when set

160

7

Common mode continued

Symbol Function

Control input pin for output deselect level

The input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls

"

the LCD driver circuit

level “L”, the LCD driver output pins (Y1 - Y

SS

DISPOFF

When set to V

"

While set to “L”, the contents of the shift resister are reset and are not read ing data. When the DISPOFF

"

function is canceled, the driver outputs desele ct level (V
edge of the LP. At that time, if the

DISPOFF removal time can not keep regulation with what is shown on

the AC characteristics, then the shift data is not read correctly

AC signal input for LCD driving waveform

The input si gnal is lev el-shifted from th e logic v oltage lev el to the LCD driv er voltage level, an d controls t he

"

FR

LCD driver circuit

Normally, it inputs a frame inversion signal

"

The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR
signal

Mode selection pin

MD

When set to V

"

level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode

SS

operation is selected

Dual Mode data input pin

According to the data shift direction of the data shift register, data can be input starting from the 81st bit

D

7

S/C

D0 - D6

XCK

"

When the chip is used in Dual Mode, D
When the chip is used in Single Mode, D

will be pulled-down

7

won’t be pulled-down

7

Segment mode/common mode sele ctio n pin

When set to V

"

level “L”, co mmon mode is set

SS

Not used

Connect D

"

to VSS or VDD. Avoid floating

0-D6

Not used

XCK is pulled-down in common mode, so connect to V

"

LCD driver output pins

Y1 - Y

160

These correspond directly to each bit of the shift register, one level (V0, V

"

output

NT7703

) are set to level V

160

or V34), and the shift data is read on the falling

12

or leave open

SS

5

, or V5) is selected and

12, V43

8

Functional Description

1. Block description

1.1. Active Control

In segment mode, it controls the selection or deselection of
the chip. Following a LP signal input and after the select
signal is input, a se lect signal is generated internally unti l 160
bits of data have been read in. Once data input has been
completed, a select signal for the cascade connection is
output, and the ship is deselected.

In common mode, it controls the input/output data of the
bidirectional pins.

1.2. SP Conversion & Data Control

In segment mode, it keeps input data, which are 2 clocks of
XCK at 4-bit parallel mode in the latch circuit, or keeps input
data which are 1 clock of XCK at 8-bit parallel mode in the
latch circuit, after which they are put on the internal data bus
8 bits at a time.

1.3. Data Latch Control

In segment mode, it selec ts the state of the d ata latch, w hich
reads in the data bus signa ls. The sh ift dire ction i s contro lled
by the control logic and for every 16 bits of data read in, the
selection signal shifts one bit, based on the state of the
control circuit.

1.4. Data Latch

In segment mode, it latches the data onto the data bus. The
latched state of each LCD driver output pin is controlled by
the control logic and the data latch control. 160 bits of data
are read in 20 sets of 8 bits.

NT7703

1.5. Line Latch / Shift Register

In segment mode, it ensures that all 160 bits which have
been read into the data latch are simultaneously latched on
to the falling edge of the LP signal, and output to the level
shift block.

In common mode, shifts data from the data input pin on to
the falling edge of the LP signal.

1.6. Level Shifter

It ensures the logic voltage signal is level-shifted to the LCD
driver voltage level, and output to the driver block.

1.7. 4-Level Driver

It drives the LCD driver output pins from the line latch/shift
register data, selecting one of 4 levels (V

based on the S/C, FR and

1.8. Control Logic

It controls the operation of each block. In segment mode,
when an LP signal has been input, all blocks are reset and
the control logic waits f or the se lectio n sign al outpu t fro m the
active control block. Once the selection signal has been
output, operation of th e dat a l atc h and data transmission are
controlled, 160 bits of data are read in, and the chip is
deselected.

In common mode, it controls the direction of the data shift.

DISPOFF signals.

, V12, V43, V5)

0

9

NT7703

2. LCD Driver Output Voltage Level

The relationship between the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table
below:

2.1. Segment Mode

Here, VSS ≤ V5 < V

FR Latch Data

DISPOFF

LLH V

LHH V
HLH V
HHH V
XXL V

43

< V

12 <V0

, H: V

(+2.5 to +5.5V), L: V

DD

(0V), X: Don't care

SS

Driver Output Voltage Level (Y

43

5

12

0

5

1 - Y160

)

2.2. Common Mode

Here, VSS ≤ V5 < V

FR Latch Data

DISPOFF

LLH V

LHH V
HLH V
HHH V
XXL V

< V

43

< V0, H: V

12

(+2.5 to +5.5V), L: V

DD

(0V), X: Don't care

SS

Driver Output Voltage Level (Y

43

0

12

5

5

1 - Y160

)

Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular

voltage, which is assigned by specification for each power pin.
That time "Don't care" should be fixed to "H" or "L", avoiding floating.

10

3. Relationship between the Display Data and Driver Output Pins

3.1. Segment Mode:

(a) 4-bit Parallel Mode

MD L/R EIO1EIO

L L Output Input

L H Input Output

Data

2

Input

40clock 39clock 38clcok ~ 3clock 2clock 1clock

D
D
D
D
D
D
D
D

Y1 Y5 Y9

0

Y2 Y6 Y10

1

Y3 Y7 Y11

2

Y4 Y8 Y12

3

Y160 Y156 Y152

0

Y159 Y155 Y151

1

Y158 Y154 Y150

2

Y157 Y153 Y149

3

(b) 8-bit Parallel Mode

MD L/R EIO1EIO

H L Output Input

H H Input Output

Data

2

Input

20clock 19clock 18clcok ~ 3clock 2clock 1clock

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

Y1 Y9 Y17 ~ Y137 Y145 Y153

0

Y2 Y10 Y18 ~ Y138 Y146 Y154

1

Y3 Y11 Y19 ~ Y139 Y147 Y155

2

Y4 Y12 Y20 ~ Y140 Y148 Y156

3

Y5 Y13 Y21 ~ Y141 Y149 Y157

4

Y6 Y14 Y22 ~ Y142 Y150 Y158

5

Y7 Y15 Y23 ~ Y143 Y151 Y159

6

Y8 Y16 Y24 ~ Y144 Y152 Y160

7

Y160 Y152 Y144 ~ Y24 Y16 Y8

0

Y159 Y151 Y143 ~ Y23 Y15 Y7

1

Y158 Y150 Y142 ~ Y22 Y14 Y6

2

Y157 Y149 Y141 ~ Y21 Y13 Y5

3

Y156 Y148 Y140 ~ Y20 Y12 Y4

4

Y155 Y147 Y139 ~ Y19 Y11 Y3

5

Y154 Y146 Y138 ~ Y18 Y10 Y2

6

Y153 Y145 Y137 ~ Y17 Y9 Y1

7

Number of Clock

~
~
~
~
~
~
~
~

Number of Clock

NT7703

Y149 Y153 Y157
Y150 Y154 Y158
Y151 Y155 Y159
Y152 Y156 Y160
Y12 Y8 Y4
Y11 Y7 Y3
Y10 Y6 Y2
Y9 Y5 Y1

11

3.2. Common Mode

NT7703

MD L/R Data Transfer Direction EIO

L

(Single)

L (shift to left) Y160 to Y1 Output Input X

H (shift to right) Y1 to Y160 Input Output X

L (shift to left)

H

(Dual)

H (shift to right)

Here, L: VSS (0V), H: V

(+2.5V to +5.5V), X: Don't care

DD

Note: "Don't care" should be fixed to "H" or "L", avoiding floating.

Y160 to Y81

Y80 to Y1
Y1 to Y80

Y81 to Y160

EIO

1

2

D

7

Output Input Input

Input Output Input

12