NOVATEK NT7702H-BDT, NT7702H-TABF4 Datasheet
240 Output LCD Segment/Common Driver
Features
(Segment mode)
Shift Clock frequency:
!
20 MHz (Max.) (V
Adopts a data bus system
!
4-bit/8-bit parallel input modes are selectable with a
!
mode (MD) pin
Automatic transfer function with an enable signal
!
Automatic counting function when in the chip select
!
mode, causes the internal clock to be stopped by
automatically counting 240 bits of input data
(Common mode)
Shift clock frequency :
!
4.0 MHz (Max.)
Built-in 240-bits bidirectional shift register (divisible into
!
120-bits x 2)
General Description
The NT7702 is a 240-bit output segment/common driver LSI
suitable for driving large scale dot matrix LCD panels using
as PDA/personal computers/work stations. Through the use
of SST (Super Slim TCP) technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7702 is good as both a segment driver
and as a common driver, and a low power consuming, high-
= 5 V ± 10%)
DD
NT7702
Available in a single mode (240-bits shift register) or in a
!
dual mode(120-bits shift register x 2)
1. Y1 → Y240 Single mode
2. Y240 → Y1 Single mode
3. Y1 → Y120, Y121 → Y240 Dual mode
4. Y240 → Y121, Y120 → Y1 Dual mode
The above 4 shift directions are pin-selectable
(Both for segment mode and common mode)
Supply voltage for LCD driver: 15.0 to 30.0 V
!
Number of LCD driver outputs: 240
!
Low output impedance
!
Low power consumption
!
Supply voltage for the logic system: +2.5 to +5.5 V
!
COMS process
!
Package: 272pin TCP (Tape Carrier Package)
!
Not designed or rated as radiation hardened
!
precision LCD panel display can be assembled using the
NT7702. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In the common mode, the data input/output
pins are bi-directional and the four data shift directions are
pin-selectable.
Pin Configuration
D
U
M
M
Y
Y
Y
Y
2
2
2
3
3
4
8
9
0
271 270 269 268
Y
Y
Y
Y
Y
Y
Y
2
2
3
3
6
7
1
2
3
Y
1
1
1
1
1
2
2
2
1
1
2
1
0
9
8
151
152153154155 150 33
NT7702
1
234567891011121314151617181920212223242526272829303132
D
V
V
V
V
V
V
V
S
E
5
S
L
S
D0D1D2D3D4D5D6D7X
D
/
I
D
C
O
2
U
0
0
1
4
M
L
L
2
3
M
L
L
Y
D
LPE
FRL
C
K
MDNCV
I
I
/
S
P
O
F
F
S
O
R
S
1
1V1.0
D
U
Y5Y4Y3Y2Y
NCV
V
V
V
V
D
5
4
1
0
0
U
R
3
2
R
R
M
R
R
M
Y
M
M
1
Y
34353637272
Pad Configuration
NT7702
x x
xxx
283
296
x
1 44
Block Diagram
DISPOFF
EIO
EIO
XCK
L/R
59282
58
x
Dummy Pad
V
V
12R
0R
FR
Level
Shifter
NT7702
V
43R
5R
Y1 Y2 Y239 Y240V
240 Bits 4 Level Driver
/240
240 Bits Level Shifter
1
2
LP
Active
Control
Control
Logic
240 Bits Line Latch/Shift Register
8Bits2
Data
Latch
/240
x
Dummy Pad
ALK_RALK_L
45
x xx
x
5L
V
43L
V
12L
V
0L
V
/16/16 /16 /16 /16
x
Data Latch Control
/8
MD
S/C
SP Conversion & Data Control
(4 to 8 or 8 to 8)
D0D1D2D3D4D5D6D
V
7
VSSV
DD
SS
2
Pin Description
Pin No. Designation I/O Description
1, 2 V
3V
4V
5V
6V
7V
0L
12L
43L
5L
SS
DD
8 S/C I Segment mode /common mode selection
9EIO2I/O Input/output for chip select or data of the shift register
10 - 16 D0 - D6 I Display data input for segment mode
17 D7 I Display data input for Segment mode/ Dual mode data input
18 XCK I Display data shift clock input for segment mode
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Ground (0V), these two pads must be connected to each other
P Power supply for the logic system (+2.5 to +5.5V)
NT7702
19
DISPOFF
I Control input for deselect output level
20 LP I Latch pulse input/shift clock input for the shift register
21 EIO
1
I/O Input/output for chip select or data of the shift register
22 FR I AC-converting signal input for LCD driver waveform
23 L/R I Display data shift direction selection
24 MD I Mode selection input
25, 27 NC - No connected
26 V
28 V
29 V
30 V
31, 32 V
SS
5R
43R
12R
0R
P Ground (0V), these two pads must be connected to each other
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
33 - 272 Y1 - Y240 O LCD driver output
3
Pad Description
Pad No. Designation I/O Description
1, 2 V
3, 4 V
5, 6 V
5L
SS
DD
7, 8 S/C I Segment mode/common mode sele ctio n
9, 10 EIO
2
11, 12 - 23, 24 D0 - D6 I Display data input for segment mode
25, 26 D7 I Display data input for Segment mode/ Dual mode data input
27, 28 XCK I Display data shift clock input for segment mode
P Power supply for LCD driver
P Ground (0V), these two pads must be connected to each other
P Power supply for the logic system (+2.5 to +5.5V)
I/O Input/output for chip select or data of the shift register
NT7702
29, 30
DISPOFF
I Control input for deselect output level
31, 32 LP I Latch pulse input/shift clock input for the shift register
33, 34 EIO
1
I/O Input/output for chip select or data of the shift register
35, 36 FR I AC-converting signal input for LCD driver waveform
37, 38 L/R I Display data shift direction selection
39, 40 MD I Mode selection input
41, 42 V
43, 44 V
45, 46 V
47, 48 V
49, 50 V
SS
5R
43R
12R
0R
P Ground (0V), these two pads must be connected to each other
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
51 - 290 Y1 - Y240 O LCD driver output
291, 292 V
293, 294 V
295, 296 V
0L
12L
43L
P Power supply for LCD driver
P Power supply for LCD driver
P Power supply for LCD driver
4
Input / Output Circuits
NT7702
DD
V
I
Input Signal
Applicable Pins
L/R, S/C, D0 - D6,
, LP, FR, MD
SS
V
Input Circuit (1)
DD
V
I
Control Signal
SS
V
SS
V
Input Circuit (2)
DISPOFF
Input Signal
Applicable Pins
D7, XCK
5
I/O
NT7702
DD
V
Input Signal
Control Signal
SS
V
DD
V
SS
V
SS
V
Output Signal
Control Signal
Applicable Pins
EIO1, EIO2
Control Signal 1
O
Control Signal 3
Input / Output Circuit
V0 V12
V43
SS
LCD Driver Output circuit
Control Signal 2
Control Signal 4
Applicable Pins
Y1 to Y240
V5V
6
Pad Description
Segment mode
Symbol Function
V
DD
V
SS
VOR, V
V
, V
12R
V
, V
43R
V5R, V
D
0 - D7
XCK
LP
L/R
DISPOFF
FR
MD
Logic system power supply pin connects to +2.5 to +5.5V
Ground pin connects to 0V
Power supply pin for LCD driver voltage bias
OL
12L
43L
5L
Normally, the bias voltage used is set by a resistor divider
"
Ensure that the voltages are set such that V
"
To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and
"
externally connect ViR and V
Y
240,
(I = 0, 12, 43, 5)
iL
Input pin for display data
In 4-bit parallel input mode, input data into the 4 pins D
"
In 8-bit parallel input mode, input data into the 8 pins D0 - D
"
Clock input pin for taking display data
Data is read on the falling edge of the clock pulse
"
Latch pulse input pin for display data
Data is latched on the falling edge of the clock pulse
"
Direction selection pin for reading display data
When set to VSS level "L", data is read sequentially from Y240 to Y1
"
When set to VDD level "H", data is read sequentially from Y1 to Y240
"
Control input pin for output deselect level
The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD
"
driver circuit.
When set to V
"
Whi le DISPOFF set to “L”, the contents of the line latch are reset, but read the display data in the data
"
level “L”, the LCD driver output pins (Y1-Y240) are set to level V
SS
latch are read regardless of the condition of
driver outputs deselect level (V
edge of the LP. That time, if
or V43), then outputs the contents of the date latch onto the next falling
12
DISPOFF removal time can not keep regulation what is shown AC
characteristics, can not output the reading data correctly
AC signal input for LCD driving waveform
The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD
"
driver circuit.
Normally inputs a frame inversion signal
"
The LCD driver output pin’s output v oltage level can be set to the line latch o utput signal and the FR s ignal
Mode selection pin
When set to VSS level “L”, 8-bit parallel inp ut mode is set
"
When set to VDD level “H", 4-bit parallel input mode is set
"
V
≤
SS
DISPOFF. When the DISPOFF function is canceled, the
NT7702
< V
< V
5
43
0 - D3
< V
12
0
. Connect D4 - D7 to VSS or V
5
DD
7
Segment mode continued
Symbol Function
Segment mode/common mode sele ctio n pin
When set to VDD level "H", segment mode is set
S/C
"
When set to V
"
level "L", common mode is set
SS
Input/output pin for chip selection
level “L”, EIO1 is set for output, and EIO2 is set for input
SS
XCK is “H” and after 240-bits of data have been read, it is set to
EIO1, EIO
When L/R input is at V
"
When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output
"
2
During output, it is set to “H” while LP*
"
“L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”
During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 240-bits of data
"
have been read, the chip is deselected
LCD driver output pins
Y1 - Y
240
These correspond directly to each bit of the data latch, one level (V
output
Common mode
Symbol Function
NT7702
, V12, V43, or V5) is selected and
0
V
V
V0R, V
V
12R
V
43R
V5R, V
EIO
EIO
L/R
LP
DD
SS
, V
, V
1
2
0L
12L
43L
5L
Logic system power supply pin connects to +2.5 to +5.5V
Ground pin connects to 0V
Power supply pin for LCD driver voltage bias.
Normally, the bias voltage used is set by a resistor divider
"
< V
Ensure the voltages are set such that V
"
SS
V
≤
5 <V43
12
< V
0
To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and
externally connect ViR and V
Y
240,
(I = 0, 12, 43, 5)
iL
Bi-directional shift register shift data input/output pin
Is an output pin when L/R is at V
"
When EIO
"
When EIO
"
is used as an input pin, it will be pulled-down
1
is used as an output pin, it won’t be pulled-down
1
level “L” and an input pin when L/R is at VDD level “H”
SS
Bi-directional shift register shift data input/output pin
Is an input pin when L/R is at V
"
When EIO
"
When EIO
"
is used as input pin, it will be pulled-down
2
is used as output pin, it won’t be pulled-down
2
level “L” and an output pin when L/R is at VDD level “H”
SS
Bi-directional shift register shift clock pulse input pin
Data is shifted on the falling edge of the clock pulse
"
Bi-directional shift register shift direction selection pin
Data is shifted from Y
"
set to V
level “H”
DD
to Y1 when it is set to VSS level “L”, and data i s shifted fr om Y1 to Y
240
when it is
240
8
Common mode continued
Symbol Function
DISPOFF
Control input pin for output deselect level
The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls
"
the LCD driver circuit
When set to V
"
While set to “L”, the contents of the s hift resister are reset a nd are no t reading data. When the
"
level “L”, the LCD driver output pins (Y1-Y
SS
function is canceled, the driver o utputs des elect lev el (V
edge of the LP. That time, if
DISPOFF removal time can not keep regulation what is shown AC
characteristics, the shift data is not reading correctly
FR AC signal input for LCD driving waveform
The input signal is level-sh ifted from lo gic volta ge level t o the LCD driver v oltage lev el, and it control s the
"
LCD driver circuit
Normally, inputs a frame inversion signal
"
The LCD driver output pin’s outp ut voltage level can be set using the shift reg ister output si gnal and the FR
signal
MD Mode selection pin
When set to V
"
level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode
SS
operation is selected
D
7
Dual Mode data input pin
According to the data sh ift d irectio n of the d ata shi ft re gister, d ata can be in put starti ng from t he 1 21st bit
"
When the chip is used as Dual Mode, D
When the chip is used as Single Mode, D
will be pulled-down
7
won’t be pulled-down
7
S/C Segment mode/common mode selectio n pin
When set to V
"
level “L”, common mode is set
SS
D0 - D6 Not used
Connect D
"
to VSS or VDD. Avoiding floating
0-D6
XCK Not used
XCK is pull-down in common mode, so connect to V
"
Y1 - Y
240
LCD driver output pins
These correspond directly Correspond ing dir ectly to each bit of the s hift regi ster, one level (V
"
) is selected and output
or V
5
) are set to level V
240
or V43), and the shift data is re ad on the falling
12
or open
SS
5
NT7702
DISPOFF
, V
0
12, V43
,
9
Functional Description
1. Block description
1.1 Active Control
In the case of the segment mode, it controls the selection or
deselection of the chip. Following a LP signal input, and after
the select signal is input, a select signal is generated
internally until 240 bit s of dat a h av e bee n rea d i n. O nc e dat a
input has been completed, a select signal for cascade
connection is output, and the ship is deselect ed.
In the case of the common mode, it controls the in put/output
data of the bi-directional pins.
1.2. SP Conversion & Data Control
In the case of the segment mode, keep input data which are
2 clocks of XCK at 4-bit parallel mode into latch circuit, or
keep input data which are 1 clock of XCK at 8-bit parallel
mode into latch circuit, after that they are put on the internal
data bus 8 bits at a time.
1.3. Data Latch Control
In the case of the segment mode, selects the state of the
data latch, which reads in the data bus signals. The shift
direction is controlled by the control logic and for every 16
bits of data read in, the selection signal shifts one bit, based
on the state of the control circuit.
1.4. Data Latch
In the case of the segment mode, latches the data on the
data bus. The latched state of each LCD driver output pin is
controlled by the control logic and the data latch control 240
bits of data are read in 20 sets of 8 bits.
NT7702
1.5. Line Latch/Shift Register
In the case of the segment mode, all 240 bits which have
been read into the data latch, are simultaneously latched on
to the falling edge of the LP signal, and output to the level
shift block.
In the case of the common mode, it sh ifts data from the data
input pin on to the falling edge of the LP signal.
1.6. Level Shifter
The logic voltage signal is level-shifted to the LCD driver
voltage level, and output to the driver block.
1.7. 4-Level Driver
It drives the LCD driver output pins from the line latch/shift
register data, selecting one of 4 levels (V
based on the S/C, FR and
1.8. Control Logic
Controls the operation of each block. In case of segment
mode, when an LP signal h as been in put, all blo cks are re set
and the control logic w aits for the sele ction signal o utput from
the active control block. Once the selection signal has been
output, operation of th e dat a l atc h and data transmission are
controlled, 240 bits of data are read in, and the chip is
deselected.
In the case of the common mode, it controls the direction of
data shift.
DISPOFF signals.
, V12, V43, V5)
0
10
NT7702
2. LCD Driver Output Voltage Level
The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table
below:
2.1. Segment Mode
1 - Y240
)
Here, V
SS
FR Latch Data
LLH V
LHH V
HLH V
HHH V
XXL V
< V
< V
V
≤
5
43
< V0, H: V
12
(+2.5 to +5.5V), L: V
DD
DISPOFF
SS
Driver Output Voltage Level (Y
43
5
12
0
5
(0V), X: Don't care
2.2. Common Mode
Here, V
SS
FR Latch Data
DISPOFF
LLH V
LHH V
HLH V
HHH V
XXL V
< V
< V
V
≤
5
43
< V0, H: V
12
(+2.5 to +5.5V), L: V
DD
(0V), X: Don't care
SS
Driver Output Voltage Level (Y
43
0
12
5
5
1 - Y240
)
Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular
voltage which assigned by specification for each power pin.
That time "Don't care" should be fixed to "H" or "L", avoiding floating.
11
3. Relationship between the Display Data and Driver Output pins
3.1. Segment Mode:
(a) 4-bit Parallel Mode
NT7702
MD L/R EIO1EIO
H L Output Input
H H Input Output
(b) 8-bit Parallel Mode
MD L/R EIO1EIO
L L Output Input
L H Input Output
2
2
Data
Input
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
Data
Input
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Number of Clock
60clock 59clock 58clcok ~ 3clock 2clock 1clock
Y1 Y5 Y9
Y2 Y6 Y10
Y3 Y7 Y11
Y4 Y8 Y12
Y240 Y236 Y232
Y239 Y235 Y231
Y238 Y234 Y230
Y237 Y233 Y229
~
~
~
~
~
~
~
~
Y229 Y233 Y237
Y230 Y234 Y238
Y231 Y235 Y239
Y232 Y236 Y240
Y12 Y8 Y4
Y11 Y7 Y3
Y10 Y6 Y2
Y9 Y5 Y1
Number of Clock
30clock 29clock 28clcok ~ 3clock 2clock 1clock
Y1 Y9 Y17 ~ Y217 Y225 Y233
Y2 Y10 Y18 ~ Y218 Y226 Y234
Y3 Y11 Y19 ~ Y219 Y227 Y235
Y4 Y12 Y20 ~ Y220 Y228 Y236
Y5 Y13 Y21 ~ Y221 Y229 Y237
Y6 Y14 Y22 ~ Y222 Y230 Y238
Y7 Y15 Y23 ~ Y223 Y231 Y239
Y8 Y16 Y24 ~ Y224 Y232 Y240
Y240 Y232 Y224 ~ Y24 Y16 Y8
Y239 Y231 Y223 ~ Y23 Y15 Y7
Y238 Y230 Y222 ~ Y22 Y14 Y6
Y237 Y229 Y221 ~ Y21 Y13 Y5
Y236 Y228 Y220 ~ Y20 Y12 Y4
Y235 Y227 Y219 ~ Y19 Y11 Y3
Y234 Y226 Y218 ~ Y18 Y10 Y2
Y233 Y225 Y217 ~ Y17 Y9 Y1
12
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