NOVATEK NT68P62U, NT68P62 Datasheet

8-Bit Microcontroller for Monitor (32K OTP ROM Type)

Features

n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K bytes of OTP (one time programming) ROM
n 512 bytes of RAM
n One 8-bit base timer
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/vsync signals processor for separate &

composite signal, including hardware sync signals
polarity detection and freq. counters with 2 sets of
Hsync counting interval

n Hsync/Vsync polarity controlled output, 5 selectable

free run output signals and self-test patterns, auto­mute function, half freq. I/O function

n Two built-in I2C bus interfaces support VESA

DDC1/2B+

NT68P62-01

n Two layers of interrupt management

NMI interrupt sources

- INTE0 (External INT with selectable edge trigger)

- INTMUTE (Auto Mute Activated)

IRQ interrupt sources

- INTS0/1 (SCL Go-low INT)

- INTA0/1 (Slave Address Matched INT)

- INTTX0/1 (Shift Register INT)

- INTRX0/1 (Shift Register INT)

- INTNAK0/1 (No Acknowledge)

- INTSTOP0/1 (Stop Condition Occurred INT)

- INTE1 (External INT with Selectable Edge Trigger)

- INTV (VSYNC INT)

- INTMR (Base Timer INT)

- INTADC (AD Conversion Done INT)

n Hardware watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages

General Description

The NT68P62 is a new generation of monitor µC for auto­sync and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channel of 8-bit
PWM D/A converters, 4-channel A/D converters for keys
detection which can save I/O pins, one 8-bit pre-loadable
base timer, internal Hsync and Vsync signals processor,
and a watch-dog timer which prevents the system from

abnormal operation and two I2C bus interface. The user
can store EDID data in the 128 bytes of RAM for DDC1/2B,

so that user can reduce a dedicated EEPROM for EDID.
And Half frequency output function can save external one­shot circuit. All of these designs are committed to offer our
user saving component cost. The 42 pin S-DIP IC provides
two additional I/O pins – port40 & port41, Part number
NT68P62U represents the S-DIP IC. For future reference,
port40 & port42 is only available for the 42 pin S-DIP IC.

1 V2.2

Pin Configurations

NT68P62-01

40-Pin P-DIP

[PGM] DAC2

DAC1/ADC3

[OE] DAC0/ADC2

[VPP] RESET

GND

OSCO

OSCI

P15/INTE0

[CE] P14/PATTERN

[A11] P13/HALFI

[A10] P12/HALFO

[A9] P11/ADC1
[A8] P10/ADC0

P16/INTE1

[DB7] P27
[DB6] P26
[DB5] P25

[DB4] P24

[DB3] P23

1
2
3
4
5

V

DD

6
7
8
9
10
11
12
13
14
15
16 25
17
18
19
20

* [ ]: OTP Mode

40
39
38
37
36
35
34
33

NT68P62

32
31
30
29
28
27
26

24
23
22
21

VSYNCI/INTV [A14]
HSYNCI
DAC3 [MODE0]
DAC4/SCL1 [MODE1]
DAC5/SDA1 [MODE2]
DAC6 [RESET]
CREG
P07/HSYNCO [A7]
P06/VSYNCO [A6]
P05/DAC12 [A5]
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]

P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]

[PGM] DAC2

DAC1/ADC3

[OE] DAC0/ADC2

[VPP] RESET

P40

GND

OSCO

OSCI

P15/INTE0

[CE] P14/PATTERN

[A11] P13/HALFI

[A10] P12/HALFO

[A9] P11/ADC1
[A8] P10/ADC0

[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23

1
2
3
4

V

DD

5
6
7
8
9
10
11
12
13
14
15
16 27
17
18
19
20
21

* [ ]: OTP Mode

42
41
40
39
38
37
36

NT68P62U

35
34
33
32
31
30
29
28

26
25
24
23
22

VSYNCI/INTV [A14]
HSYNCI
DAC3 [MODE0]
DAC4/SCL1 [MODE1]
DAC5/SDA1 [MODE2]
P41
DAC6 [RESET]
CREG
P07/HSYNCO [A7]
P06/VSYNCO [A6]
P05/DAC12 [A5]
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]P16/INTE1
P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]

Block Diagram

V

DD

CREG

GND

OSCI

OSCO

INTE0/1

VSYNCI/INTV

HSYNCI

VSYNCO
HSYNCO

PATTERN

HALFI

HALFO

42-Pin S-DIP

Voltage

Regulator

Timing Generator

CPU core

6502

Interrupt
Controller

H/V Sync Signals

Processor

OTP Program ROM

32K Bytes

SRAM + STACK

512 Bytes

8-Bit Base Timer

Watch Dog Timer

IIC BUS

PWM DACs

A/D Converter

I/O Ports

SCL0
SDA0
SCL1
SDA1

DAC0 - DAC7
DAC8 - DAC12

ADC0 - ADC3

P00 - P07

P10 - P16
P20 - P27
P30 - P31
P40 - P41

2

Pin Description

NT68P62-01

Pin No.

40 Pin 42 Pin

1 1 DAC2

2 2 DAC1/ADC3 DAC1 O Open drain 5V, D/A converter output 1, shared with A/D

3 3 DAC0/ADC2

4 4

5 5 VDD P Power
6 7 GND P Ground
7 8 OSCO O Crystal OSC output
8 9 OSCI I Crystal OSC input
9 10 P15/INTE0 I/O

Designation Reset Init. I/O Description

O

Open drain 5V, D/A converter output 2

[ I ]

[PGM ]

[OE ]

RESET

[ VPP ]

DAC0 O Open drain 5V, D/A converter output 0, shared with A/D

[ P ]

[OTP ROM program control]

converter channel 3 input

converter channel 2 input
[OTP ROM program output enable]

I

Schmitt Trigger input pin, low active reset with internal
pulled down 50K Ω register *

[OTP ROM program supply voltage]

Bi-directional I/O pin with internal pulled up 22KΩ register,
shared with input pin of external interrupt source0 (NMI),
with schmitt trigger, selectable triggered, and internal pulled
up 22K Ω register

10 11 P14/PATTERN

[ A15/CE ]

11 12 P13/HALFI

[ A11 ]

12 13 P12/HALFO

[ A10 ]

13 14 P11/ADC1

[ A9 ]

14 15 P10/ADC0

[ A8 ]

15 16 P16/INTE1 P16 I/O

P13 I/O

P12 I/O

P11 I/O

P10 I/O

I/O

[ I ]

[ I ]

[ I ]

[ I ]

[ I ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with the output of self test pattern

[ OTP ROM program address buffer & chip enable ]
Bi-directional I/O pin with internal pulled up 22K Ω register,

shared with half hsync input, shared with A/D converter
channel 3 input
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with half hsync output
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with A/D converter channel 1 input
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with A/D converter channel 0 input
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22KΩ register,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22K Ω register

3

Pin Description (continued)

NT68P62-01

Pin No.

Designation Reset Init. I/O Description

40 Pin 42 Pin

16 - 23 17 - 24 P27 – P20

[ DB7 ] – [ DB0]

24 25 P30/SDA0

[ A12 ]

25 26 P31/SCL0

[ A13 ]

26 27 P00/DAC7

[ A0 ]

27 28 P01/DAC8

[ A1 ]

28 29 P02/DAC9

[ A2 ]

29 30 P03/DAC10

[ A3 ]

I/O

[ I/O ]

P30 I/O

[ I ]

P31 I/O

[ I ]

P00 I/O

[ I ]

P01 I/O

[ I ]

P02 I/O

[ I ]

P03 I/O

[ I ]

Bi-directional I/O pin, push-pull structure with high current
drive/sink capability
[ OTP ROM program data buffer ]

Open drain 5V bi-directional I/O pin P30, shared with SDA0
pin of I2C bus Schmitt Trigger buffer
[ OTP ROM program address buffer ]

Open drain 5V bi-directional I/O pin P31, shared with SCL0
pin of I2c bus Schmitt Trigger buffer
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 8
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 9
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 10
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 11
[ OTP ROM program address buffer ]

30 31 P04/DAC11

[ A4 ]

31 32 P05/DAC12

[ A5 ]

32 33 P06/VSYNCO

[ A6 ]

33 34 P07/HSYNCO

[ A7 ]

34 35 CREG O On chip voltage regulator output, external regulating

35 36 DAC6

[RESET]

36 38 DAC5/SDA1

[ MODE2 ]

P04 I/O

[ I ]

P05 I/O

[ I ]

P06 I/O

[ I ]

P07 I/O

[ I ]

O

[ I ]

O

[ I ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 12
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with open drain 5V D/A converter output 13
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with vsync out
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22K Ω register,
shared with hsync out

[ OTP ROM program address buffer ]

cap.(10µF ~ 100µF) should be connected here
Open drain 5V, D/A converter output 6
[ OTP ROM reset ]
Open drain 5V, D/A converter output 5, shared with open

drain SDA1 line of I2C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]

4

Pin Description (continued)

Pin No. Designation Reset Init. I/O Description

40 Pin 42 Pin

NT68P62-01

37 39 DAC4/SCL1

[ MODE1 ]

38 40 DAC3

[ MODE0 ]

39 41 HSYNCI I Debouncing & Schmitt Trigger input pin for video horizontal

40 42 VSYNCI/INTV

[ A14 ]

- 6 P40 I/O

- 37 P41 I/O

* This RESET pin must be pulled high by external pulled-up register (5KΩ suggestion), or it will remain in low voltage to

continually rest system.

VSYNCI I

O

Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I2C bus, Schmitt Trigger buffer

[ I ]

[ OTP ROM mode select ]

O

Open drain 5V, D/A converter output 3

[ I ]

[ OTP ROM mode select ]

sync signal, internal pull high, shared with composite sync
input

Debouncing & Schmitt trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of

[ I ]

external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22KΩ register
[ OTP ROM program address buffer ]

Bi-directional I/O pin with internal pulled up 22KΩ register,
only 42 pin S-DIP available

Bi-directional I/O pin with internal pulled up 22KΩ register,
only 42 pin S-DIP available

5

NT68P62-01

Functional Description

1. 6502 CPU

The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges,
and interrupt input options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Please refer to the 6502 data sheet for more detailed
information.

07

Accumnlator A

7

Index Register Y

7 0

Index Register X

Program Counter PCH

PCL

7 0
7

Stack Pointer SP

N V

B

ZID

0

815

0

07
C

Status Register P

Carry
Zero
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative

1=TRUE
1=Result ZERO
1=DISABLE
1=TRUE
1=BRK
1=TRUE
1=NEG

Figure 1.1. The 6502 CPU Registers and Status Flags

6

2. Instruction Set List

Instruction Code Meaning Operation

NT68P62-01

ADC Add with carry
AND Logical AND

ASL Shift left one bit

BCC Branch if carry clears

BCS Branch if carry sets
BEQ Branch if equal to zero

BIT Bit test

BMI Branch if minus

BNE Branch if not equal to zero

BPL Branch if plus
BRK Break
BVC Branch if overflow clears Branch on V ＝ 0

BVS Branch if overflow sets Branch on V ＝ 1
CLC Clear carry 0 → C
CLD Clear decimal mode

A + M + C → A, C
A•M → A
C ← M7 …M0 ← 0
Branch on C ＝ 0
Branch on C ＝ 1
Branch on Z ＝ 1
A•M, M7 →N, M6 →V
Branch on N ＝ 1
Branch on Z ＝ 0
Branch on N ＝ 0
Forced Interrupt PC+2↓ PC↓

0 → D

CLI Clear interrupt disable bit

CLV Clear overflow

CMP Compare Accumulator to memory

CPX Compare with index register X
CPY Compare with index register Y

DEC Decrement memory by one

DEX Decrement index X by one
DEY Decrement index Y by one

EOR Logical exclusive-OR

INC Increment memory by one

INX Increment index X by one
INY Increment index Y by one Y + 1 → Y

0 → I
0 → V
A － M
X － M
Y － M
M － 1 → M
X － 1 → X
Y － 1 → Y
A ⊕ M→A
M + 1 → M
X + 1 → X

7

Instruction Set List (continued)

Instruction Code Meaning Operation

NT68P62-01

JMP Jump to new location

JSR Jump to subroutine

LDA Load accumulator with memory

LDX Load index register X with memory M → X

LDY Load index register Y with memory
LSR Shift right one bit

NOP No operation No operation (2 cycles)

ORA Logical OR
PHA Push accumulator on stack
PHP Push status register on stack

PLA Pull accumulator from stack

PLP Pull status register from stack P ↑
ROL Rotate left through carry

ROR Rotate right through carry

RTI Return from interrupt

RTS Return from subroutine

(PC+1)→ PCL, (PC+2)→ PCH
PC+2↓, (PC+1)→ PCL, (PC+2)→ PCH
M → A

M → Y
0 → M7 …M0 → C

A + M → A
A ↓
P ↓
A ↑

C ← M7 …M0 ← C
C → M7 …M0 → C
P ↑, PC ↑

PC ↑, PC+1 → PC
SBC Subtract with borrow A － M － C → A, C
SEC Set carry
SED Set decimal mode

SEI Set interrupt disable status
STA Store accumulator in memory
STX Store index register X in memory X → M
STY Store index register Y in memory
TAX Transfer accumulator to index X
TAY Transfer accumulator to index Y
TSX Transfer stack pointer to index X
TXA Transfer index X to accumulator X → A
TXS Transfer index X to stack pointer
TYA Transfer index Y to accumulator

* Refer to 6502 programming data book for more details.

1 → C
1 → D
1 → I
A → M

Y → M
A → X
A → Y
S → X

X → S
Y → A

8

NT68P62-01

3. RAM: 512 X 8 bits

The built-in 512 X 8-bit SRAM is used for data memory and stack area. The RAM addressing range is from $0080 to $027F.
The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can
allocate stack area in the RAM by setting stack pointer register (S). Because the 6502 default stack pointer is $01FF,
programmers must set S register to FFH when starting the program.

as; LDX #$FF

TXS

$0000

$003D

$0080

System Registers

Unused

$01FF

$027F

$0280

$7FFF

$8000

( 32 K Bytes )

RAM

( 512 Bytes )

Unused

OTP

ROM

stack pointer

$FFFA NMI-L

$FFFB
$FFFC RST-L
$FFFD

$FFFE

$FFFF

NMI-H

RST-H

IRQ-L

IRQ-H

NMI vector

RESET vector

IRQ vector

4. ROM: 32K X 8 bits

NT68P62 provides 32K ROM space for programming. The ROM space is located from $8000 to $FFFF.
The addresses, from $FFFA to $FFFF, are reserved for the 6502 CPU vectors, thus users must arrange them by
themselves.

9

NT68P62-01

INSEN

INSEN

ENHOUT

ENHOUT

ENHDIFF

5. System Registers

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

Control Registers for I/O Port0 & Port1

$0000 PT0 FFH P07 P06 P05 P04 P03 P02 P01 P00 RW
$0001 PT1 7FH - P16 P15 P14 P13 P12 P11 P10 RW

Control Register to Control Port2 I/O Direction

$0002 PT2DIR FFH

$0003 PT2 FFH P27 P26 P25 P24 P23 P22 P21 P20 RW
$0004 PT3 03H - - - - - - P31 P30 RW
$0005 PT4 03H Only available for the 42 Pin SDIP version - P41 P40 RW

FFH - - - ­FFH - - - ­FFH - - HSYNCI VSYNCI HPOLI VPOLI HPOLO VPOLO R$0007 HV CON

FFH

P27OE P26OE P25OE P24OE P23OE P22OE P21OE P20OE

Control Registers for I/O Port2 - 4

Control Registers for Synprocessor

-

ENHSEL HSEL S/C

HSEL S/C

- - - - HPOLO VPOLO W

W

R$0006 SYNCON

W

$0008 HCNT L 00H HCL7 HCL6 HCL5 HCL4 HCL3 HCL2 HCL1 HCL0 R

HCNTOV - - - HCH3 HCH2 HCH1 HCH0 R$0009 HCNT H 00H

CLRHOV - - - - - - - W

$000A VCNT L 00H VCL7 VCL6 VCL5 VCL4 VCL3 VCL2 VCL1 VCL0 R

VCNTOV - VCH5 VCH4 VCH3 VCH2 VCH1 VCH0 R$000B VCNT H 00H
CLRVOV - - - - - - - W

$000C FREECON FFH

$000D HALFCON FFH

$000E AUTOMUTE FFH

ENPAT PAT1

ENHALF NOHALF

ENPOL ENOVER

- - -

HALFPOL

- - - - - W

- HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0 W

FREQ2 FREQ1 FREQ0

Control Registers to Enable PWM 8 - 15 Channels

$000F ENDAC FFH - -

ENDK12 ENDK11

ENDK10

ENDK9

ENDK8

ENDK7

Control Registers for ADC 0 - 3 Channels

$0010 ENADC FFH

CSTA

- - -

ENADC3 ENADC2 ENADC1 ENADC0
$0011 AD0 REG C0H - - AD05 AD04 AD03 AD02 AD01 AD00 R
$0012 AD1 REG 00H - - AD15 AD14 AD13 AD12 AD11 AD10 R
$0013 AD2 REG 00H - - AD25 AD24 AD23 AD22 AD21 AD20 R
$0014 AD3 REG 00H - - AD35 AD34 AD33 AD32 AD31 AD30 R

W

W

W

10

NT68P62-01

System Registers (continued)

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests

- - - - - - INTE0 INTMUTE R$0016 NMIPOLL 00H

- - - - - - CLRE0 CLRMUTE W

$0017 IRQPOLL 00H - - - - - IRQ2 IRQ1 IRQ0 R

Control Registers of Interrupt Enable

$0018 IENMI 00H - - - - - - INTE0 INTMUTE RW
$0019 IEIRQ0 00H - - INTS0 INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 RW

$001A IEIRQ1 00H - - INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 RW

$001B IEIRQ2 00H - - - - INTADC INTV INTE1 INTMR RW

Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests

- - INTS0 INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 R$001C IRQ0 00H

- - CLRS0 CLRA0 CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0 W

- - INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 R$001D IRQ1 00H

- - CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 W

- - - - INTADC INTV INTE1 INTMR R$001E IRQ2 00H

- - - - CLRADC CLRV CLRE1 CLRMR W

Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts

$001F TRIGGER FFH - - - - - INTVR INTE1R INTE0R R/W

Control Registers for Clearing Watch Dog Timer

$0020 CLR WDT - 0 1 0 1 0 1 0 1 W

Control Register for DDC1/2B+ of Channel 0

$0021 CH0ADDR A0H ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 - W
$0022 CH0TXDAT 00H TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 W
$0023 CH0RXDAT 00H RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 R

E0H

ENDDC

- -

$0025 CH0CLK FFH

$0026 CH1ADDR A0H ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 - W
$0027 CH1TXDAT 00H TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 W
$0028 CH1RXDAT 00H RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 R

MODE MRW RSTART

MD1/ 2

Control Register for DDC1/2B+ of Channel 1

- START STOP -

SRW

START STOP - - - R

- - DDC2BR2 DDC2BR1 DDC2BR0 W

TXACK

- W$0024 CH0CON

11

NT68P62-01

System Registers (continued)

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

ENDDC

MD1/ 2

- START STOP ­TXACK

- W$0029 CH1CON E0H

- -

$002A CH1CLK FFH

$002E BT 00H BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 W
$002F BTCON 03H - - - - - -

$0030 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0031 DACH1 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0032 DACH2 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0033 DACH3 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0034 DACH4 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0035 DACH5 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0036 DACH6 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0037 - - - - - - - - ­$0038 DACH7 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0039 DACH8 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$003A DACH9 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

MODE MRW RSTART

Control Registers for PWM Channel 0 - 13

SRW

Control Registers for Base Timer

START STOP - - - R

- - DDC2BR2 DDC2BR1 DDC2BR0 W

BTCLK ENBT

W

$003B DACH10 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$003C DACH11 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$003D DACH12 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

12

6. Timing Generator

This block generates the system timing and control signal
to be supplied to the CPU and on-chip peripherals. A
crystal quartz, ceramic resonator, or an external clock
signal which will be provided to the OSCI pin generates
system timing. It generates 8MHz system clock, 4MHz for
the CPU. Although internal circuits have a feedback resister

NT68P62-01

and compacitor included, users can externally add these
components for proper operating.
The typical clock frequency is 8MHz. Different frequencies
will affect the operation of those on-chip peripherals whose
operating frequency is based on the system clock.

OSCI

8MHz

OSCO

(1)

NT68P62

Figure 6.1. Oscillator Connections

7. RESET

The NT68P62 can be reset by the external reset pin or by
the internal watch-dog timer. This is used to reset or start
the microcontroller from a POWER DOWN condition.
During the time that this reset pin is held LOW (*reset line
must be held LOW for at least two CPU clock cycles),
writing to or from the µC is inhibited. When a positive edge
is detected on the RESET input, the µC will immediately
begin the reset sequence.
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the µC will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.

An internal Schmitt Trigger buffer at the RESET pin is
provided to improve noise immunity.

External Clock

Unconnected

The reset status is as follows:

1. PORT0、PORT1、PORT2、PORT3 (& PORT4) pins
will act as I/O ports with HIGH output

2. Sync processor counters reset and VCNT | HCNT
latches cleared

3. All sync outputs are disabled

4. Base timer is disabled and cleared

5. Various Interrupt sources are disabled and cleared

6. A/D converter is disabled and stopped

7. DDC1/2B+ function is disabled

8. PWM DAC0 – DAC6 output 50% duty waveform and
DAC7 - DAC12 is disabled

9. Watch-dog timer is cleared and enabled

OSCI

OSCO

NT68P62

(2)

13

NT68P62-01

8. A/D Converters

The structure of these analog to digital converters is 6-bit
successive approximation. Analog voltage is supplied from
external sources to the A/D input pins and the result of the
conversion is stored in the 6-bit data latch registers ($0011
& $0014). The A/D channels are activated by clearing the
correspondent control bits in the ENADC control register.
When users write '0' into one of the enable control bits, its
correspondent I/O pin or DAC will be switched to the A/D
converter input pin (ADC0 & ADC1 shared with PORT10 &
PORT 11; ADC2 & ADC3 shared wit DAC0 & DAC1).

Conversion will be started by clearing CSTA bit

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

(CONVERSION START) in the ENADC control register.
When conversion is finished, system will set this INTADC
bit. Users can monitor this bit to get the valid A/D
conversion data in the AD latch registers ($0011 - $0014).
Users can also open interrupt sources to remind users to
get the stable digital data. Notice that only at the activated
A/D channel, its latched data are available.

The analog voltage to be measured should be stabled
during the conversion operation and the variation will not

exceed LSB for the best accuracy in measurement.

$0010 ENADC FFH

$0011 AD0 REG C0H - - AD05 AD04 AD03 AD02 AD01 AD00 R
$0012 AD1 REG 00H - - AD15 AD14 AD13 AD12 AD11 AD10 R
$0013 AD2 REG 00H - - AD25 AD24 AD23 AD22 AD21 AD20 R
$0014 AD3 REG 00H - - AD35 AD34 AD33 AD32 AD31 AD30 R
$001B IEIRQ2 00H - - - - INTADC INTV INTE1 INTMR R/W
$001E IRQ2 00H - - - - INTADC INTV INTE1 INTMR R

Reference ADC Table (V

CSTA

- - - - CLRADC CLRV CLRE1 CLRMR W

= 5.0V)

DD

- - -

ENADC3 ENADC2 ENADC1 ENADC0

15 1.50V 1C 2.06V 23 2.59V 2A 3.14V
16 1.58V 1D 2.12V 24 2.67V 2B 3.22V
17 1.66V 1E 2.20V 25 2.75V 2C 3.30V
18 1.74V 1F 2.28V 26 2.82V 2D 3.38V
19 1.82V 20 2.35V 27 2.91V 2E 3.46V
1A 1.90V 21 2.44V 28 2.98V 2F 3.54V

1B 1.98V 22 2.51V 29 3.07V 30 3.62V

W

Note: It is strongly recommended that the ADC’s input signal should be allocated in the ADC’s linear voltage range

(1.5V~3.5V) to obtain a stable digital value. Do not use the outer ranges (0V~1.4V & 3.6V~5.0V) in which the
converted digital value is not guaranteed.

14

NT68P62-01

9. PWM DACs (Pulse Width Modulation D/A Converters)

There are 13 PWM D/A converters with 8-bit resolution in NT68P62. All of these D/A (DAC0 - DAC12) converters are open­drain output structure with external 5V applied maximum. DAC0 – DAC6 are dedicated PWM channels, and DAC7 - DAC12
are shared with I/O pins. Those shared PWM channels are activated by clearing the correspondent control bits in the
ENDAC control register ($000F). When users write '0' into one of the enable control bits, its correspondent I/O pin will be
switched to PWM output pin.

The PWM refresh rate is 62.5KHz operating on 8MHz system clock. There are 13 readable DACH registers corresponding to
13 PWM channels ($0030 - $003D). Each PWM output pulse width is programmable by setting the 8 bit digital to the
corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND level) and every
1 bit addition will add 62.5ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output). (Please refer to Figure

9.1 for the detailed timing diagram of PWM D/A output.)

Fosc

8MHz

00

01

02

03

m

255(FF)

255 0 1 2 m

3 m-1 0

Figure 9.1. The DAC Output Timing Diagram and Wave Table

255

1PWM value :

15

NT68P62-01

ENDK7

PWM DACs (continued)

DAC0 & DAC1 are shared with ADC2 & ADC3 input pins respectively. If ENADC2/ 3 bit in the ENADC control register is
cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC2/ 3 bits will be in HIGH state

and DAC0 & DAC1 will act as PWM output pins.

DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the ENDDC bit in the CH1CON control
register to LOW, channel 1 of DDC will be activated. When used as DDC channel, the I/O port will be an open drain structure

and include 'Schmitt Trigger' buffer for noise immunity. After the chip is reset, ENDDC bits will be in HIGH state and DAC4 ­DAC5 will act as PWM output pins.

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

$000F ENDAC FFH - -

$0010 ENADC FFH

$0030 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0031 DACH1 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0032 DACH2 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0033 DACH3 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0034 DACH4 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0035 DACH5 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0036 DACH6 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0037 - - - - - - - - ­$0038 DACH7 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0039 DACH8 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$003A DACH9 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

$003B DACH10 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$003C DACH11 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$003D DACH12 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW

CSTA

ENDK12 ENDK11

- - -

ENDK10 ENDK9

ENADC3 ENADC2 ENADC1 ENADC0

ENDK8

DAC control register ($000F) and DAC value register ($0030 - $003D)

W

W

16

NT68P62-01

10. Watch-Dog Timer (WDT)

The NT68P62 implements a watch-dog timer reset to avoid
system stop or malfunction. The clock of the WDT is from
on-chip RC oscillator which does not require any external
components. Thus, the WDT will run, even if the clock on
the OSCI/OSCO pins of the device have been stopped.
The WDT time interval is about 0.5 second. The WDT must

as; LDA #$55

STA $0020

Addr. Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W

$0020 CLR WDT - 0 1 0 1 0 1 0 1 W

11. Interrupt Controller

The system provides two kinds of interrupt sources: NMI &
IRQ. The NMI can not be masked and if enabling NMI
interrupt sources, users will execute the NMI interrupt
vector anytime when sources are activated. The IRQ
interrupts can be masked by executing a CLI instruction or
setting the interrupt mask flag directly in the µC status
register. In process IRQ interrupt, if the interrupt mask flag
is not set, the µC will begin an interrupt sequence. The
program counter and processor status register will be
stored in the stack. The µC will then set the interrupt mask
flag HIGH so that no further interrupts may occur. At the
end of this cycle, the program counter will be loaded from
addresses $FFFE & $FFFF, then transferring program
control to the memory vector located at these addresses.
For NMI interrupt, µC will transfer execution sequence to
the memory vector located at addresses $FFFA & $FFFB.

be cleared within every 0.5 second when the software is in
normal sequence, otherwise the WDT will overflow and
cause a reset. The WDT is cleared and enabled after the
system is reset, and can not be disabled by the software.
Users can clear the WDT by writing 55H to CLRWDT
register ($0020).

When manipulating various interrupt sources, NT68P62
divides them into two groups for accessing them easily.
One is NMI group and the other is IRQ group.

- The NMI group includes INTE0, INTMUTE.

- The IRQ group includes subgroup of IRQ0, IRQ1,RQ2:
IRQ0: DDC1/2B+ Channel 0 interrupt sources; It

includes INTS0, INTA0, INTTX0, INTRX0,
INTNAK0 and INTSTOP0 interrupts.

IRQ1: DDC1/2B+ Channel 1 interrupt sources; It

includes INTS0, INTA1, INTTX1, INTRX1,
INTNAK1 and INTSTOP1.

IRQ2: It includes INTADC, IN TV, INTE1 and INTMR

interrupt sources.

Below are the interrupt sources.

Nonmaskable Interrupt Group:

Interrupt Meaning Action

INTE0 INT External 0 INT It will be activated by the rising edge or falling edge of external interrupt pulse.

The triggered edge can be selected by EDGE0 bit.

INTMUTE Auto Mute It will be activated when the mute condition occurres (Hsync frequency

change). Please refer the synprocessor section for more detailed explanation.

Maskable Interrupt Group:

Interrupt Meaning Action

INTADC A/D Converion

Done

INTV INT Vsync INT It will be activated as the rising edge of every vsync pulse.

INTE1 INT External 1 INT It will be activated by the rising edge or falling edge of external interrupt pulse.

INTMR INT Timer INT It will be activated as the rising edge of every when the Base Timer counter

User activates the ADC by clearing the CSTART bit. When AD conversion is
done, this bit will be set.

The triggered edge can be selected by EDGE1 bit.

overflows and counting from $FF to $00.

17