The function of the BS1 PDA module in RAE–2 Communicator device is
to run all applications that utilize the PDA LCD display of the device. The
GEOS operating system is applied on a 486 based PDA module platform.
This processing platform utilizes the communicator–type user interface
which is accessible when the RAE–2 is opened.
Technical Summary
The BS1 PDA module consists of a printed circuit board with a CPU, two
kinds of memories, a Power unit, HF amplifier circuitry, and an IR–transceiver.
The PDA module is assembled on a single 8–layer printed circuit board.
All components are assembled on one single side. The other side is reserved for keyboard keypads.
Technical Documentation
Serial ports, DMA– and LCD controller for timers are integrated in the
CPU. The operating system is GEOS supplied by Geoworks.
The BS1 module includes three non–volatile Flash memories which are
used for two kind of purposes. XIP (executed in place) memory is used
for program file storage and RFD (resident flash disk) memory is writeable for user data.
One DRAM Memory is used for the code execution and for the volatile
storage of the internal run–time system data.
Both memory types (DRAM and Flash) have their own address– and data
bus, routed directly from the CPU.
Table 1. Used memory blocks
Memory typeAmount (Bytes)
Flash (XIP)4M
Flash (RFD)2M
DRAM2M
The BS1 PWRU block regulates the PDA module power and controls the
power-up and -down. After a battery has been connected, the PWRU
gives the CPU system voltage and releases the reset as fast as possible
after which the CPU SW has full power management control. The PWRU
also generates and controls the voltages that the PDA LCD uses. The
PDA has a rechargeable back–up battery which the PWRU block charges
when the main battery is connected. The VBACK voltage is normally always available for real time clock. Power is fed from the battery through
the CMT module to the PDA PWRU. The PWRU has a filter in battery
line to reduce interference from the CMT module. The PWRU provides
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Technical Documentation
A/D converter readings of the battery voltage and temperature via a parallel interface to the CPU. Many PWRU items can be controlled by register writing or directly via pin. The system voltage is always present until
battery voltage drops below 3.0V.
Electronics
The following sections of circuitry are included on the BS1:
PWRU Power supply unit
PDA CPU
IR transceiver
DRAM memory
Flash memory
HF Amplifier
Table 2. Supply Voltages and Power Consumption (continued)
Conn.
3/X800V28_1
21/N450V28_2
46/X830V28_3
16/X830VBB
NOTE : Complete temperature range
Technical Documentation
NotesUnitMaximumNominalMinimumLine SymbolPin /
2.702.802.85VDCLCD Logic voltage
14mACurrent
2.702.82.85VDCIrDA Logic voltage
24mACurrent
2.752.82.85VDCMMC supply voltage
0.0150100mACurrent
2.752.82.85VDCBase Band operating voltage
mACurrent
AC Characteristics
MinimumNominalMaximumUnit / Notes
External XT AL
CPU clock33.18MHz, Rise time
Memory bus clock33.18MHz, Rise time
Memory Controller clock66.3552MHz, Rise time
MMC clock during data0.25928.294Mhz, Rise time
MMC clock during identification
32.768kHz
20ppm, accuracy
1–2ns
2–3ns
1–2ns
2–3ns, NOTE1
259.2kHz, Rise time 2–3ns
NOTE: Frequency is a multiple of 259.2kHz
External Signals and Connections
This section describes the external electrical connection and interface levels on BS1 module. The electrical interface specifications are collected
into tables that cover each connector and defined interface.
Table 3. List of Connectors and testpoints
Connector NameCodeNotes
UI flex connectorX800CMT/PDA LCD– and Keyboard signals
Board to Board connectorX830CMT PDA interface
System connector padsX810
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Technical Documentation
Table 3. List of Connectors and testpoints
(continued)
BS1
NotesCodeConnector Name
Audio connector padsE880, E881,
HF–speaker connection and earpiece connection
E850, E851
Backup battery holderX451
TestpadsE300–E315Testpads ”under” battery pack
Frame connector padsX840Include manufacturing testpads. Is removed before
assembly
TestpointsJ310,
Testpoints around the BS1 PCB.
J400–J404,
J430, J434,
J435,
J440 – J456,
J497 – J499,
J801, J803,
J804, J808,
J854, J880,
J881
UI flex connector
The Interface between the BS2 and BS1 modules comprises a 51–pin
flex connector. The connector includes supply voltage for the BS2 module, and required information signals. Signals from the BS8 module are
also carried via the flex connector.
2.302.802.85VDCHigh, to the CMT
00.45VDCLow, to the CMT
2.12.802.85VDCHigh, from the
00.5VDCLow, from the CMT
2.752.802.85VDC
2mA
2.752.802.85VDCHigh, Cover open
0VDCLow, Cover closed
10kohm. Pull–up resistor
2.752.802.85VDCHigh, Cover open
0VDCLow, Cover closed
2.302.802.85VDCData to the card
00.45VDCData to the Card
2.12.802.85VDCdata from the card
0.34VDCData from the card
259.3kHzfrequency
2.752.85VDC
0.01100mACurrent
2.302.802.85VDCData to the Card
00.45VDCData to the card
2.12.802.85VDCData from the
00.34VDCData from the card
8.294MHzfrequency
CMT
High, Pulled up
with 10kohm resistor to MMC_VSYS
in CMT Module
Low
High, Pulled up
with 10kohm resistor to MMC_VSYS
in CMT Module
Low
High, Pulled up
with 10kohm resistor to MMC_VSYS
in CMT Module
Low
Card High, Pulled
up with 10kohm
resistor to
MMC_VSYS in
CMT Module
Low
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Technical Documentation
Table 5. Board to board connector X830
49OMMC_CLKMMC Clock
50GNDGlobal Ground
(continued)
Description /
UnitMaxNomMinFunctionNameI/OPin
Note
2.302.802.85VDCHigh
00.45VDCLow
0.25928.294MHzFrequency
BS1
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BS1
System connector pads
The RAE–2 System connector is a multipurpose connector, which is
shared with the BS8 module. In this section are described only the signals that are connected to the BS1 module. These signals are needed for
PC–connectivity. The connector comprises spring type contacts to the
BS1 and BS8 module. The PCB comprises pads on which the springs
are pressed.
Technical Documentation
Table 6. System Connector pads X810
PinLine
10DCE_DTRPDA CPU Data set
11GNDGlobal ground
Symbol
8DCT_TXPDA CPU Receive
9DCE_RXPDA CPU Transmit
Page 5 – 16
ParameterMinimumNominalMaximum UnitUnit / Notes
ata
ata
ready
2.02.802.85VDC
00.8VDC
2.302.802.85VDC
00.45VDC
2.02.802.85VDC
00.8VDC
Section 02/99
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Technical Documentation
Audio connector pads
The audio connector has two contact types. The earpiece contacts are of
spring type, and the contacts for the handsfree speaker are elastomeric
contacts.
Table 7. Audio connector pads
PinLine
Symbol
E850EARPEarpiece positive
E851EARNEarpiece negative
E880PHFEARNHandsfree speaker
E881PHFEARPHandsfree speaker
ParameterMinimumNominalMaximumUnitUnit / Notes
node
node
negative node
positive node
BS1
50223mVpp Differential voltage between
EARP and EARN nodes
6.0VppVBATT=4.4V. Differential voltage between PHFEARN and
PHFEARP nodes
4.4VppVBATT=3.6V. Differential voltage between PHFEARN and
PHFEARP nodes
6.0VppVBATT=4.4V. Differential voltage between PHFEARN and
PHFEARP nodes
4.4VppVBATT=3.6VBATT=4.4V. Differential voltage between
PHFEARN and PHFEARP
nodes.
Backup battery
Figure 2. Backup battery insertion direction
NOTE: Positive node is against PCB, it can be identified by 2mm diameter contact plate
Table 8. Backup battery holder X450
PinNameFunctionMinNomMaxUnitDescription / Note
VBACKBackup battery voltage2.43.03.1VDC
GNDGlobal ground
Section 02/99
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BS1
Internal Signals and Connections
Table 9. IR–transceiver (N300) signals
PinLine
Symbol
3TXDTransmit data from CPU
4RXDReceive data to CPU
Table 10. Signals between PDA CPU and Flash memories
NameFunctionMinNomMaxUnitDescription / Note
SA(21:1)System address
SD(15:0)System data from CPU
ROMCS(2:0)Chip selects for Flash memo-
FLSHWRxFlash write signal
ROMRDxFlash read signal
GPIO_CS1Write protect for RFD memory
GPIO_CS7RFD Flash ready
ParameterMinimumNominalMaximumUnit / Notes
2.30V2.80V2.85V
0V0.45V
2.0V2.8V2.85V
00.8V
2.302.802.85VDCHigh
2.302.82.85VDCHigh
System data from memory
ries
2.402.82.85VDCHigh
2.302.802.85VDCHigh
2.302.802.85VDCHigh
2.302.802.85VDCHigh
2.302.802.85VDCHigh
2.02.802.85VDCHigh, ready
Technical Documentation
00.4VDCLow
00.4VDCLow
00.4VDCLow
00.4VDCLow
00.4VDCLow, write enabled
00.4VDCLow, read enabled
00.4VDCLow, powered down
00.8VDCLow, busy
Table 11. Signals between PDA CPU and DRAM Memory
NameFunctionMinNomMaxUnitDescription / Note
MA(11:0)Memory address
SD(15:0)Memory data from CPU
Memory data from memory
RAS0Row access strobe
CAS(1:0)Column access strobe
MWExMemory write enable
2.302.802.85VDCHigh
00.4VDCLow
2.302.82.85VDCHigh
000.4VDCLow
2.02.82.85VDCHigh
000.6VDCLow
2.302.802.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow, write enabled
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Technical Documentation
Table 12. Signals between PDA CPU and PWRU
NameFunctionMinNomMaxUnitDescription / Note
SA(2:0)System address
SD(6:0)System data
CS3xChip select for Phaser
IOWxPhaser write signal
IORxPhaser read signal
RESETxReset for CPU, and for Flash
memories.
VBACKBack–up battery voltage2.403.03.1VDCHigh
V17_ENLCD bias voltage enable
V28_1ENLCD logic voltage enable
2.302.802.85VDCHigh
00.4VDCLow
2.402.82.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow, write enabled
2.302.802.85VDCHigh
00.4VDCLow, read enabled
2.302.802.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow
2.302.802.85VDCHigh
00.4VDCLow
BS1
Section 02/99
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BS1
Functional Description
Power Unit
V17
V28_1
MMCV28_3
IrDA
HF–
power amp.
V28_2
VPDA
VPDA
VBATT
V28_1
PWRU
V28
VPDAVPDA
Interm.voltages 1–4
PWRGOOD
PWRGOOD
Charging
VBB
IOW
IOR
ADD(2:0)
DATA (6:0)
CS3x
V28_EN
V17_EN
RESETx
VBACK
BS2
TESTPADS
VSYS
Am486 CPU
PMI
NMI
PMI
Technical Documentation
BS1
VSYS
DRAM
VSYS
XIP
XIP
Write protect
NMI
Flashes
RESETx
VSYS
VPP
RESETx
RFD
RFD
Flash
VPP
FRAME CONNECTOR
Backupbattery
Lid Switch
VBATT
VSYS
VBB
BATTDET
MMC_SWITCH
BS8
Figure 3. PDA Power distribution diagram
Battery voltage is supplied from the BS8 module through a board to board
connector. In the BS1 module the battery voltage is filtered and then supplied to the Phaser, IR–transceiver circuit, BS2 module, and PHF–speaker circuitry.
The phaser generates internally the system voltage V28, switched voltages V28_1 ,V28_2, V28_3, the LCD bias voltage V17, the LCD intermediate voltages V17_ix, x=1–4 and the backup battery charging voltage
VBACK.
When the battery voltage level is adequate, the PWRU switches V28 on
and after a certain time releases the reset–signal for the CPU. The CPU
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Technical Documentation
controls the LCD, MMC, and IR–transceiver logic voltages by writing command to the PWRU register. Optionally the CPU can control the LCD logic- and biasing voltage directly by means of I/O signals.
The backup battery supplies power to the CPU’s real time clock. The
PWRU charges the backup battery when the main battery is connected.
The CPU puts the Flash memories to power down mode when they are
not used.
The BS8 signal BATTDET is a warning signal that the battery will be removed soon, when power down procedure is started. VBB is the supply
voltage for the CMT display, located in the BS2 module, and the VBB
provides information for the BS1 CPU whether the CMT powered or not
and it enables the keyboard buffer. The MMC_SWITCH indicates that the
MMC card will be removed, when the CPU controls the Phaser to turn the
V28_3 off.
Input filter
BS1
The Battery voltage is fed from the BS8 module and then filtered by using
a LC–lowpass filter, after filtering the voltage is named VPDA. The VPDA
is then fed to the PWRU, the IR–transceiver, the PHF–speaker circuitry,
and to the BS2 module.
Linear regulator V28
System voltage V28 is generated by a linear regulator. V28 stays on all
the time when the battery voltage is higher than cutoff limit.
Linear regulator V28_1,_2,_3
These regulators are controlled by the CPU. The CPU can enable these
regulators by writing a command to the PWRU’s register. V28_1 is the
switched V28 and is used for the LCD logic. V28_2 is the switched V28
and is used for the IRDA logic. V28_3 is the MMC voltage.
Switchmode regulator V17
The LCD bias voltage V17 is generated by a step–up DC–DC converter.
The control scheme is the current limited pulse width modulation (PWM).
The switching transistor is internal. The regulator output, too, is separated from the battery line by an integrated switch transistor between the
regulator output and load.
Backup battery
The Real time clock is kept running by a backup battery only when the
main battery is not connected. At the nominal RTC load used , the
12mAh capacity of the backup battery provides about 40 days of RTC operation when the main battery is not connected. The backup battery is
Section 02/99
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BS1
rechargeable. It is charged by the Phaser VBACK regulator using 0.5mA
current when the main battery is connected.
Reset and power management
The Phaser is connected to the I/O space of the H3 by using a 7 bit wide
data bus and a 3 bit wide address bus. The BS2 PDAPWRU on the PDA
board supplies two different voltage levels to the system;
2.85V is used as the main operating voltage for all circuits and
about 19V that is needed for the LCD bias (V17). The LCD bias voltage is
used to adjust the contrast ratio of the LCD screen. The LCD bias voltage is controlled by the Phaser ASIC.
The V17 and V28_1 ON/OFF are switched by the Phaser, but optionally
also the CPU can control these signals directly with HW means, independently of the SW controlled register settings. The phaser provides also
the POWERGOOD signal for the CPU. The system reset circuit is part of
the power supply. When the battery voltage is higher than 3.4V a
PWRGOOD is generated for the CPU. The reset circuit also asserts the
reset signal whenever the Vcc supply voltage declines below the threshold, keeping it asserted for at least 50ms after Vcc has risen above the
reset threshold. The reset circuit is designed to ignore fast transients
(t < 64µs) in Vcc.
Technical Documentation
There is an undervoltage lockout (UVLO) block inside the Phaser. Below
the threshold limit the comparator shuts down all Phaser functionality to
prevent the battery from overdischarge. Otherwise the VSYS regulator
current drains the battery when left unused for long period. After the
UVLO there is only reference block in the Phaser drawing current from
the battery. The UVLO has a little hysteresis and is cancelled when the
battery voltage has risen to 2.7V. However, reset to the CPU is given only
when battery voltage rises to 3.45V. This in order to avoid unsuccessful
power–ups. When the lockout voltage level is reached, the battery voltage rises because the load is removed.
PDA CPU
The PDA CPU is a SC450–33CC in a 256 pin plastic ball grid array package.
The core features a 32–bit architecture with internal 8k write–back cache.
The clock rate is 33MHz, which can be slowed down to1MHz. The default clock rate on reset is 8.29MHz. The bus clock rate is 33MHz. A
32kHz clock signal for the BS8 module is provided by the CPU PLL circuit. The clock signal is started when ever the system voltage is applied
to the CPU.
The CORE starts when the reset signal is provided and then it begins to
execute the program code from the Flash memory. The external pull–up
resistor controls the start–up procedure (Boot code Chip select, and data
bus width).
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Technical Documentation
The memory controllers are integrated to the chip. A ROM controller is
used for Flash interface and a DRAM controller supports extended data
out (EDO) page mode DRAMs. Both memory types (DRAM and Flash)
have their own address and data bus routed directly to the CPU. The
power unit is controlled via an I/O-mapped 7-bit wide data- and 3-bit wide
address bus, which is shared with Flash data- and address bus. The CPU
block diagram is the figure below.
Am486SLE
Core
DMA
controller
8237
Reset
Loop filters
x32kHz
32kHz xtal
Power
management
unit
Clock
generation
Real time
clock
Addr
Data
Addr
Memory
management
unit
Address
decoder
Data
steering
Graphics
controller
MMC bus
controller
BS1
SA bus
Data bus
LCD
MMC bus
JTAG port
GPIO’s
Boundary
scan
AT port
logic
Timer
8254
Interrupt
controller
8259
Memory
controller
Keyboard cntrl
matrix/XT
UART
16550
UART
16550
Elan SC450–33CC
DRAM control
ROM control
IrDA
infrared
controller
Columns
Rows
FBUS
Serial port
R–tranceiver
For serial interface two UART circuits are used. UART2 is a serial interface reserved for data transfer between the BS1 and BS8 modules.
UART2 is disabled or enabled according to the CMT voltage. UART1 is
used for RS–232 interface with external level changer. The UARTs can be
connected together to establish Re–Link connection, where received data
is directly linked to the UART’s transmit data pin. That way the BS8 module can be programmed by using an external RS-interface. Autobauding
detection circuitry is included in the UART1 block.
Section 02/99
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BS1
Technical Documentation
The LCD–controller supports a 4-bit data and 16-grey shades. The display control signals are routed from the CPU. The bigger (640x200) LCD
is located in the lid. The interconnection between the CPU and the LCD
comprises a flex through the hinge. Data and control signals are provided
by the CPU. The required voltages are supplied by the PWRU.
The PDA CPU supports a synchronous serial interface that is compatible
with the Multimedia Card Bus (MMC) Protocol. The MMC is changeable
Flash or ROM memory card with variable memory size. The MMC connector is located on the BS8 Module. MMC signals are routed to the BS8
module through a Board to board connector. The interface consists of
three pins: one clock(output), one command/response (bidirectional), and
one data pin (bidirectional). The controller is capable up to 8Mbits/second
transfer rate.
The keyboard controller includes a matrix keyboard which is used for
PDA keyboard and for PDA lid keys. The PC/AT standard core includes
a 8254 programmable interval timer, two 8259 programmable interrupt
controllers, and a real time clock. The CPU’s general purpose input/outputs (GPIO) are controlled by the CPU’s registers.
I/O Signals
In the Table 13 below are listed BS1 module I/O signals which are
mapped to general purpose pins of the CPU.
Table 13. Spock CPU Controllable I/O Signals
Scotty PinSignal NameLowHighNote
GPIO_CS1RFD_WPxWrite operationWrite not possible
GPIO_CS2XIP_STSMemory busyMemory readyInput, CS(1:0) Flash memory status
GPIO_CS5TESTMODExTestmode acti-
BL disabled
GPIO18BZR_ENReset, SuspendOperationEnables the PA.
BL1BATTDETBattery con-
nected
SUS/RESLIDSWITCHCover closedCover openSTI. Indicates when the coved is open
Reset, Suspend,
Operation
Reset, SuspendActivate the power on procedure for the
Flash ready for
new command
Reset, MMC cover open
Backlight activated
Battery removedIndicates when the battery is going to
Input.
CMT
Input. Open drain output, processor’s
internal pull–up is used. (Only for the
RFD)
Input. MMC cover status indication
module, Input otherwise.
Backlight EL driver controller.
be removed. Pin has build in 15ms debounce
or closed
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Table 13. Spock CPU Controllable I/O Signals (continued)
LVDDLVDDReset, SuspendPDA LCD Logic
LVEELVEEReset, SuspendPDA LCD bias
voltage activated
voltage activated
Memories
The memory units of the module are connected to the CPU via a 16–bit
wide data bus. Both memory types (DRAM and Flash) have an own
data– and address bus.
MD [15:0]
MA [11:0]
control [3:0]
DRAM
BS1
Routed to the Phaser
Routed to the Phaser
control [7:0]
BS1 CPU
SD [15:0]
SA [21:0]
DRAM memory
The 1Mx16bit DRAM is connected to the CPU with a dedicated 16–bit
wide data- and 12-bit wide address bus. The DRAM type used is the extended data out (EDO) DRAM with 60ns access time, and self–refresh
capability. DRAM is packaged in a 5.55mmX9.10mm, 40–ball uBGA
package.
XIP Flash 1RFD FlashXIP Flash 0
When the DRAM is driven by the CPU, no wait states is needed.
Flash memory
Three 1Mx16bit Flash memory devices are used for non–volatile memory.
The Flash type features a 120ns access time. The Flash is packaged in
8mmX11mm 64–ball CSP package. When the Flash is read by the CPU,
4 wait states are needed to ensure proper timing.
Section 02/99
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BS1
External Serial Interface
The UART1 External serial interface is used for PC–connectivity. The RS–
connection is provided by a 3–signal interface (RXD,TXD, and DTR)
which is routed to the system connector. Maximum data rate is
230.4kbps.
The re–link feature connects the UART1 and the UART2 (FBUS) internal-
ly together. This provides the signal routing from the system connector to
the CMT.
The Autobaud detection circuitry can detect bit rates from 300 bps tp
115.2kbps. The autobaud state machine starts when enabled by the CPU.
The bit rate measurement begins on the first negative edge of the
CPU_RXD line. After detecting the start bit width, and therefore the bit
rate, the remainder of the incoming data stream is sampled at this rate.
This UART is shared with the IrDA circuitry and thus only one of them can
be used at a time.
Technical Documentation
IR–Transceiver
The IR–transceiver controller is shared with the UART1. Infrared data
transfer is started with 9600bps and then the data rate is increased to
115.2kbps if the connected device supports higher speed. The protocol is
the standard one of the Infrared Data Association. The CPU hardware
implementation includes bit stuffing (when transmitting), CRC calculation,
removing bit stuffing, and removing beginning of frame (when receiving) .
Handsfree loudspeaker
The Handsfree speaker power amplifier circuitry is located on the BS1
module. The HF–speaker is used to produce the PDA key–click sounds,
error beeps, and tunes. When the lid is opened, the loudspeaker is used
as an handsfree speaker, producing key–click sound when a PDA
QWERTY key is pressed, and producing tunes. The HF–speaker power
amplifier can be controlled by the PDA CPU, or CMT.
Keyboard
The keyboard interface comprises 10x8 matrix lines. The QWERTY keyboard pads are located on the other side of the BS1 module board. 4x2
(2Row/4Column) matrix is routed to the lid. Four columns are multiplexed
with CMT keyboard columns. Multiplexing is done by using buffer located
on the BS1 module. This buffer is controlled by Baseband voltage (VBB).
When the lid is closed these four columns are switched to inputs and they
are not read by the CPU.
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Technical Documentation
Table 14. Key Reference Numbers vs. Senses and Drives.
NOTE1: Shift pads has dedicated Sense line (ROW9), These shift pads
are connected parallel
NOTE2: Grey shaded switches are located in BS2 module.
Figure 4. BS1 PDA keyboard
Section 02/99
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BS1
Test pads
Test pads are located under the battery pack. They include JTAG port
which is used for After Sales Flashing purposes. The different voltages
can be measured from these testpads. Serial data transfer test pads are
used for data transfer between the BS1 and BS8 modules.
Technical Documentation
Page 5 – 28
Figure 5. Test pad layout
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Technical Documentation
Table 15. Test pads
PinI/ONameFunctionMinNomMaxUnitDescription /
E300V17_OUTPDA LCD Biasing voltage
E301IBNDSCN_TMSBoundary scan Test mode se-
E302IBNDSCN_TCKBoundary scan test clock
E303IBNDSCN_TDIBoundary scan data in
E304OBNDSCN_TDOBoundary scan data out
E305IBNDSCN_ENBoundary scan enabled
E306IFlash VPPFlashing voltage for XIP
E307VBACKBackup battery voltage2.403.03.10VDCHigh
E308OFBUS_RXDPDA CPU Tx–pin
E309/
E311I/OMBUSBidirectional Serial Bus
E312VSYSSystem voltage2.752.802.85VDC
E313GNDGlobal Ground
E314IFLSHWRxWrite signal for Flash memo-
E315ITESTMODExtestmode activation
IFBUS_TXD1,2PDA CPU Rx–pin
lect
Flashes.
ries
Note
13.819.422.2VDCHigh
0VDCLow
2.02.802.85VDC High, test mode
selected
00.8VDCLow
2.02.802.85VDCHigh
00.8VDCLow
2.02.802.85VDCHigh
00.8VDCLow
2.302.802.85VDCHigh
00.45VDCLow
2.02.802.85VDCHigh, boundary
scan enabled
00.8VDCLow
2.752.802.85VDCConnected to
VBATT inside
the Service
battery.
2.302.802.85VDCHigh
00.45VDCLow
2.02.802.85VDCHigh
00.8VDCLow
2.302.802.85VDCHigh, to the
CMT
00.45VDCLow, to the
CMT
2.12.802.85VDCHigh, from the
CMT
00.5VDCLow, from the
CMT
2.302.802.85VDCHigh
00.45VDCLow, write en-
abled
2.02.802.85VDCHigh
00.8VDCLow, testmode
enabled
BS1
NOTE : Testpad E308 ... E310 is reserved for R&D use.
Section 02/99
Page 5 – 29
RAE–2
PAMS
BS1
Testpoints
Testpoints are located around the PDA PCB. They include clock, control,
data signals and voltages which is used for R&D, fault finding and testing
purposes.
Technical Documentation
Figure 6. Testpoints layout
Table 16. Testpoints
PointI/ONameFunctionMinNomMaxUnitDescription /
J310LID_SWITCH_IFLid switch state
J40033MHzCPU core clock
J401OX32_CLKCMT sleep clock
J402IVBBCMT baseband voltage
2.752.82.85VDCHigh, lid open
0VDCLow, lid closed
2.32.802.85VDCHigh
00.45VDCLow
2.32.802.85VDCHigh
00.45VDCLow
2.72.802.85VDCHigh
1.0mAMaximum cur-
Note
rent
Page 5 – 30
Section 02/99
PAMS
CPU
RAE–2
Technical Documentation
Table 16. Testpoints
J403I/OMBUSBidirectional Serial Bus
J404OPWR_ONx
J430LF_INTIntermidiate PLL loop filter1.2VDCWhen PLLs are
J434IX32IN
J435OX32OUT
J440ROMCS2RFD flash chip select
J441ROMCS0XIP1 flash chip select
J442FLASHWRx XIP and RFD flashes write
enable from
I XIP and RFD flashes write
enable from frame connector
or testpads
J443ROMRDxRFD flash read enable
J444WPRFD flash write protect
J445ROMCS1XIP2 flash chip select
J446RASxDRAM row address strobe
J447MWExDRAM write enable
J448CASL1xDRAM upper column address
select
J449CASL0xDRAM lower column address
select
J450FLASH_CTRL2RFD flash status
(continued)
UnitMaxNomMinFunctionNameI/OPoint
2.302.802.85VDCHigh, to the
00.45VDCLow, to the
2.12.802.85VDCHigh, from the
00.5VDCLow, from the
2.02.802.85VDCHigh
00.45VDCLow
1.35VDCHigh, Sini vawe
0VDCLow
1.0VDCHigh
–0.3VDCLow
2.32.802.85VDCHigh
00.45VDCLow, chip se-
2.32.802.85VDCHigh
00.45VDCLow, chip se-
2.32.802.85VDCHigh
00.45VDCLow, write en-
2.02.802.85VDCHigh
00.8VDCLow, write en-
2.32.802.85VDCHigh
00.45VDCLow, read en-
2.32.802.85VDCHigh
00.45VDCLow, write pro-
2.32.802.85VDCHigh
00.45VDCLow
2.32.802.85VDCHigh
00.45VDCLow
2.32.802.85VDCHigh
00.45VDCLow
2.32.802.85VDCHigh
00.45VDCLow
2.32.802.85VDCHigh
00.45VDCLow
2.42.802.85VDCHigh
00.4VDCLow
BS1
Description /
Note
CMT
CMT
CMT
CMT
locked
lected
lected
abled
abled
abled
tected
Section 02/99
Page 5 – 31
RAE–2
d
PAMS
BS1
Table 16. Testpoints
J451STS1XIP1 flash status
J452STS2XIP2 flash status
J453SD1System data bus line 1
J454SA4System address bus line 4
J455D0Memory data bus line 0
J456MA3Memory address bus line 3
J497VCOMP11.241.285VDC
J498CS3xPhaser chip select
J499RESETxReset from Phaser to CPU
and flash memories
J801OGENSDIOCMT LCD and CCONT serial
ata
J803I/OLCDCDCMT LCD command / data
select
J804I/OLCDCSxCMT LCD chip select
J808OSCKPDA LCD data clock2.32.802.85VDCHigh
J854BZR_IFBuzzer signal
J880HFENAHandsfree earpiece enable
J881OXEARAudio output for handsfree
use
(continued)
2.42.802.85VDCHigh
2.42.802.85VDCHigh
2.32.802.85VDCHigh, data to
2.42.82.85VDCHigh, data to
2.32.802.85VDCHigh
2.32.802.85VDCHigh
2.32.802.85VDCHigh
2.32.802.85VDCHigh
2.52.802.85VDCHigh
2.02.802.85VDCHigh
2.02.802.85VDCHigh, data
2.12.802.85VDCHigh
2.02.802.85VDCHigh
2.32.802.85VDCHigh, HF ampli-
Technical Documentation
UnitMaxNomMinFunctionNameI/OPoint
00.4VDCLow
00.4VDCLow
00.45VDCLow, data to
00.4VDCLow, data to
00.45VDCLow
00.45VDCLow
00.45VDCLow
00.4VDCLow, chip se-
00.5VDCLow
00.5VDCLow
00.6VDCLow, command
00.5VDCLow, chip se-
00.6VDCLow
00.45VDCLow, HF ampli-
2.0Vpp
Description /
Note
memory
memory
CPU
CPU
lected
lected
fied enabled
fied disabled
Page 5 – 32
Section 02/99
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