NEC uPD78F4218AYGF-3BA, uPD78F4218AGF-3BA, uPD78F4218AYGC-8EU, uPD78F4218AGC-8EU, uPD78F4216AYGF-3BA Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

16-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD78F4216A/78F4218A and 78F4216AY/78F4218AY are products of µPD784216A/784218A,

784216AY/784218AY Subseries in the 78K/IV Series.

The µPD78F4216A/78F4218A have flash memory in place of the internal ROM of the µPD784216A/784218A. The

incorporation of flash memory allows a program to be written or erased while mounted on the target board.

The µPD78F4216AY/78F4218AY are based on the µPD78F4216A/78F4218A Subseries with the addition of a

multimaster-supporting I2C bus interface.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

PD784216A, 784216AY Subseries User’s Manual Hardware: U13570E

µµµµ

PD784218A, 784218AY Subseries User’s Manual Hardware: U12970E

µµµµ

78K/IV Series User’s Manual Instructions: U10905E

FEATURES

Pin compatible with the mask ROM products

•

Flash memory: 128 KB (

•

256 KB (µPD78F4218A/78F4218AY)

Internal RAM: 8,192 bytes (µPD78F4216A/78F4216AY)

•

12,800 bytes (µPD78F4218A/78F4218AY)

Supply voltage: VDD = 1.9 to 5.5 V

•

PD78F4216A/78F4216AY)

µ

APPLICATIONS

Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment

Unless otherwise specified, references in this document to the

78F4218A, 78F4216AY, and 78F4218AY.

PD78F4218AY refer to the

µµµµ

PD78F4216A,

µµµµ

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. U14125EJ1V0DS00 (1st edition)
Date Published November 2000 N CP(K)
Printed in Japan

2000

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

ORDERING INFORMATION

Part Number Package Internal ROM (Bytes) Internal RAM (Bytes)

PD78F4216AGC-8EU 100-pin plastic LQFP

µ

(fine pitch) (14 × 14)

PD78F4216AGF-3BA 100-pin plastic QFP

µ

(14 × 20)

PD78F4218AGC-8EU 100-pin plastic LQFP

µ

(fine pitch) (14 × 14)

PD78F4218AGF-3BA 100-pin plastic QFP

µ

(14 × 20)

PD78F4216AYGC-8EU 100-pin plastic LQFP

µ

(fine pitch) (14 × 14)

128 K 8,192

128 K 8,192

256 K 12,800

256 K 12,800

128 K

8,192

PD78F4216AYGF-3BA 100-pin plastic QFP

µ

(14 × 20)

PD78F4218AYGC-8EU 100-pin plastic LQFP

µ

(fine pitch) (14 × 14)

PD78F4218AYGF-3BA 100-pin plastic QFP

µ

(14 × 20)

128 K

256 K 12,800

256 K 12,800

8,192

2

Data Sheet U14125EJ1V0DS00

78K/IV SERIES LINEUP

: Products in mass-production

: Products under development

Standard models

PD784026

µ

Enhanced
A/D converter,
16-bit timer, and
power management

ASSP models

PD784956A

µ

For DC inverter control

PD784908

µ

On-chip IEBus

PD784915

µ

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

TM

controller

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

2

Supports I

µ

µ

PD784038

Enhanced internal memory capacity
Pin-compatible with the PD784026

Supports multimaster I2C bus

µ

PD784216AY

µ

PD784216A

100-pin, enhanced I/O and
internal memory capacity

µ

PD784046

On-chip 10-bit A/D converter

µ

PD784938A

Enhanced functions of the

µ

PD784908, enhanced
internal memory capacity,
ROM correction added.

Supports multimaster I

µ

PD784928

µ

Enhanced functions
of the PD784915

C bus

PD784038Y

µ

PD784054

PD784928Y

µ

2

C bus

Supports multimaster I

µ

PD784225Y

µ

PD784225

µ

80-pin, ROM correction added

Supports multimaster I

µ

PD784218AY

µ

PD784218A

Enhanced internal memory
capacity, ROM correction added

µ

PD784967

Enhanced functions of the

µ

PD784938A, enhanced
I/O and internal memory
capacity.

2

C bus

2

C bus

PD784976

µ

On-chip VFD controller/driver

Data Sheet U14125EJ1V0DS00

3

µµµµ

OVERVIEW OF FUNCTIONS (1/2)

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Part Number

Item
Number of basic instruc t i ons (mnemonics) 113

General-purpose registers 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory

mapping)

Minimum instructi on execution time

Flash memory 128 KB 256 KBInternal

memory
Memory space 1 MB with program and data spaces combined

I/O ports

Pins with
additional
functions

Real-time output port 4 bits × 2 or 8 bits × 1
Timer/event counter

Serial interface

A/D converter 8-bit resolution × 8 channels
D/A converter 8-bit resolution × 2 channels

Note 1

RAM 8,192 bytes 12,800 bytes

Total 86
CMOS input 8
CMOS I/O 72
N-ch open-drain I/O 6
Pins with pull-up resistor 70
LED direct drive output 22
Middle-voltage pin 6

160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with

•

main system clock)

61

•

µ

Timer/event counter: Timer counter × 1 Pulse output
(16-bit) Capture/compare register × 2 • PPG output

Timer/event counter 1: Timer counter × 1 Pulse output
(8-bit) Compare register

Timer/event counter 2: Timer counter × 1 Pulse output
(8-bit) Compare register

Timer/event counter 5: Timer counter × 1 Pulse output
(8-bit) Compare register

Timer/event counter 6: Timer counter × 1 Pulse output
(8-bit) Compare register

Timer/event counter 7: Timer counter × 1 Pulse output
(8-bit) Compare register

Timer/event counter 8: Timer counter × 1 Pulse output
(8-bit) Compare register

UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generat or)

•

CSI (3-wire serial I / O , multimaster support i ng I

•

PD78F4216A,

µ

PD78F4216AY

µ

s (@fXT = 32.768 kHz operation with subsystem clock)

1

×

1

×

1

×

1

×

1

×

1

×

PD78F4218A,

µ

PD78F4218AY

µ

Square wave output

•

One-shot pulse output

•

PWM output

•

Square wave output

•

PWM output

•

Square wave output

•

PWM output

•

Square wave output

•

PWM output

•

Square wave output

•

PWM output

•

Square wave output

•

PWM output

•

Square wave output

•

2

Note 2

C bus

): 1 channel

Notes 1.

4

Pins with additional functions are included with the I/O pins.

PD78F4216AY, 78F4218AY only

2.

µ

Data Sheet U14125EJ1V0DS00

OVERVIEW OF FUNCTIONS (2/2)

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Item
Clock output

Buzzer output
Watch timer
Watchdog timer
Standby

Interrupt

Supply voltage
Package

Part Number

Selectable from f
Selectable from f

PD78F4216A,

µ

PD78F4216AY

µ

XX

, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, f

XX

/210, fXX/211, fXX/212, fXX/2

13

1 channel
1 channel

HALT/STOP/IDLE modes

•

In low power consumption m ode (wi th subsystem clock): HALT/IDLE modes

•

Hardware sources 29 (i nternal: 20, external: 9)
Software sources BRK instruction, BRKCS instruction, operand error
Non-maskable Internal: 1, external: 1
Maskable Internal: 19, external: 8

4 programmable priority lev el s

•

3 service modes: V ectored interrupt/macro serv ice/context switc hi ng

•

DD

V

= 1.9 to 5.5 V

100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)

PD78F4218A,

µ

PD78F4218AY

µ

XT

Data Sheet U14125EJ1V0DS00

5

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

CONTENTS

1. DIFFERENCES AMONG MODELS IN

SUBSERIES.............................................................................................................................................7

2. PIN CONFIGURATION (TOP VIEW)...................................................................................................8

3. BLOCK DIAGRAM...............................................................................................................................11

4. PIN FUNCTIONS..................................................................................................................................12

4.1 Port Pins .....................................................................................................................................12

4.2 Non-Port Pins .............................................................................................................................14

4.3 Pin I/O Circuits and Recommended Connections of Unused Pins .......................................16

5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)................................................................20

6. PROGRAMMING FLASH MEMORY.....................................................................................................22

6.1 Selecting Communication Mode ..............................................................................................22

6.2 Flash Memory Programming Function ....................................................................................23

6.3 Connecting Flashpro ll and Flashpro lll...................................................................................24

7. ELECTRICAL SPECIFICATIONS ........................................................................................................25

PD784216A/784216AY, 784218A/784218AY

µµµµ

8. PACKAGE DRAWINGS.......................................................................................................................47

9. RECOMMENDED SOLDERING CONDITIONS..................................................................................49

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................50

APPENDIX B. RELATED DOCUMENTS................................................................................................53

6

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

1. DIFFERENCES AMONG MODELS IN

PD784216A/784216AY, 784218A/784218AY SUBSERIES

µµµµ

The only difference among the µPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal

memory capacity.

The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus

control function.

The µPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory

instead of the mask ROM of the above models.

These differences are summarized in Table 1-1.

Table 1-1. Differences Among Models in

PD784214A,

Part Number

Item
Internal ROM 96 KB

Internal RAM 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes 8,192

Internal memory size
switching register
(IMS)

ROM correction Not provided Provided Not

External access status
function

Supply voltage VDD = 1.8 to 5.5 V VDD = 1.9 to 5.5 V
Electrical

specifications
Recommended

soldering conditions
EXA pin Not provided Provided Not

TEST pin Provided Not provided
VPP pin Not provided Provided

µ

PD784214AY

µ

(Mask
ROM)

Not provided

Not provided Provided Not

Refer to the data sheet for each device.

PD784215A,

µ

PD784215AY

µ

128 KB (Mask ROM) 192 KB

PD784216A/784216AY, 784218A/784218AY Subseries

µµµµ

µ

PD784216A,

µ

PD784216AY

µ

PD784217A,

µ

PD784217AY

µ

(Mask
ROM)

PD784218A,

µ

PD784218AY

µ

256 KB
(Mask
ROM)

PD78F4216A,

µ

PD78F4216AY

128 KB
(Flash
memory)

bytes
Provided

provided

provided

provided

µ

256 KB
(Flash
memory)

12,800
bytes

Note

Provided

Provided

Provided

µ

PD78F4218A,

PD78F4218AY

The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

Note

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U14125EJ1V0DS00

7

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

2. PIN CONFIGURATION (TOP VIEW)

100-pin plastic LQFP (fine pitch) (14

••••

PD78F4216AGC-8EU,

µµµµ

P95

P94

100 76

P120/RTP0
P121/RTP1
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7

V

X2
X1

V
XT2
XT1

RESET
P00/INTP0
P01/INTP1

P02/INTP2/NMI

P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6

Note 2

AV

DD

AV

REF0

P10/ANI0

DD

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26 504948474645444342414039383736353433323130292827

14)

××××

PD78F4218AGC-8EU,

µµµµ

Note 5

Note 1

P91

P90

PP

V

P37/EXA

P36/TI01

P35/TI00

P93

P92

PD78F4216AYGC-8EU,

µµµµ

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P103/TI8/TO8

P102/TI7/TO7

P101/TI6/TO6

P100/TI5/TO5

VDDP67/ASTB

PD78F4218AYGC-8EU

µµµµ

P66/WAIT

P65/WR

P64/RD

P63/A19

7778798081828384858687888990919293949596979899

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P62/A18
P61/A17
P60/A16
V
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3

SS

Notes 1.

8

REF1

AV

P130/ANO0

P131/ANO1

P70/RxD2/SI2

P20/RxD1/SI1

P71/TxD2/SO2

P72/ASCK2/SCK2

Note 4

P23/PCL

P24/BUZ

P21/TxD1/SO1

P22/ASCK1/SCK1

Note 4

P80/A0

P26/SO0

P25/SI0/SDA0

P27/SCK0/SCL0

P81/A1

P82/A2

P11/ANI1

Connect the V

Note 3

SS

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

PP

pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the

AV

P16/ANI6

P17/ANI7

VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.

Connect the AVDD pin to VDD.

2.

Connect the AVSS pin to VSS.

3.

The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.

4.

The EXA pin is available in the µPD78F4218A, 78F4218AY only.

5.

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

100-pin plastic QFP (14

••••

PD78F4216AGF-3BA,

µµµµ

P60/A16
P61/A17
P62/A18
P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

V

DD

P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8

P30/TO0
P31/TO1
P32/TO2

P33/TI1

P34/TI2
P35/TI00
P36/TI01

Note 5

P37/EXA

Note 1

V

PP

P90
P91
P92
P93
P94

P95
P120/RTP0
P121/RTP1

20)

××××

PD78F4218AGF-3BA,

µµµµ

VSSP57/A15

P56/A14

P55/A13

P54/A12

P53/A11

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 50494847464544434241403938373635343332

PD78F4216AYGF-3BA,

µµµµ

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

PD78F4218AYGF-3BA

µµµµ

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

81828384858687888990919293949596979899

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P84/A4
P83/A3
P82/A2
P81/A1
P80/A0
P27/SCK0/SCL0
P26/SO0
P25/SI0/SDA0
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AV

REF1

P131/ANO1
P130/ANO0

Note 3

AV

SS

P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AV

REF0

Note 2

AV

DD

Note 4

Note 4

Notes 1.

X2

X1

SS

V

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

P02/INTP2/NMI

Connect the V

DD

V

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

PP

pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the
VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.

Connect the AVDD pin to VDD.

2.

Connect the AVSS pin to VSS.

3.

The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.

4.

The EXA pin is available in the µPD78F4218A, 78F4218AY only.

5.

Data Sheet U14125EJ1V0DS00

9

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

A0 to A19: Address Bus P120 to P127: Port 12
AD0 to AD7: Address/Data Bus P130, P131: Port 13
ANI0 to ANI7: Analog Input PCL: Programmable Clock
ANO0, ANO1: Analog Output RD: Read Strobe
ASCK1, ASCK2: Asynchronous Serial Clock RESET: Reset
ASTB: Address Strobe RTP0 to RTP7: Real-time Output Port
AVDD: Analog Power Supply RxD1, RxD2: Receive Data

REF0

AV
AVSS: Analog Ground SCL0
BUZ: Buzzer Clock SDA0
EXA
INTP0 to INTP6: Interrupt from Peripherals SO0 to SO2: Serial Output
NMI: Non-maskable Interrupt TI00, TI01,
P00 to P06: Port 0 TI1, TI2, TI5 to TI8: Timer Input
P10 to P17: Port 1 TO0 to TO2, TO5 to TO8: Timer Output
P20 to P27: Port 2 TxD1, TxD2: Transmit Data
P30 to P37: Port 3 VDD: Power Supply
P40 to P47: Port 4 VPP: Programming Power Supply
P50 to P57: Port 5 VSS: Ground
P60 to P67: Port 6 WAIT: Wait
P70 to P72: Port 7 WR: Write Strobe
P80 to P87: Port 8 X1, X2: Crystal (Main System Clock)
P90 to P95: Port 9 XT1, XT2: Crystal (Subsystem Clock)
P100 to P103: Port 10

REF1

, AV

Note 2

: Analog Reference Voltage SCK0 to SCK2: Serial Clock

Note 1

: Serial Clock

Note 1

: Serial Data

: External Access Status Output SI0 to SI2: Serial Input

Notes 1.

The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.

The EXA pin is available in the µPD78F4218A, 78F4218AY only.

2.

10

Data Sheet U14125EJ1V0DS00

3. BLOCK DIAGRAM

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP6

TI00
TI01
TO0

TI1

TO1

TI2

TO2

TI5/TO5

TI6/TO6

TI7/TO7

TI8/TO8

RTP0 to RTP7

NMI/INTP2

ANO0
ANO1

REF1

AV

AV

SS

P03/INTP3

ANI0 to ANI7

AV

REF0

AV

DD

AV

SS

PCL

BUZ

Programmable
interrupt
controller

Timer/event

counter

(16 bits)

Timer/event

counter 1

(8 bits)

Timer/event

counter 2

(8 bits)

Timer/event

counter 5

(8 bits)

Timer/event

counter 6

(8 bits)

Timer/event

counter 7

(8 bits)

Timer/event

counter 8

(8 bits)

Watch timer

Watchdog timer

Real-time
output port

D/A
converter

A/D
converter

Clock output
control

Buzzer output

78K/IV

CPU core

RAM

Flash

memory

UART/IOE1
Baud-rate
generator

UART/IOE2
Baud-rate
generator

Clocked
serial
interface

Bus I/F

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8

Port 9
Port 10
Port 12
Port 13

System control

RxD1/SI1
TxD1/SO1

ASCK1/SCK1
RxD2/SI2

TxD2/SO2
ASCK2/SCK2

SI0/SDA0

Note 1

SO0
SCK0/SCL0

AD0 to AD7
A0 to A7

A8 to A15
A16 to A19

RD
WR
WAIT
ASTB

Note 2

EXA
P00 to P06

P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127
P130, P131

RESET
X1
X2
XT1
XT2

V

DD

V

SS

V

PP

Note 1

Notes 1.

2

This function supports the I

The EXA pin is available in the µPD78F4218A, 78F4218AY only.

2.

C bus interface and is available in the µPD78F4216AY, 78F4218AY only.

Data Sheet U14125EJ1V0DS00

11

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4. PIN FUNCTIONS

4.1 Port Pins (1/2)

Pin Name I / O Alternate Function Function
P00 INTP0
P01 INTP1
P02 INTP2/NMI
P03 INTP3
P04 INTP4
P05 INTP5
P06
P10 to P17 Input ANI0 to ANI7 Port 1 (P1):

P20 RxD1/SI1
P21 TxD1/SO1
P22 ASCK1/SCK1
P23 PCL
P24 BUZ
P25 SI0/SDA0
P26 SO0
P27
P30 TO0
P31 TO1
P32 TO2
P33 TI1
P34 TI2
P35 TI00
P36 TI01
P37
P40 to P47 I/O AD0 to AD7 Port 4 (P4):

P50 to P57 I/O A8 to A15 Port 5 (P5):

I/O

I/O

I/O

INTP6

SCK0/SCL0

Note 2

EXA

Note 1

Note 1

Port 0 (P0):

7-bit I/O port

•

Input/output can be spec i f i ed i n 1-bi t units.

•

Whether specifying input m ode or output mode, an on-chip pull-up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

8-bit input only port

•

Port 2 (P2):

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

Port 3 (P3):

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

When used as an input port, an on-chip pull-up resistor c an be

•

specified by means of s oftware.

LEDs can be driven directly.

•

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

When used as an input port, an on-chip pull -up resistor can be

•

specified by means of s oftware.

LEDs can be driven directly.

•

Notes 1.

12

This SDA0 and SCL0 are available in the

This function is available in the µPD78F4218A, 784218AY only.

2.

Data Sheet U14125EJ1V0DS00

PD78F4216AY, 78F4218AY only.

µ

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.1 Port Pins (2/2)

Pin Name I / O Alternate Function Function
P60 A16
P61 A17
P62 A18
P63 A19
P64 RD
P65 WR
P66 WAIT
P67
P70 RxD2/SI2
P71 TxD2/SO2
P72

P80 to P87 I/O A0 to A7 Port 8 (P8):

P90 to P95 I/O

P100 TI5/TO5
P101 TI6/TO6
P102 TI7/TO7
P103
P120 to P127 I/O RTP0 to RTP7 P ort 12 (P12):

P130, P131 I/O ANO0, ANO1 Port 13 (P13):

I/O

I/O

I/O

ASTB

ASCK2/SCK2

−

TI8/TO8

Port 6 (P6):

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

When used as an input port, an on-chip pull -up resistor can be

•

specified by means of s oftware.

Port 7 (P7):

3-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

The interrupt control flag (KRIF) is set t o 1 when a falling edge is

•

detected at a pin of this port .

Port 9 (P9):

N-ch open-drain middle-voltage I/O port

•

6-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

LEDs can be driven directly.

•

Port 10 (P10):

4-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

8-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Whether specifying input mode or output mode, an on-c hi p pul l -up

•

resistor can be specif i ed i n 1-bi t units by means of sof tware.

2-bit I/O port

•

Input/output can be specified in 1-bit uni t s.

•

Data Sheet U14125EJ1V0DS00

13

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.2

Non-Port Pins (1/2)

Pin Name I / O Alternate Function Function
TI00 P35 External count c l ock input to 16-bit timer c ounter
TI01 P36 Capture trigger signal input to capture/compare register 00
TI1 P33 External count c l ock input to 8-bit timer c ounter 1
TI2 P34 External count c l ock input to 8-bit timer c ounter 2
TI5 P100/TO5 External count clock input t o 8-bi t timer counter 5
TI6 P101/TO6 External count clock input t o 8-bi t timer counter 6
TI7 P102/TO7 External count clock input t o 8-bi t timer counter 7
TI8
TO0 P30 16-bit timer output (shared by 14-bit PWM output)
TO1 P31
TO2 P32
TO5 P100/TI5
TO6 P101/TI6
TO7 P102/TI7
TO8
RxD1 P20/SI1 Serial data input (UART1)
RxD2
TxD1 P21/SO1 Serial data output (UART1)
TxD2
ASCK1 P22/SCK1 Baud rate clock input (UA RT1)
ASCK2
SI0 P25/SDA0
SI1 P20/RxD1 Serial data input (3-wi re serial I/O 1)
SI2
SO0 P26 Serial data output (3-wire s eri al I/O 0)
SO1 P21/TxD1 S eri al data output (3-wire serial I/O 1)
SO2

Note

SDA0
SCK0 P27/SCL0
SCK1 P22/ASCK1 S eri al c l ock input/output (3-wire serial I/O 1)
SCK2 P72/ASCK2 S eri al c l ock input/output (3-wire serial I/O 2)

Note

SCL0
NMI P02/INTP2 Non-maskable interrupt request input
INTP0 P00
INTP1 P01
INTP2 P02/NMI
INTP3 P03
INTP4 P04
INTP5 P05
INTP6

Input

Output

Input

Output

Input

Input

Output

I/O

Input

P103/TO8 External count clock input t o 8-bi t timer counter 8

8-bit timer output (shared by 8-bi t PWM output)

P103/TI8

P70/SI2 Serial data input (UA RT2)

P71/SO2 Serial data output (UA RT2)

P72/SCK2 Baud rate cl ock input (UART2)

Note

P70/RxD2 Serial data input (3-wire serial I /O 2)

P71/TxD2 S eri al data output (3-wire serial I/O 2)
P25/SI0 Serial data input/output (I2C bus)

Note

P27/SCK0 Serial c l ock input/output (I

P06

Serial data input (3-wire serial I /O 0)

Serial clock input/ output (3-wire serial I/O 0)

2

C bus)

External interrupt request i nput

14

This function is available in the

Note

PD78F4216AY, 78F4218AY only.

µ

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.2 Non-Port Pins (2/2)

Pin Name I / O Alternate Function Function
PCL Output P23 Clock output (for trimming main system clock and subsystem clock)
BUZ Output P24 Buzzer out put
RTP0 to RTP7 Output P120 to P127 Real-time output port that out put s data in synchronizati on wi t h

trigger
AD0 to AD7 I/O P40 to P47 Lower address/data bus for expanding memory externally
A0 to A7 P80 to P87 Lower addres s bus for expanding memory external l y
A8 to A15 P50 to P57 Mi ddl e address bus for expanding memory ex t ernal l y
A16 to A19
RD P64 Strobe signal output f or readi ng from external memory
WR
WAIT Input P66 Wait insertion at external memory access
ASTB Output P67 Strobe output that external l y latches address inform at i on output to

Note

EXA
RESET Input
X1 Input
X2
XT1 Input
XT2
ANI0 to ANI7 Input P10 t o P17 A/D converter analog input
ANO0, ANO1 Output P130, P131 D/A converter analog output

REF0

AV

REF1

AV

DD

AV

SS

AV

DD

V

SS

V

PP

V

Output

P60 to P63 Higher addres s bus for expanding memory ext ernal l y

Output

P65 Strobe signal output for writing to external memory

ports 4 through 6 and 8 to access external memory

Output P37 Status signal output at external memory access

−

−

System reset input

Connecting crystal res onator for main system clock oscillation

−

−

Connecting crystal res onator for subsystem clock oscillation

−

−−

A/D converter reference v ol t age i nput

D/A converter reference v ol t age i nput

A/D converter positi ve power supply. Connect to VDD.

GND for A/D converter and D/A converter. Connect to VSS.

Positive power supply

GND

Flash memory programming mode setting.

Applying high-voltage for program wri te/verify. Connect t hi s pin to

SS

directly or via a pull-down res i s tor in normal operation mode.

V

Connect the V

PP

pin to VSS via a pull-down resistor in a system in
which the on-chip flash mem ory is written while mounted on the
target board. For the pull-down connect i on, it is recommended to
use a resistor with a resistance ranging from 470 Ω to 10 kΩ.

The EXA pin is available in the

Note

PD78F4218A, 78F4218AY only.

µ

Data Sheet U14125EJ1V0DS00

15

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 4-1.
For each type of input/output circuit, refer to Figure 4-1.

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pi ns
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3 to P06/INTP6
P10/ANI0 to P17/ANI7 9 Input Connect to VSS or V
P20/RxD1/SI1 10-K
P21/TxD1/SO1 10-L
P22/ASCK1/SCK1 10-K
P23/PCL
P24/BUZ
P25/SI0/SDA0

Note 1

8-N I/O Input: Independently connect to V

Output: Leave open

I/O Input: Independently connect t o V

Output: Leave open

10-L

10-K

DD

SS

via a resistor

SS

via a resistor

P26/SO0 10-L

Note 2

Note 1

10-K

12-E
5-A

8-N

P27/SCK0/SCL0
P30/TO0 to P32/TO2 12-E

P33/TI1, P34/TI2 8-N
P35/TI00, P36/TI01 10-M
P37/EXA

P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60/A16 to P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2 8-N
P71/TxD2/SO2 10-M
P72/ASCK2/SCK2 8-N
P80/A0 to P87/A7 12-E
P90 to P95 13-D
P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P120/RTP0 to P127/RTP7 12-E
P130/ANO0, P131/ANO1 12-F

Notes 1.

16

The SDA0 and SCL0 pins are available in the

The EXA pin is available in the

2.

PD78F4218A, 78F4218AY only.

µ

Data Sheet U14125EJ1V0DS00

PD78F4216AY, 78F4218AY only.

µ

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pi ns
RESET 2-G
XT1

16

XT2

REF0

AV

REF1

AV

DD

AV

SS

AV

PP

V

−

Input

−

−

Connect to V

SS

Leave open
Connect to V
Connect to V

Connect to V
Connect this pin to V

operation mode. Connect the V

SS

DD

SS

SS

directly or via a pull-down res i s t in normal

PP

pin to VSS via a pull-down
resistor in a system in which the on-chip flash memory is written
while mounted on the target board.
For the pull-down connection, it i s recommended to use a resistor
with a resistance ranging from 470 Ω to 10 kΩ.

Remark

Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U14125EJ1V0DS00

17

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Figure 4-1. Types of Pin I/O Circuits (1/2)

Type 2-G

IN

Schmitt-triggered input with hysteresis characteristics

Type 5-A

Pullup
enable

Data

DD

V

P-ch

DD

V

P-ch

IN/OUT

Output
disable

N-ch

Input
enable

Type 10-K

Pullup

enable

Data

Open drain

Output disable

Type 10-L

Pullup

enable

Data

Open drain

Output disable

V

DD

P-ch

DD

V

P-ch

IN/OUT

N-ch

V

DD

P-ch

DD

V

P-ch

IN/OUT

N-ch

V

SS

Type 8-N

Pullup
enable

Data

Output
disable

Type 9

IN

P-ch

N-ch

(Threshold voltage)

DD

V

P-ch

N-ch

REF

V

V

DD

P-ch

Comparator

+
–

IN/OUT

Input
enable

Type 10-M

Pullup

enable

Data

Output disable

Type 12-E

Pullup
enable

Data

Output
disable

Input
enable

Analog output
voltage

P-ch

N-ch

V

DD

P-ch

V

DD

P-ch

IN/OUT

N-ch

V

SS

V

DD

P-ch

DD

V

P-ch

IN/OUT

N-ch

18

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Figure 4-1. Types of Pin I/O Circuits (2/2)

Type 12-F

Data

Output

disable

Input

enable

Type 13-D

Data

Output disable

Analog output
voltage

RD

Type 16

DD

V

P-ch

IN/OUT

N-ch

V

SS

P-ch
N-ch

N-ch

V

P-ch

V

SS

IN/OUT

DD

XT1 XT2

Feedback
cut-off

P-ch

Middle-voltage input buffer

Data Sheet U14125EJ1V0DS00

19

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)

IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.
By setting this register, the internal memory of the µPD78F4218AY can be mapped identically to that of a mask ROM
version with a different internal memory (ROM and RAM) capacity.

IMS is set with an 8-bit memory manipulation instruction.

RESET input sets IMS to FFH.

(1)

PD78F4216A, 78F4216AY

µµµµ

Figure 5-1. Internal Memory Size Switching Register (IMS) Format

Address: 0FFFCH After reset: FFH W

76543210

IMS 1 1 ROM1 ROM0 1 1 RAM1 RAM0

ROM1 ROM0 Internal ROM Capacity Selection

0 0 48 KB
0 1 64 KB
1 0 96 KB
1 1 128 KB

RAM1 RAM0 Peripheral RAM Capacity Selection

0 0 3,072 bytes
0 1 4,608 bytes
1 0 6,114 bytes
1 1 7,680 bytes

Caution IMS is not provided on the mask ROM versions (

PD784214A, 784215A, 784216A,

µµµµ

PD784214AY,

µµµµ

784215AY, and 784216AY).

Table 5-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM
versions.

Table 5-1. Setting Value of Internal Memory Size Switching Register (IMS)

Target Mask ROM Version IMS Setting Value

PD784214A, 784214AY ECH

µ

PD784215A, 784215AY FDH

µ

PD784216A, 784216AY FFH

µ

20

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

(2)

PD78F4218A, 78F4218AY

µµµµ

Figure 5-2. Internal Memory Size Switching Register (IMS) Format

Address: 0FFFCH After reset: FFH W

76543210

IMS 1 1 ROM1 ROM0 1 1 RAM1 RAM0

ROM1 ROM0 Internal ROM Capacity Selection

0 0 64 KB
0 1 128 KB
1 0 192 KB
1 1 256 KB

RAM1 RAM0 Peripheral RAM Capacity Selection

0 0 3,072 bytes
0 1 6,656 bytes
1 0 7,168 bytes
1 1 12,288 bytes

Caution IMS is not provided on the mask ROM versions (

PD784217A, 784218A, 784217AY, and

µµµµ

784218AY).

Table 5-2 shows the IMS setting values to make the memory mapping the same as that of the mask ROM

versions.

Table 5-2. Setting Value of Internal Memory Size Switching Register (IMS)

Target Mask ROM Version IMS Setting Value

PD784217A, 784217AY EFH

µ

PD784218A, 784218AY FFH

µ

Data Sheet U14125EJ1V0DS00

21

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

6. PROGRAMMING FLASH MEMORY

The flash memory can be written with the µPD78F4218AY mounted on the target board (on-board). To do so,
connect a dedicated flash programmer (Flashpro II (part number: FL-PR2), Flashpro III (part number: FL-PR3, PG­FP3) to the host machine and target system.

Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro II or
Flashpro III.

Remark

FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.

6.1 Selecting Communication Mode

To write the flash memory, use Flashpro II and Flashpro III by serial communication. Select a serial
communication mode from those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is
selected by the number of VPP pulses shown in Table 6-1.

Table 6-1. Communication Modes

Communication

Mode

3-wire serial I/O 3

Handshake

Note 2

Number of

Channels

1

Pins Used Number of

SCK0/P27/SCL0
SO0/P26
SI0/P25/SDA0

SCK1/ASCK1/P22
SO1/TxD1/P21
SI1/RxD1/P20

SCK2/ASCK2/P72
SO2/TxD2/P71
SI2/RxD2/P70

SCK0/P27/SCL0
SO0/P26
SI0/P25/SDA0
P24/BUZ

TxD1/SO1/P21
RxD1/SI1/P20

TxD2/SO2/P71
RxD2/SI2/P70

Note 1

Note 1

Note 1

Note 1

0

1

2

3

8UART 2

9

PP

V

Pulses

Notes 1.

The SCL0 and SDA0 pins are available in the
This made is available in the µPD78F4216A, 78F4216AY (other than I, K, E standard)

2.

PD78F4216AY, 78F4218AY only.

µ

This made is available in the µPD78F4218A, 78F4218AY (other than I standard)

Caution Be sure to select a communication mode with the number of V

22

Data Sheet U14125EJ1V0DS00

PP

pulses shown in Table 6-1.

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Figure 6-1. Communication Mode Selecting Format

VPP pulses

10 V

V

V

RESET

PP

DD

V

SS

V

DD

V

SS

12 n

Flash programming mode

6.2 Flash Memory Programming Function

The flash memory is written by transferring or receiving commands and data in a selected communication mode.

The major functions of flash memory programming are listed in Table 6-2.

Table 6-2. Major Functions of Flash Memory Programming

Function Description
Batch erasure Erases all cont ents of memory.
Block erasure Erases contents of specified m em ory block with one memory bloc k

consisting of 16 KB .
Batch blank check Checks erased status of entire memory.
Block blank check Checks erased status of specified block.
Data write Writes flash memory based on write start address and number of

data to be written (in bytes ).
Batch verify Compares all c ont ents of memory with input dat a.
Block verify Compares contents of specifi ed m em ory block with input data.

Data Sheet U14125EJ1V0DS00

23

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

6.3 Connecting Flashpro II and Flashpro III

The Flashpro II, Flashpro III and µPD78F4218AY are connected differently depending on the selected
communication mode (3-wire serial I/O or UART). Figures 6-2 to 6-4 show the connections in the respective
communication modes.

Figure 6-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode

V

PP

V

DD

RESET

Flashpro ll,
Flashpro lll

SCK0 or SCK1 or SCK2

SI0 or SI1 or SI2

SO0 or SO1 or SO2

SS

V

µ

PD78F4218AY

Figure 6-3. Connection of Flashpro III in Handshake Mode

VPP

VDD

RESET

SCK0

Flashpro lll PD78F4218AY

SI0

SO0

P24

VSS

µ

Figure 6-4. Connection of Flashpro II and Flashpro III in UART Mode

VPP
VDD

Flashpro ll,
Flashpro lll

RESET

RxD1 or RxD2

µ

PD78F4218AY

24

TxD1 or TxD2

SS

V

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

7. ELECTRICAL SPECIFICATIONS

A

= 25

Absolute Maximum Ratings (T

Parameter Symbol Conditions Ratings Unit

DD

AV
AV

V
AV
AV

V
V
V

T

DD

SS

REF0

A/D converter reference v ol t age i nput

REF1

D/A converter reference v ol t age i nput

I1

Other than P90 to P95

I2

P90 to P95 N-ch open drain

I3

VPP pin for programming

AN

Analog input pin AVSS − 0.3 to AV

O

OL

Per pin 15 mA
Total of P2, P4 to P8 75 mA
Total of P0, P3, P9, P10, P12, P13 75 mA
Total of all pins 100 mA

OH

Per pin
Total of all pins

A

stg

Supply voltage

Input voltage

Analog input voltage V
Output voltage V
Output current, low I

Operating ambient
temperature

Storage temperature T

C)

°°°°

0.3 to +6.5 V

−

DD

0.3 to V

−

0.3 to V

−

0.3 to VDD + 0.3 V

−

0.3 to VDD + 0.3 V

−

0.3 to VDD + 0.3 V

−

−

−

0.3 to V

−

−

+ 0.3 V

SS

+ 0.3 V

0.3 to +12 V

0.3 to +10.5 V

DD

+ 0.3 V

10 mAOutput current, high I

−

50 mA

−

40 to +85

−

65 to +125

REF0

+ 0.3 V

C

°

C

°

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.

Data Sheet U14125EJ1V0DS00

25

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Operating Conditions

A

Operating ambient temperature (T

•

Supply voltage and clock cycle time: See Figure 7-1

•

Operating voltage with subsystem clock operation: VDD = 1.9 to 5.5 V

•

): −40 to +85°C

Figure 7-1. Supply Voltage and Clock Cycle Time (CPU Clock Frequency: f

10,000

8,000

500

400

[ns]

CYK

320
300

Clock cycle time t

200
160

Guaranteed

operating range

CPU

)

100

80

0

01231.9 2.7 4.5 5.5

Supply voltage [V]

Capacitance (TA = 25

Parameter Symbol Conditions MIN. TYP. MAX. Unit

C, VDD = VSS = 0 V)

°°°°

I

f = 1 MHz
Unmeasured pins
returned to 0 V.

O

IO

Other than Port 9 15 pFInput capacitance C
Port 9 20 pF
Other than Port 9 15 pFOutput capacitance C
Port 9 20 pF
Other than Port 9 15 pFI/O capacitance C
Port 9 20 pF

456

26

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Main System Clock Oscillator Characteristics (TA =

Resonator Recom m ended Ci rcuit Parameter Conditions MIN. TYP. MAX. Unit
Ceramic

resonator
or crystal
resonator

External
clock

X2 X1 V

X2 X1

PD74HCU04

µ

SS

Oscillation frequency

X

(f

)

X1 input frequency (fX)

X1 input high-/low-

WXH

level width (t
X1 input rising/falling

XR

time (t

, tXF)

WXL

, t

40 to +85

−−−−

4.5 V ≤ VDD ≤ 5.5 V 2 12.5

2.7 V ≤ VDD < 4.5 V 2 6.25

2.0 V ≤ VDD < 2.7 V 2 3.125

1.9 V ≤ V

4.5 V ≤ VDD ≤ 5.5 V 2 12.5

2.7 V ≤ VDD < 4.5 V 2 6.25

2.0 V ≤ VDD < 2.7 V 2 3.125

1.9 V ≤ V

)

4.5 V ≤ VDD ≤ 5.5 V 0 5

2.7 V ≤ VDD < 4.5 V 0 10

2.0 V ≤ VDD < 2.7 V 0 20

1.9 V ≤ V

C)

°°°°

DD

< 2.0 V 2 2

DD

< 2.0 V 2 2

15 250 ns

DD

< 2.0 V 0 30

MHz

MHz

ns

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with other signal lines.

••••

Do not route the wiring near a signal line through which a high fluctuating current flows.

••••

Always make the ground point of the oscillator capacitor the same potential as VSS.

••••

Do not ground the capacitor to a ground pattern through which a high current flows.

••••

Do not fetch signals from the oscillator.

••••

2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched back to the main system clock after the oscillation
stabilization time is secured by the program.

Remark

For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14125EJ1V0DS00

27

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Subsystem Clock Oscillator Characteristics (TA =

Resonator Recom m ended Ci rcuit P aram et er Conditions MIN. TYP. MAX. Unit
Crystal

resonator

External
clock

Time required to stabilize oscillation after applying supply voltage (V

Note

VSSXT2 XT1

XT2 XT1

PD74HCU04

µ

Oscillation frequency

XT

(f

)

Oscillation
stabilization time

XT1 input frequency

XT

(f

)

XT1 input high-/low­level width (t

XTH

Note

XTL

, t

40 to +85

−−−−

4.5 V ≤ VDD ≤ 5.5 V 1.2 2

1.9 V ≤ VDD < 4.5 V 10

)

C)

°°°°

32 32.768 35 kHz

32 35 kHz

14.3 15.6

DD

).

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with other signal lines.

••••

Do not route the wiring near a signal line through which a high fluctuating current flows.

••••

Always make the ground point of the oscillator capacitor the same potential as V

••••

Do not ground the capacitor to a ground pattern through which a high current flows.

••••

Do not fetch signals from the oscillator.

••••

SS

.

s

s

µ

Remark

2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.

For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.

28

Data Sheet U14125EJ1V0DS00

µµµµ

,

,

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, low

Input voltage, high

Output voltage, low

Output voltage, high V

Input leakage current, high

Output leakage current, low I
Output leakage current, high I

40 to +85

−−−−

IL1

V

IL2

V

IL3

V

IL4

V

IL5

V

IL6

V

IH1

V

IH2

V

IH3

IH4

V

IH5

V

IH6

V

OL1

V

OL2

V

OH1

LIL1

I

LIL2

I

LIH1

I

LIH2

I

LIH3VIN

I

LOL1VOUT

LOH1VOUT

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (1/3)

°°°°

Note 1

P00 to P06, P20, P22, P 33,
P34, P70, P72,

2.2 V ≤ VDD ≤ 5.5 V 0 0.3V

DD

1.9 V ≤ V

< 2.2 V 0 0.2V

2.2 V ≤ VDD ≤ 5.5 V 0 0.2V

1.9 V ≤ V

DD

< 2.2 V 0 0.15V

P100 to P103, RESET
P90 to P95

(N-ch open drain)
P10 to P17, P130, P131

X1, X2, XT1, XT2

P25, P27

Note 1

P00 to P06, P20, P22, P 33,
P34, P70, P72,

2.2 V ≤ VDD ≤ 5.5 V 0 0.3V

1.9 V ≤ V

DD

< 2.2 V 0 0.2V

2.2 V ≤ VDD ≤ 5.5 V 0 0.3V

1.9 V ≤ V

DD

< 2.2 V 0 0.2V

2.2 V ≤ VDD ≤ 5.5 V 0 0.2V

1.9 V ≤ V

DD

< 2.2 V 0 0.1V

2.2 V ≤ VDD ≤ 5.5 V 0 0.3V

1.9 V ≤ V

2.2 V ≤ VDD ≤ 5.5 V 0.7V

1.9 V ≤ V

2.2 V ≤ VDD ≤ 5.5 V 0.8V

1.9 V ≤ V

DD

< 2.2 V 0 0.2V

DD

DD

< 2.2 V 0.8V

DD

< 2.2 V 0.85V

DD

DD

DD

P100 to P103, RESET
P90 to P95

(N-ch open drain)
P10 to P17, P130, P131

X1, X2, XT1, XT2

P25, P27

For pins other than
P40 to P47, P50 to P57,

Note 2

OL

= 1.6 mA

P90 to P95 I
P40 to P47, P50 to P57

OL

I

= 8 mA
P90 to P95 IOL = 15 mA
IOL = 400 µA
IOH = −1 mA
IOL = −100 µA

Note 2

Note 2

Note 2

VIN = 0 V

2.2 V ≤ VDD ≤ 5.5 V 0.7V

1.9 V ≤ V

DD

< 2.2 V 0.8V

2.2 V ≤ VDD ≤ 5.5 V 0.7V

1.9 V ≤ V

DD

< 2.2 V 0.8V

2.2 V ≤ VDD ≤ 5.5 V 0.8V

1.9 V ≤ V

DD

< 2.2 V 0.85V

2.2 V ≤ VDD ≤ 5.5 V 0.7V

1.9 V ≤ V

DD

< 2.2 V 0.8V

4.5 V ≤ VDD ≤ 5.5 V 0.4 V

Note 1

4.5 V ≤ VDD ≤ 5.5 V 1.0 V

Note 2

4.5 V ≤ VDD ≤ 5.5 V 0.8 2.0 V

4.5 V ≤ VDD ≤ 5.5 V V

Except X1, X2, XT1

DD

DD

DD

DD

DD

DD

DD

DD

DD

1.0 V

−

DD

V

0.5 V

−

XT2
X1, X2, XT1, XT2

VIN = V

DD

Except X1, X2, XT1
XT2

X1, X2, XT1, XT2 20

= 12 V (N-ch open drain) P90 to P95 20

= 0 V

DD

= V

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

V

DD

V

DD

V

DD

V

12V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

0.5 V

3

−

20

−

3

3

−

3

V

V

V

V

V

V

V

V

V

V

V

V

AInput leakage current, low

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

Notes 1.

P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127
Per pin

2.

Data Sheet U14125EJ1V0DS00

29

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (TA =

(1)

PD78F4216A, 78F4216AY

µµµµ

40 to +85

−−−−

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (2/3)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply voltage

DD1

I

DD2

I

Operation
mode

HALT mode

fXX = 12.5 MHz, VDD = 5.0 V ±10% 17 40 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 5 17 mA

XX

f

= 2 MHz, VDD = 2.0 V ±5% 2 10 mA
fXX = 12.5 MHz, VDD = 5.0 V ±10% 6 20 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 2 10 mA

XX

f

= 2 MHz, VDD = 2.0 V ±5% 0.4 7 mA

DD3

I

IDLE mode

fXX = 12.5 MHz, VDD = 5.0 V ±10% 1 3 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 0.5 1.3 mA

XX

f

= 2 MHz, VDD = 2.0 V ±5% 0.3 0.9 mA

I

DD4

Operation

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 130 500
fXX = 32 kHz, VDD = 3.0 V ±10% 90 350
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 80 300
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 70 250

DD5

I

HALT

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 60 200
fXX = 32 kHz, VDD = 3.0 V ±10% 20 160
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 15 120
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 10 100

DD6

I

IDLE

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 50 190
fXX = 32 kHz, VDD = 3.0 V ±10% 15 150
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 12 110
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 7 90

Data retention voltage V

DDDR

HALT, IDLE modes 1.9 5.5 V

DDDR

STOP mode

VDD = 2.0 V ±5% 2 10

DD

V

= 5.0 V ±10% 10 50

Pull-up resistor RLVIN = 0 V 10 30 100 k

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

AData retention current I

µ

A

µ

Ω

Note

Remark

30

When main system clock is stopped and subsystem clock is operating.

Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (TA =

(2)

PD78F4218A, 78F4218AY

µµµµ

40 to +85

−−−−

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (3/3)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply voltage

DD1

I

DD2

I

Operation
mode

HALT mode

fXX = 12.5 MHz, VDD = 5.0 V ±10% 19 40 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 6 17 mA

XX

f

= 3 MHz, VDD = 2.0 V ±5% 2 10 mA
fXX = 12.5 MHz, VDD = 5.0 V ±10% 7 20 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 2 10 mA

XX

f

= 3 MHz, VDD = 2.0 V ±5% 0.5 7 mA

DD3

I

IDLE mode

fXX = 12.5 MHz, VDD = 5.0 V ±10% 1 3 mA
fXX = 6 MHz, VDD = 3.0 V ±10% 0.5 1.3 mA

XX

f

= 3 MHz, VDD = 2.0 V ±5% 0.3 0.9 mA

DD4

I

Operation

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 140 500
fXX = 32 kHz, VDD = 3.0 V ±10% 100 350
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 90 300
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 80 250

DD5

I

HALT

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 60 200
fXX = 32 kHz, VDD = 3.0 V ±10% 20 160
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 15 120
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 10 100

DD6

I

IDLE

Note

mode

fXX = 32 kHz, VDD = 5.0 V ±10% 50 190
fXX = 32 kHz, VDD = 3.0 V ±10% 15 150
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V 12 110
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V 7 90

Data retention voltage V

DDDR

HALT, IDLE modes 1.9 5.5 V

DDDR

STOP mode

VDD = 2.0 V ±5% 2 10

DD

V

= 5.0 V ±10% 10 50

Pull-up resistor RLVIN = 0 V 10 30 100 k

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

AData retention current I

µ

A

µ

Ω

When main system clock is stopped and subsystem clock is operating.

Note

Remark

Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14125EJ1V0DS00

31

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

AC Characteristics (TA =

40 to +85

−−−−

(1) Read/write operation (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Cycle time t

Address setup time (t o A STB↓)t

Address hold time (from A STB↓)t

ASTB high-level width t

Address hold time (from RD↑)t

Delay time from address to RD↓t

Address float time (from RD↓)t

Data input time from address t

Data input time from AS TB

Data input time from RD

↓

Delay time from ASTB↓ to RD↓t

Data hold time (from RD↑)t

CYK

SAST

HSTLA

WSTH

HRA

DAR

FAR

DAID

DSTID

t

↓

DRID

t

DSTR

HRID

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

4.5 V ≤ VDD ≤ 5.5 V 80 ns

2.7 V ≤ VDD < 4.5 V 160 ns

2.0 V ≤ V

DD

2.7 V 320 ns

<

1.9 V ≤ VDD < 2.0 V 500 ns
VDD = 5.0 V ±10% (0.5 + a)T − 20 ns
VDD = 3.0 V ±10% (0.5 + a)T − 40 ns
VDD = 2.0 V ±5% (0.5 + a)T − 80 ns
VDD = 5.0 V ±10% 0.5T − 19 ns
VDD = 3.0 V ±10% 0.5T − 24 ns
VDD = 2.0 V ±5% 0.5T − 34 ns
VDD = 5.0 V ±10% (0.5 + a)T − 17 ns
VDD = 3.0 V ±10% (0.5 + a)T − 40 ns
VDD = 2.0 V ±5% (0.5 + a)T − 110 ns
VDD = 5.0 V ±10% 0.5T − 14 ns
VDD = 3.0 V ±10% 0.5T − 14 ns
VDD = 2.0 V ±5% 0.5T − 14 ns
VDD = 5.0 V ±10% (1 + a)T − 24 ns
VDD = 3.0 V ±10% (1 + a)T − 35 ns
VDD = 2.0 V ±5% (1 + a)T − 80 ns
VDD = 5.0 V ±10% 0 ns
VDD = 3.0 V ±10% 0 ns
VDD = 2.0 V ±5% 0 ns
VDD = 5.0 V ±10% (2.5 + a + n)T − 37 ns
VDD = 3.0 V ±10% (2.5 + a + n)T − 52 ns
VDD = 2.0 V ±5% (2.5 + a + n)T − 120 ns
VDD = 5.0 V ±10% (2 + n)T − 35 ns
VDD = 3.0 V ±10% (2 + n)T − 50 ns
VDD = 2.0 V ±5% (2 + n)T − 80 ns
VDD = 5.0 V ±10% (1.5 + n)T − 40 ns
VDD = 3.0 V ±10% (1.5 + n)T − 50 ns
VDD = 2.0 V ±5% (1.5 + n)T − 90 ns
VDD = 5.0 V ±10% 0.5T − 9ns
VDD = 3.0 V ±10% 0.5T − 9ns
VDD = 2.0 V ±5% 0.5T − 20 ns
VDD = 5.0 V ±10% 0 ns
VDD = 3.0 V ±10% 0 ns
VDD = 2.0 V ±5% 0 ns

Remark

32

CYK

T: t

= 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of waits (n ≥ 0)

Data Sheet U14125EJ1V0DS00

AC Characteristics

(1) Read/write operation (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Address active time from RD

Delay time from RD↑ to ASTB↑t

RD low-level width t

Delay time from address t o WR↓t

Address hold time (from WR↑)t

Delay time from ASTB↓ to data
output

Delay time from WR↓ to data
output

Delay time from ASTB↓ to WR↓t

Data setup time (to WR↑)t

Data hold time (from WR↑)t

Delay time from WR↑ to ASTB↑t

WR low-level width t

DRA

t

↑

DRST

WRL

DAW

HRD

DSTOD

t

DWOD

t

DSTW

SODWR

HWOD

DWST

WWL

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

VDD = 5.0 V ±10% 0.5T − 2ns
VDD = 3.0 V ±10% 0.5T − 12 ns
VDD = 2.0 V ±5% 0.5T − 35 ns
VDD = 5.0 V ±10% 0.5T − 9ns
VDD = 3.0 V ±10% 0.5T − 9ns
VDD = 2.0 V ±5% 0.5T − 40 ns
VDD = 5.0 V ±10% (1.5 + n)T − 25 ns
VDD = 3.0 V ±10% (1.5 + n)T − 30 ns
VDD = 2.0 V ±5% (1.5 + n)T − 25 ns
VDD = 5.0 V ±10% (1 + a)T − 24 ns
VDD = 3.0 V ±10% (1 + a)T − 34 ns
VDD = 2.0 V ±5% (1 + a)T − 70 ns
VDD = 5.0 V ±10% 0.5T − 14 ns
VDD = 3.0 V ±10% 0.5T − 14 ns
VDD = 2.0 V ±5% 0.5T − 14 ns
VDD = 5.0 V ±10% 0.5T + 15 ns
VDD = 3.0 V ±10% 0.5T + 30 ns
VDD = 2.0 V ±5% 0.5T + 240 ns
VDD = 5.0 V ±10% 0.5T − 30 ns
VDD = 3.0 V ±10% 0.5T − 30 ns
VDD = 2.0 V ±5% 0.5T − 30 ns
VDD = 5.0 V ±10% 0.5T − 9ns
VDD = 3.0 V ±10% 0.5T − 9ns
VDD = 2.0 V ±5% 0.5T − 20 ns
VDD = 5.0 V ±10% (1.5 + n)T − 20 ns
VDD = 3.0 V ±10% (1.5 + n)T − 25 ns
VDD = 2.0 V ±5% (1.5 + n)T − 70 ns
VDD = 5.0 V ±10% 0.5T − 14 ns
VDD = 3.0 V ±10% 0.5T − 14 ns
VDD = 2.0 V ±5% 0.5T − 50 ns
VDD = 5.0 V ±10% 0.5T − 9ns
VDD = 3.0 V ±10% 0.5T − 9ns
VDD = 2.0 V ±5% 0.5T − 30 ns
VDD = 5.0 V ±10% (1.5 + n)T − 25 ns
VDD = 3.0 V ±10% (1.5 + n)T − 30 ns
VDD = 2.0 V ±5% (1.5 + n)T − 30 ns

Remark

CYK

T: t

= 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)

Data Sheet U14125EJ1V0DS00

33

AC Characteristics

(2) External wait timing

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input time from address to
WAIT

↓

Input time from ASTB↓ to
WAIT

↓

Hold time from ASTB↓ to WAIT

Delay time from ASTB↓ to
WAIT

↑

Input time from RD↓ to WAIT

Hold time from RD↓ to WAIT

Delay time from RD↓ to WAIT

Data input time from WAI T

Delay time from WAIT↑ to RD

Delay time from WAIT↑ to WR

Input time from WR↓ to WAIT

Hold time from WR↓ to WAIT

Delay time from WR↓ to WAIT

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DAWT

t

VDD = 5.0 V ±10% (2 + a)T − 40 ns
VDD = 3.0 V ±10% (2 + a)T − 60 ns
VDD = 2.0 V ±5% (2 + a)T − 300 ns

DSTWT

t

VDD = 5.0 V ±10% 1.5T − 40 ns
VDD = 3.0 V ±10% 1.5T − 60 ns
VDD = 2.0 V ±5% 1.5T − 260 ns

HSTWT

t

VDD = 5.0 V ±10% (0.5 + n)T + 5ns
VDD = 3.0 V ±10% (0.5 + n)T + 10 ns
VDD = 2.0 V ±5% (0.5 + n)T + 30 ns

DSTWTH

t

VDD = 5.0 V ±10% (1.5 + n)T − 40 ns
VDD = 3.0 V ±10% (1.5 + n)T − 60 ns
VDD = 2.0 V ±5% (1.5 + n)T − 90 ns

DRWTL

t

↓

VDD = 5.0 V ±10% T − 40 ns
VDD = 3.0 V ±10% T − 60 ns
VDD = 2.0 V ±5% T − 70 ns

HRWT

t

↓

VDD = 5.0 V ±10% nT + 5ns
VDD = 3.0 V ±10% nT + 10 ns
VDD = 2.0 V ±5% nT + 30 ns

DRWTH

t

↑

VDD = 5.0 V ±10% (1 + n)T − 40 ns
VDD = 3.0 V ±10% (1 + n)T − 60 ns
VDD = 2.0 V ±5% (1 + n)T − 90 ns

DWTID

t

↑

VDD = 5.0 V ±10% 0.5T − 5ns
VDD = 3.0 V ±10% 0.5T − 10 ns
VDD = 2.0 V ±5% 0.5T − 30 ns

DWTR

t

↑

VDD = 5.0 V ±10% 0.5T ns
VDD = 3.0 V ±10% 0.5T ns
VDD = 2.0 V ±5% 0.5T + 5ns

DWTW

t

↑

VDD = 5.0 V ±10% 0.5T ns
VDD = 3.0 V ±10% 0.5T ns
VDD = 2.0 V ±5% 0.5T + 5ns

DWWTL

t

↓

VDD = 5.0 V ±10% T − 40 ns
VDD = 3.0 V ±10% T − 60 ns
VDD = 2.0 V ±5% T − 90 ns

HWWT

t

VDD = 5.0 V ±10% nT + 5ns
VDD = 3.0 V ±10% nT + 10 ns
VDD = 2.0 V ±5% nT + 30 ns

DWWTH

t

↑

VDD = 5.0 V ±10% (1 + n)T − 40 ns
VDD = 3.0 V ±10% (1 + n)T − 60 ns
VDD = 2.0 V ±5% (1 + n)T − 90 ns

Remark

34

CYK

T: t

= 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Serial Operation (TA =

40 to +85

−−−−

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY1

2.7 V ≤ VDD ≤ 5.5 V 800 nsSCK cycle time t

KH1

2.7 V ≤ VDD ≤ 5.5 V 350 nsSCK high-/low-level width t

,

KL1

t

SIK1

2.7 V ≤ VDD ≤ 5.5 V 10 nsSI setup time (to SCK↑)t

t

KSI1

KSO1

SI hold time (from SCK↑)t
SO output delay time

(from SCK↓)

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY2

2.7 V ≤ VDD ≤ 5.5 V 800 nsSCK cycle time t

KH2

2.7 V ≤ VDD ≤ 5.5 V 400 nsSCK high-/low-level width t

KL2

t

SIK2

2.7 V ≤ VDD ≤ 5.5 V 10 nsSI setup time (to SCK↑)t

t

KSI2

KSO2

SI hold time (from SCK↑)t
SO output delay time

(from SCK↓)

3,200 ns

1,500 ns

30 ns
40 ns

30 ns

3,200 ns

1,600 ns

30 ns
40 ns

30 ns

(c) UART mode

Parameter Symbol Conditions MIN. TYP. MAX. Unit

ASCK cycle time t

ASCK high-/low-level wi dth t

KCY3

4.5 V ≤ VDD ≤ 5.5 V 417 ns

2.7 V ≤ VDD < 4.5 V 833 ns
1,667 ns

KH3

4.5 V ≤ VDD ≤ 5.5 V 208 ns

KL3

t

2.7 V ≤ VDD < 4.5 V 416 ns

833 ns

Data Sheet U14125EJ1V0DS00

35

(d) I2C bus mode

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

SCL0 clock frequency f
Bus free time (between st op

and start conditions)
Hold time

Note1

Low-level width of SCL0 cloc k t
High-level width of SCL0 c l ock t
Setup time of start/restart

conditions

When using CBUS-

time

compatible master
When using I

2

C bus
Data setup time t
Rise time of SDA0 and SCL0

signals
Fall time of SDA0 and SCL0

signals
Setup time of stop c ondi t i on t
Pulse width of spike restricted

by input filter
Load capacitance of each bus

line

CLK

BUF

t

HD : STA

t

LOW

HIGH

SU : STA

t

HD : DAT

t

SU : DAT

R

t

F

t

SU : STO

SP

t

Cb

Standard Mode High-Speed ModeParameter Symbol

MIN. MAX. MIN. MAX.

0 100 0 400 kHz

Note 2

0

250

4.7

4.0

4.7

4.0

4.7

5.0

−

−

4.0

−

−

−

−

−

−−−

−

−

1,000 20 + 0. 1Cb

300 20 + 0.1Cb

−

−−

−

400

0

100

1.3

0.6

1.3

0.6

0.6

Note 2

Note 4

Note 5

Note 5

0.6

−

−

−

−

−

Note 3

0.9

−

300 ns

300 ns

−

050ns

−

400 pF

Unit

µ

µ
µ
µ
µ

µ

µ

ns

µ

s

s
s
s
s

sData hold

s

s

Notes 1.

For the start condition, the first clock pulse is generated after the hold time.
To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

2.

IHmin.

SDA0 signal (on V

If the device does not extend the SCL0 signal low-level hold time (t

3.

HD : DAT

time t

The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the

4.

needs to be satisfied.

) with at least 300 ns of hold time.

LOW

), only the maximum data hold

conditions described below must be satisfied.

If the device does not extend the SCL0 signal low-level hold time

•

SU : DAT

t

≥ 250 ns

If the device extends the SCL0 signal low-level hold time

•

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t

Rmax.

+ t

SU : DAT

= 1,000 + 250 = 1,250 ns by standard mode I2C bus specification)

Cb: Total capacitance per bus line (unit: pF)

5.

36

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Other Operations (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit

NMI high-/low-level widt h t

Interrupt input high-/low-lev el wi dth t

RESET high-/low-level width t

40 to +85

−−−−

Clock Output Operation (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit
PCL cycle time t
PCL high-/low-level width t

PCL rise/fall time t

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

WNIL

WNIH

t

WITL

INTP0 to INTP6 100 ns

WITH

t

WRSL

WRSH

t

40 to +85

−−−−

CYCL

CLL

CLH

t

CLR

CLF

t

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

4.5 V ≤ VDD ≤ 5.5 V, nT 80 31,250 ns

4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10 30 15,615 ns

4.5 V ≤ VDD ≤ 5.5 V 5 ns

2.7 V ≤ VDD < 4.5 V 10 ns

1.9 V ≤ VDD < 2.7 V 20 ns

10

10

s

µ

s

µ

Remark

CYK

T: t

= 1/fXX (fXX: Main system clock frequency)

n: Divided frequency ratio set by software in the CPU

When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

•

When using the subsystem clock: n = 1

•

Data Sheet U14125EJ1V0DS00

37

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

A/D Converter Characteristics (TA =

40 to +85

−−−−

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888bits
Overall error

Notes 1, 2

Conversion time t
Sampling time t
Analog input voltage V
Reference voltage AV
Resistance between AV

Notes 1.

Remark

Quantization error (±1/2 LSB) is not included.
Overall error is indicated as a ratio to the full-scale value.

2.

XX

f

REF0

and AVSSR

: Main system clock frequency

D/A Converter Characteristics (TA =

2.7 V ≤ VDD ≤ 5.5 V

REF0

2.2 V ≤ AV

≤ V

DD

1.9 V ≤ VDD < 2.7 V

REF0

1.9 V ≤ AV

CONV

SAMP

IAN

REF0

AVREF0

When not A/D converting 40 k

40 to +85

−−−−

DD

≤ V

14 144

XX

24/f

SS

AV

1.9 AV

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

1.2 %FSR

±

1.6 %FSR

±

REF0

AV

DD

s

µ

s

µ

V
V

Ω

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888Bits

Overall error

Settling time Load conditions:

Output resistance RODACS0, 1 = 55H 8 k
Reference voltage AV

REF1

AV

Notes 1.

Notes 1, 2

R = 10 MΩ, 2.0 V ≤ AV

2.0 V ≤ V

DD

R = 10 MΩ, 1.9 V ≤ AV

1.9 V ≤ V

DD

C = 30 pF

REF1

current AI

REF1

For only 1 channel 2.5 mA

Quantization error (±1/2 LSB) is not included.
Overall error is indicated as a ratio to the full-scale value.

2.

≤ 5.5 V

≤ 2.0 V

REF1

≤ VDD,

REF1

≤ VDD,

4.5 V ≤ AV

2.7 V ≤ AV

1.9 V ≤ AV

REF1

≤ 5.5 V 10

REF1

< 4.5 V 15

REF1

< 2.7 V 20

1.9 V

0.6 %FSR

±

1.2 %FSR

±

µ
µ
µ

DD

s
s
s

Ω

V

38

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Data Retention Characteristics (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention voltage V

VDD rise time t
VDD fall time t
VDD hold time

DDDR

DDDR

RVD

FVD

HVD

t

(from STOP mode setti ng)
STOP release signal input time t

Low-level input voltage V
High-level input voltage V

DREL

WAIT

IL

IH

AC Timing Test Points

DD

− 1 V

V

0.45 V

0.8VDD or 1.9 V

0.8 V

40 to +85

−−−−

C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

°°°°

STOP mode 1.9 5.5 V

DDDR

V

= 5.0 V ±10% 10 50

DDDR

V

= 2.0 V ±5% 2 10

200
200

µ
µ

µ
µ

0ms

0ms
Crystal resonator 30 msOscillation stabilization wait time t
Ceramic resonator 5 ms

V

DDDR

DDDR

RESET, P00/INTP0 to P06/INTP6

00.1V

DDDR

0.9V

0.8VDD or 1.9 V

Test points

0.8 V

AData retention current I
A
s
s

V
V

Data Sheet U14125EJ1V0DS00

39

Timing Waveforms

(1) Read operations

(CLK)

t

CYK

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

A0 to A7

(Output)

A8 to A19

(Output)

AD0 to AD7

(I/O)

ASTB

(Output)

RD
(Output)

WAIT

(Input)

Lower address Lower address

Higher address

t

DAID

t

DSTID

Hi-Z Hi-Z Hi-Z

Lower address
(Output)

t

SAST

t

WSTH

t

DAWT

t

DAR

t

HSTLA

t

DSTR

t

DRWTL

t
t
t

DSTWT
DSTWTH
HSTWT

Data (Input)

t

HRID

t

FAR

t

DRID

t

WRL

t

DRWTH

t

HRWT

t

DWTID

t

DWTR

t

t

HRA

t

DRA

DRST

Higher address

Lower address
(Output)

40

Remark

The signal is output from pins A0 to A7 when P80 to P87 are unused.

Data Sheet U14125EJ1V0DS00

(2) Write operation

(CLK)

A8 to A19

(Output)

ASTB

(Output)

WAIT

(Input)

AD0 to AD7

(Output)

t

CYK

t

DAID

t

HWA

t

SAST

t

WSTH

t

DSTW

t

DWST

t

DAW

t

DWOD

t

WWL

t

DWWTH

t

DSTWT

t

DSTWTH

t

HSTWT

t

HWWT

t

DAWT

t

DWTW

t

HSTLA

t

FAR

t

DWTID

t

DWWTL

t

HWOD

t

DAW

t

DSTOD

t

SODWR

Hi-Z Hi-Z Hi-Z

WR

(Output)

Higher address Higher address

A0 to A7

(Output)

Lower address Lower address

Data (Output)

Lower address
(Output)

Lower address
(Output)

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Remark

The signal is output from pins A0 to A7 when P80 to P87 are unused.

Data Sheet U14125EJ1V0DS00

41

Serial Operation

(1) 3-wire serial I/O mode

(2) UART mode

SCK

SI/SO

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

t

t

KSO1, 2

t

KSI1, 2

KCY1, 2

t

KL1, 2

t

SIK1, 2

t

KH1, 2

t

KCY3

t

KH3

t

KL3

2

C bus mode (

(3) I

SCL0

SDA0

Stop
condition

ASCK

PD78F4216AY, 78F4218AY only)

µµµµ

R

t

t

HD : DAT

t

HD : STA

t

BUF

Start
condition

t

HIGH

t

SU : DAT

t

F

t

SU : STA

Restart
condition

t

HD : STA

t

SP

t

Stop
condition

SU : STO

42

Data Sheet U14125EJ1V0DS00

Clock Output Timing

CLKOUT

Interrupt Input Timing

NMI

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

t

CLH

t

CLR

t

CYCL

t

WNIH

t

CLL

t

CLF

t

WNIL

INTP0 to INTP6

Reset Input Timing

RESET

t

t

WRSH

WITH

t

WRSL

t

WITL

Data Sheet U14125EJ1V0DS00

43

Clock Timing

X1

XT1

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

t

WXH

t

XR

1/f

X

t

XTH

1/f

XT

t

WXL

t

XF

t

XTL

Data Retention Characteristics

STOP mode setting

V

DD

t

HVD

RESET

NMI
(Cleared by falling edge)

NMI
(Cleared by rising edge)

t

FVD

V

DDDR

t

RVD

t

DREL

t

WAIT

44

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7
to 10.3 V)

(1) Basic characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Operating frequency f

Supply voltage

Note 1

VDD supply current I
VPP supply current I
Write count C
Operating temperature
Storage temperature

Note 3

Note 4

Programming temperature T

X

DD

V

PPL

V

PP

V

PPH

V

DD

PP

WRT

A

T

stg

T

PRG

4.5 V ≤ VDD ≤ 5.5 V 2 12. 5 MHz

2.7 V ≤ VDD < 4.5 V 2 6.25 MHz

2.0 V ≤ VDD < 2.7 V 2 3.125 MHz

1.9 V ≤ VDD < 2.0 V 2 2 2 MHz

1.9 5.5 V

1.1V

DD

DD

V
V

Upon VPP low-level detection 0 0.2V
Upon VPP high-level detection 0.9V

DD

DD

V

Upon VPP high-voltage detection 9.7 10 10.3 V

40 mA

VPP = 10 V 100 mA

Note2

20

40 85

−

65 125

−

10 40

Times

C

°

C

°

C

°

PD78F4216A, 78F4216AY K standard: 2.7 V ≤ VDD < 5.5 V, VPP = 10.3 ±0.3 V

Notes 1.

µ

E standard: 2.7 V ≤ VDD < 5.5 V, VPP = 10.0 ±0.3 V

Operation cannot be guaranteed when the number of writes exceeds 20 times. In the case of the

2.

PD78F4216A and 78F4216AY with K standard, operation cannot be guaranteed when the number of

µ

writes exceeds 5 times.

µPD78F4216A, 78F4216AY K standard: TA = −10 to +60°C

3.

µPD78F4216A, 78F4216AY K standard: TA = −10 to +80°C

4.

Cautions 1. If writing is not successful in write operation, execute the program command again, and

execute the verify command to confirm the normal completion of the write operation.
(

PD78F4216A, 78F4216AY: I, K, E, P standard)

µµµµ

2. Handshake mode is supported by the following products.
PD78F4216A, 78F4216AY: Other than I, K, E standard

µµµµ

PD78F4218A, 78F4218AY: Other than I standard

µµµµ

Remark

The fifth alphabetic character from the left in the lot number indicates the standard of the product. After
executing the program command, execute the verify command to confirm the normal completion of the
write operation.
Handshake mode is the CSI write mode that uses P24.

Data Sheet U14125EJ1V0DS00

45

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7
to 10.3 V)

(2) Serial write operation characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VPP setup time t

PP

V

setup time to V

↑

RESET↑ set up time to V
VPP count start time from RESET

DD

↑

PP

↑

↑

Count execution time t
VPP counter high-level width t
VPP counter low-level width t
VPP counter noise elimination wi dth t

PSRON

DRPSR

t

PSRRF

t

RFCF

t

COUNT

CH

CL

NFW

VPP high voltage 1.0
VPP high voltage 10
VPP high voltage 1.0

1.0

8.0

8.0

µ
µ
µ
µ

1.0 ms

µ
µ

40 ns

s
s
s
s

s
s

Flash Memory Write Mode Setting Timing

V

VPPV

RESET (input)

V

DD

DD

V

V

0 V

PPH

PPL

V

t

DRPSR

PP

t

PSRONtPSRRF

DD

t

RFCF

t

CH

t

CL

t

COUNT

0 V

46

Data Sheet U14125EJ1V0DS00

µµµµ

100-PIN PLASTIC LQFP (FINE PITCH) (14x14)

NOTE

Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A
B

D

G

16.00±0.20

14.00±0.20

0.50 (T.P.)

1.00

J

16.00±0.20

K

C 14.00±0.20

I 0.08

1.00±0.20

L

0.50±0.20

F 1.00

N
P
Q

0.08

1.40±0.05

0.10±0.05

S100GC-50-8EU, 8EA-2

S 1.60 MAX.

H 0.22

+0.05

−0.04

M 0.17

+0.03

−0.07

R3°

+7°

−3°

1

25

26

50

100

76

75 51

S

SN

J

detail of lead end

C D

A
B

R

K

M

L

P

I

S

Q

G

F

M

H

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

8. PACKAGE DRAWINGS

Remark

The external dimensions and material of the ES version are the same as those of the mass-produced

version.

Data Sheet U14125EJ1V0DS00

47

80

81

50

100

1

31

30

51

100-PIN PLASTIC QFP (14x20)

HI

J

detail of lead end

M

Q

R

K

M

L

P

S

SN

G

F

NOTE

Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A
B

D

G

23.6±0.4

20.0±0.2

0.30±0.10

0.6

H

17.6±0.4

I

C 14.0±0.2

0.15

J

0.65 (T.P.)

K

1.8±0.2

L

0.8±0.2

F 0.8

P100GF-65-3BA1-4

N
P
Q

0.10

2.7±0.1

0.1±0.1
R5°±5°
S 3.0 MAX.

M 0.15

+0.10

−0.05

C D

A
B

S

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Remark

48

The external dimensions and material of the ES version are the same as those of the mass-produced

version.

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

9. RECOMMENDED SOLDERING CONDITIONS

The µPD78F4218AY should be soldered and mounted under the following recommended conditions. For the

details of the recommended soldering conditions, refer to the document

Technology Manual (C10535E)

.

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 9-1. Surface Mounting Type Soldering Conditions

Semiconductor Device Mounting

PD78F4216AGC-8EU:100-pin plastic LQFP (fine pitch) (14

(1)

µµµµ

PD78F4218AGC-8EU:100-pin plastic LQFP (fine pitch) (14

µµµµ

PD78F4216AYGC-8EU:100-pin plastic LQFP (fine pitch) (14

µµµµ

PD78F4218AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14

µµµµ

Soldering Method Soldering Conditions Recommended

Infrared reflow Package peak tem perat ure: 235°C, Time: 30 seconds max . (at 210°C or higher),

Count: Two times or less, Exposure limit: 7 day s
for 10 hours)

VPS Package peak temperature: 215°C, Time: 40 seconds max . (at 200°C or higher),

Count: Two times or less, Exposure limit: 7 day s
for 10 hours)

Partial heating Pin temperature: 300°C max., Time: 3 sec onds max. (per pin row)

After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Note

14)

××××

14)

××××

14)

××××

14)

××××

Note

(after that, prebake at 125°C

Note

(after that, prebake at 125°C

Condition Symbol

IR35-107-2

VP15-107-2

−

Caution Do not use different soldering methods together (except for partial heating).

(2)

PD78F4216AGF-3BA:100-pin plastic QFP (14

µµµµ

PD78F4218AGF-3BA:100-pin plastic QFP (14

µµµµ

PD78F4216AYGF-3BA:100-pin plastic QFP (14

µµµµ

PD78F4218AYGF-3BA: 100-pin plastic QFP (14

µµµµ

××××
××××

20)

20)

20)

××××

××××

20)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak tem perat ure: 235°C, Time: 30 seconds max . (at 210°C or higher),

Count: Two times or less

VPS Package peak temperature: 215°C, Time: 40 seconds max . (at 200°C or higher),

Count: Two times or less

Wave soldering Solder bath temperature: 260°C max., Time: 10 sec onds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature)

Partial heating Pin temperature: 300°C max., Time: 3 sec onds max. (per pin row)

IR35-00-2

VP15-00-2

WS60-00-1

−

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14125EJ1V0DS00

49

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD78F4218AY. Also refer to

(5) Cautions on using development tools

(1) Language processing software

RA78K4 Assembler package com m on to 78K/IV Series
CC78K4 C compiler package common to 78K / IV Series
DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
CC78K4-L C c om piler library source file common to 78K/IV Seri es

(2) Flash memory writing tools

.

Flashpro II
(Part number: FL-PR2),
Flashpro III
(Part number: FL-PR3, PG-FP3)

FA-100GF Adapter for writing 100-pin plastic QFP (GF-3B A type) flash memory. Connection must be

FA-100GC Adapter for writ i ng 100-pi n pl astic LQFP (GC-8EU type) flash memory. Connection must be

Dedicated flash programmer for m i crocontroller incorporating flash memory

performed in accordance with the target product.

performed in accordance with the target product.

(3) Debugging tools

When IE-78K4-NS in-circuit emulator is used

••••

IE-78K4-NS In-circuit emulator common t o 78K/IV Series
IE-70000-MC-PS-B Power supply unit for IE-78K4-NS
IE-70000-98-IF-C Interface adapter required when PC-9800 s eri es PC (except notebook type) i s used as host

machine (C bus supported)

IE-70000-CD-IF-A PC card and cabl e when P C-9800 series notebook PC is used as host machine (PCMCIA

socket supported)

IE-70000-PC-IF-C

IE-70000-PCI-IF Interface adapter required when usi ng PC that incorporates PCI bus as host machine
IE-784225-NS-EM1 Emulation board to emulat e µPD784216A, 784216AY, 784218A, 784218AY Subseries
NP-100GF Emulati on probe f or 100-pi n pl astic QFP (GF-3BA type)
NP-100GC Emulation probe for 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW Conversion adapter to c onnect the NP-100GC and a target system board on which a 100-pin

ID78K4-NS Integrated debugger for IE-78K4-NS
SM78K4 System si mulator common to 78K/IV Series
DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries

Interface adapter required when using I B M PC/AT
supported)

plastic LQFP (GC-8EU ty pe) c an be mounted

TM

compatibles as host m achine (ISA bus

50

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

When IE-784000-R in-circuit emulator is used

••••

IE-784000-R In-circuit emulator common to 78K/IV Series
IE-70000-98-IF-C Interface adapter required when PC-9800 s eri es PC (except notebook type) i s used as host

machine (C bus supported)

IE-70000-PC-IF-C Interface adapter required when using IBM PC/AT and c om patibles as host machine (I SA bus

supported)
IE-70000-PCI-IF Interface adapter required when usi ng PC that incorporates PCI bus as host machine
IE-78000-R-SV3 Interface adapter and cable required when EWS is used as host machine
IE-784225-NS-EM1 Emulation board to emulat e µPD784216A, 784216AY, 784218A, 784218AY Subseries
IE-784000-R-EM Emulation board common to 78K/IV S eri es
IE-78K4-R-EX3 Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R.
EP-784218GF-R Emulation probe for 100-pin plas t i c QFP (GF-3BA type)
EP-78064GC-R Emulation probe for 100-pin plas tic LQFP (GC-8EU type)
EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW Conversion adapter to c onnect the EP-78064GC-R and a target system board on which a

100-pin plastic LQFP (GC-8EU type) can be mounted
ID78K4 Integrated debugger for IE-784000-R
SM78K4 System si mulator common to 78K/IV Series
DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries

(4) Real-time OS

RX78K/IV Real-ti m e OS for 78K/IV Series
MX78K4 OS for 78K/IV Series

Data Sheet U14125EJ1V0DS00

51

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

(5) Cautions on using development tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.

•

The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

•

The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito

•

Densei Machida Mfg. Co., Ltd. (TEL: [phone]).

The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

•

For further information, contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (TEL: [phone])
Osaka Electronic Division (TEL: [phone])

For third party development tools, see the

•

Single-Chip Microcontroller Development Tool Selection

Guide (U11069E).

The host machine and OS suitable for each software are as follows:

•

PC EWSHost Machine

Software
RA78K4

CC78K4
ID78K4-NS
ID78K4
SM78K4
RX78K/IV
MX78K4

[OS]

PC-9800 series [Windows]

IBM PC/AT and compatibles

[Japanese/English Windows]

Note

√

Note

√

√−
√√
√−

Note

√

Note

√

HP9000 Series 700TM [HP-UXTM]

SPARCstation

NEWS

TM

[SunOSTM, SolarisTM]

TM

(RISC) [NEWS-OSTM]

√
√

√
√

DOS-based software

Note

52

Data Sheet U14125EJ1V0DS00

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

APPENDIX B. RELATED DOCUMENTS

Documents related to devices

Document Name Document No.

PD784214A, 784215A, 784216A, 784217A, 784218A , 784214AY, 784215AY, 784216AY, 784217AY,

µ

784218AY Data Sheet

PD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet This document

µ

PD784216A, 784216AY Subseries User’s Manual Hardware U13570E

µ

PD784218A, 784218AY Subseries User’s Manual Hardware U12970E

µ

78K/IV Series User’s Manual Instructions U10905E
78K/IV Series Ins truction Table
78K/IV Series Ins truction Set
78K/IV Series Appli cation Note Software Basic s

Documents related to development tools (user’s manuals)

Document Name Document No.

Language U11162ERA78K4 Assembler Pa ckage
Operation U11334E

RA78K Structured Assembler Preprocessor U11743E

Language U11571ECC78K4 C Compiler

Operation U11572E
IE-78K4-NS U13356E
IE-784000-R U12903E
IE-784218-R-EM1 U12155E
IE-784225-NS-EM1 U13742E
EP-78064 EEU-1469
SM78K4 System Si mulator Windows Based Reference U10093E
SM78K Series System Simulator External Part User Open

Interface Specifi c ations
ID78K4-NS Integrated Debugger PC Bas ed Reference U12796E
ID78K4 Integrated Debugger Windows Bas ed Reference U10440E
ID78K4 Integrated Debugger HP-UX, S unOS , NEWS-OS Based Reference U11960E

U14121E

U10092E

−

−

−

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14125EJ1V0DS00

53

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Documents related to embedded software (user’s manuals)

Document Name Document No.

78K/IV Series Real-Tim e OS

78K/IV Series OS MX78K4 Fundamental

Fundamental U10603E
Installation U10604E
Debugger

Other documents

Document Name Document No.
SEMICONDUCTOR SELECTION GUI DE Products & Packages (CD-ROM) X13769X
Semiconductor Device Mounting Technology Manual C10535E
Quality Grades on NEC Semic onductor Devices C11531E
NEC Semiconductor Device Reliability /Quality Control System C10983E
Guide to Prevent Damage for Semi conductor Devices by El ec trostatic Discharge (E S D) C11892E
Guide to Microcomputer-Relat ed P roducts by Third Party

−

−

−

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

54

Data Sheet U14125EJ1V0DS00

[MEMO]

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Data Sheet U14125EJ1V0DS00

55

[MEMO]

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

56

Data Sheet U14125EJ1V0DS00

[MEMO]

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Data Sheet U14125EJ1V0DS00

57

µµµµ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.

58

Data Sheet U14125EJ1V0DS00

µµµµ

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

J00.7

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Data Sheet U14125EJ1V0DS00

59

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

µµµµ

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.

•

The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

•

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.

•

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.

•

NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4