NEC UPD75328GC-XXX-3B9, UPD75328GC-A-XXX-3B9 Datasheet

Document No. IC-2763B

(O. D. No. IC-7628D)
Date Published November 1993 P
Printed in Japan

 NEC Corporation 1990

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75328

4-BIT SINGLE-CHIP MICROCOMPUTER

The mark ★ shows the major revised points.

DESCRIPTION

The µPD75328 is one of the 75X Series 4-bit single-chip microcomputer, and has a data processing

capability comparable to that of an 8-bit microcomputer.

In addition to high-speed operation with 0.95

µ

s minimum instruction execution time for the CPU, the

µ

PD75328 can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer
chip having a built-in LCD controller/driver and A/D converter, its data processing capability is the highest
in its class in the world.

The

µ

PD75P328 with one-time PROM, which is replaced with the internal mask ROM for a µPD75328,
is applicable for evaluating systems under development, or for small-scale production of developed
systems.

"Detailed functions are described in the following user's manual. Be sure to read it for designing."

"

µPD75328 User's Manual: IEM-5045"

FEATURES

• Capable of high-speed operation and variable instruction execution time to power save

• 0.95

µ

s, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz)

• 122

µ

s (Subsystem clock: operating at 32.768 kHz)

• 75X architecture comparable to that for an 8-bit microcomputer is employed

• Built-in programmable LCD controller/driver

• Built-in 8-bit resolution A/D converter:

6 channels

• Clock operation at reduced power dissipation: 5

µ

A TYP. (operating at 3 V)

• Timer function: 3 channels

• Interrupt functions especially enhanced for applications, such as remote control receiver

• Pull-up resistors can be provided for 35 I/O lines

• Built-in NEC standard serial bus interface (SBI)

APPLICATIONS

Cameras, blood pressure gauges, airconditioners, etc.

The information in this document is subject to change without notice.

ORDERING INFORMATION

Part Number Package Quality Grade

µ

PD75328GC-xxx-3B9 80-pin plastic QFP (■■14mm) Standard

Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209)
published by NEC Corporation to know the specification of quality grade on the devices and its
recommended applications.

2

µ

PD75328

Including the pins
which also serve
as LCD drive pins.
Excluding the
pins which is
specifically pro­vided for driving
LCD.

FUNCTIONAL OUTLINE (1/2)

Item Function

Number of Basic 41
Instructions

Instruction 0.95, 1.91, and 15.3 µs, (Main system clock: operating at 4.19 MHz)
Execution Time 122 µs (Subsystem clock: operating at 32.768 kHz)

ROM 8064 × 8-bit
RAM 512 × 4-bit

General-Purpose 4-bit manipulation: 8×4 banks, 8-bit manipulation: 4×4 banks
Registers

I/O Line 8 CMOS Input pins Internal pull-up resistor

specification by software

44 20 CMOS input/output pins is possible (except P00).

8 CMOS output pins Also serve as segment pins
8 N-ch open-drain Withstand voltage: 10V

input/output Internal pull-up resistor

specification by mask option
is possible.

LCD Controller/ • LCD drive output pins
Driver • Segment output pins: 20 (CMOS output pins: 8)

• Common output pins: 4

• Capable of driving up to 20 × 4 segments

• Display output mode: Static, 1/2, 1/3, 1/4 duty

A/D Converter 8-bit resolution x 6 channels (successive approximation type)

• Operating voltage VDD = 3.5 to 6.0 V

• A/D conversion speed 40.1 µs (operating at 4.19 MHz)
8-bit timer/event counter

• Clock source: 4 steps

• Event count is possible

8-bit basic interval timer

Timer 3 chs • Reference time generation (1.95, 7.82, 31.3, 250 ms: operating at 4.19
MHz)

• Can be used as watchdog timer

Clock timer

• 0.5 second interval generation

• Count clock source slectable (4.19 MHz/32.768 kHz)

• Clock advance mode (3.9 ms time interval generation)

• Buzzer output (2 kHz)

Clock synchronized serial interface
Serial • Internal NEC standard serial bus interface (SBI mode)
Interface • 3-line serial I/O mode ... MSB/LSB first selectable

• 2-line serial I/O mode

Bit Sequential Special bit manipulation memory: 16 bits
Buffer

Clock Output Φ, 524, 262, 65.5 kHz (Main system clock: 4.19 MHz)
(PCL)

Buzzer Output 2 kHz (with main system clock or subsystem clock operated)
(BUZ)

Vector Interrupt • External: 3

• Internal: 3

Test Input • External: 1

• Internal: 1

Internal
Memory

3

µ

PD75328

FUNCTIONAL OUTLINE (2/2)

Item Function

System Clock • Main system clock generation ceramic/crystal oscillator; 4.194304 MHz
Generator • Subsystem clock generation crysal oscillator: 32.768 kHz

Standby STOP/HALT mode
Operating –40 to +85°C

Temperature Range
Operating Supply VDD = 2.7 to 6.0 V

Voltage
Package 80-pin plastic QFP (■■14 mm)

4

µ

PD75328

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 6

2. BLOCK DIAGRAM ......................................................................................................................7

3. PIN FUNCTIONS ........................................................................................................................8

3.1 PORT PINS ........................................................................................................................................8

3.2 NON PORT PINS ............................................................................................................................ 10

3.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................... 12

3.4 RECOMMENDED PROCESSING OF UNUSED PINS.................................................................. 14

3.5 SELECTION OF MASK OPTION ................................................................................................... 15

3.6 NOTES ON USING THE P00/INT4, AND RESET PINS .............................................................. 15

4. MEMORY CONFIGURATION ................................................................................................. 16

5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 18

5.1 PORTS ............................................................................................................................................. 18

5.2 CLOCK GENERATOR CIRCUIT ..................................................................................................... 19

5.3 CLOCK OUTPUT CIRCUIT............................................................................................................. 20

5.4 BASIC INTERVAL TIMER .............................................................................................................. 21

5.5 WATCH TIMER ............................................................................................................................... 22

5.6 TIMER/EVENT COUNTER............................................................................................................. 22

5.7 SERIAL INTERFACE....................................................................................................................... 24

5.8 LCD CONTROLLER/DRIVER ......................................................................................................... 26

5.9 A/D CONVERTER .......................................................................................................................... 28

5.10 BIT SEQUENTIAL BUFFER .... 16 BITS ....................................................................................... 29

6. INTERRUPT FUNCTIONS ......................................................................................................... 29

7. STANDBY FUNCTIONS............................................................................................................ 31

8. RESET FUNCTION .................................................................................................................... 32

9. INSTRUCTION SET ................................................................................................................. 34

10. ELECTRICAL SPECIFICATIONS ............................................................................................. 40

11. CHARACTERISTIC CURVES (REFERENCE VALUE) ............................................................ 53

12. PACKAGE DRAWINGS ........................................................................................................... 59

13. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 61

5

µ

PD75328

APPENDIX A. COMPARISON OF FEATURES BETWEEN PD75328 AND PD75308 ........62

APPENDIX B. DEVELOPMENT TOOLS...................................................................................... 63

APPENDIX C. RELATED DOCUMENTS ..................................................................................... 64

µµ

6

µ

PD75328

P00-P03 : Port 0 AVSS : Analog Ground
P10-P13 : Port 1 AN0-AN5 : Analog Input 0-5
P20-P23 : Port 2 S12-S31 : Segment Output 12-31
P30-P33 : Port 3 COM0-COM3 : Command Output 0-3
P40-P43 : Port 4 V

LC0-VLC2 : LCD Power Supply 0-2

P50-P53 : Port 5 BIAS : LCD Power Supply Bias Control
P60-P63 : Port 6 LCDCL : LCD Clock
P70-P73 : Port 7 SYNC : LCD Synchronization
P80-P83 : Port 8 TI0 : Timer Input 0
BP0-BP7 : Bit Port PTO0 : Programmable Timer Output 0
KR0-KR7 : Key Return BUZ : Buzzer Clock
SCK : Serial Clock PCL : Programmable Clock
SI : Serial Input INT0,INT1,INT4 : External Vectored Interrupt 0,1,4
SO : Serial Output INT2 : External Test Input 2
SB0,SB1 : Serial Bus 0,1 X1,X2 : Main System Clock Oscillation 1,2
RESET : Reset Input XT1,XT2 : Subsystem Clock Oscillation 1,2
AV

REF : Analog Reference NC : No Connection

1. PIN CONFIGURATION (Top View)

S31/BP7

COM0

AN2

P73/KR7

PD75328GC– –3B9×××

µ

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

RESETX2X1NCXT2

XT1

VDDAVREF

AVSS

AN5

AN4

AN3

COM1

COM2

COM3

BIAS

VLC0

VLC1

VLC2

P40

P41

P42

P43

SSV

P50

P51

P52

P53

P00/INT4

P01/SCK

P02/SO/SB0

1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

S30/BP6
S29/BP5
S28/BP4
S27/BP3
S26/BP2
S25/BP1
S24/BP0

S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

AN1
AN0
P83
P82
P81
P80
P33
P32
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1

7

µ

PD75328

2. BLOCK DIAGRAM

AN0–AN5 6

AV

REF

AV

SS

TI0/P13

A/D
CONVERTER

BASIC
INTERVAL
TIMER

INTBT

TIMER/EVENT

COUNTER

#0

INTT0

PTO0/P20

BUZ/P23

WATCH
TIMER

INTW f

LCD

INTCSI

CLOCKED

SERIAL

INTERFACE

SI/SB1/P03

SO/SB0/P02

SCK/P01

PROGRAM
COUNTER (13)

ALU

CY

SP (8)

BANK

INT0/P10
INT1/P11
INT2/P12
INT4/P00

KR0/P60

–KR7/P73

8

INTERRUPT

CONTROL

BIT SEQ.

BUFFER (16)

PROGRAM

MEMORY

(ROM)

8064 8 BITS

×

DECODE

AND

CONTROL

GENERAL REG.

DATA

MEMORY

(RAM)

512 4 BITS

×

f /2

X

N

VDDVSSRESET

PCL/P22 XT1 XT2 X1 X2

SUB MAIN

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

SYSTEM CLOCK
GENERATOR

STAND BY
CONTROL

CPU
CLOCK

f

LCD

SYNC/P31

LCDCL/P30

BIAS

V -V

LC0 LC2

3

LCD

CONTROLLER

/DRIVER

4

8

12

COM0-COM3

S24/BP0

-S31/BP7

S12-S23

PORT 8

P80-P834

PORT 7

P70-P734

PORT 6

P60-P634

PORT 5

P50-P534

PORT 4

P40-P434

PORT 3

P30-P334

PORT 2

P20-P234

PORT 1

P10-P134

PORT 0

P00-P034

8

µ

PD75328

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

Input/

Output

Circuit

TYPE*

1

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30*

2

P31*

2

P32*

2

P33*

2

P40-43*

2

P50-53*

2

Pin Name

Input/Output Function 8-Bit I/O When Reset

Also Served
As

INT4

SCK

SO/SB0

SO/SB1

INT0

INT1

INT2

TI0

PTO0

—

PCL

BUZ

LCDCL

SYNC

—

—

—

—

4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.

With noise elimination function

4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.

4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.

Programmable 4-bit input/output port
(PORT3)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.

N-ch open-drain 4-bit input/output port
(PORT4)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the open­drain mode.

N-ch open-drain 4-bit input/output port
(PORT5)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the open­drain mode.

Input

Input

Input

Input

High level
(with internal
pull-up
resistor) or
high imped­ance

B

B -C

E-B

E-B

M

M

X

X

X

X

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

Input

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

●●

F -A

M -C

F -B

High level
(with internal
pull-up
resistor) or
high imped­ance

µ

PD75328

P60

P61

P62

P63

P70

P71

P72

P73

P80

P81

P82

P83

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

—

S24

S25

S26

S27

S28

S29

S30

S31

●●

Input/

Output

Input/

Output

Input/

Output

Output

Output

Also Served
As

Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.

Input

F -A

4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.

Input

F -A

Pin Name Input/Output Function 8-Bit I/O When Reset

4-bit input/output port (PORT8)
Internal pull-up resistors can be
specified in 4-bit units by software.

X

Input

E-B

1-bit output port (BIT PORT)
Shared with a segment output pin.

X

*2

G-C

*1: Circles indicate schmidt trigger inputs.

2: For BP0-7, V

LC1 indicated below are selected as the input source. However, the output level is

changed depending on BP0-7 and the V

LC1 external circuits.

Example: Since BP0-7 are connected to each other within the µPD75328 as shown in the diagram below,

the output level of BP0-7 depends on the sizes of R

1, R2 and R3.

PD75328

µ

ON

ON

BP

BP

V

DD

R

2

R

3

V

LC1

R

1

1

0

9

3.1 PORT PINS (2/2)

Input/

Output

Circuit

TYPE*

1

10

µ

PD75328

Parallel falling edge detection testable input/output

Parallel falling edge detection testable input/output

Segment signal output

Segment signal output

Common signal output

LCD drive power
Step-down resistor network (mask option)

External expanded driver for disconnect output

Externally expanded driver for clock output

Externally expanded driver sync clock output

6-bit analog input for A/D converter

A/D converter reference voltage input

GND potential for A/D converter reference voltage
input. Connected to VSS.

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0-KR3

KR4-KR7

S12-S23

S24-S31

COM0-

COM3

VLC0-VLC2

BIAS

LCDCL*

3

SYNC*

3

AN0-AN5

AVREF

AVSS

Input

Output

Input/
Output

Input/
Output

Input/
Output

Input/
Output

Input/
Output

Input

Input

Input

Input/
Output

Input/
Output

Output

Output

Output

—

Output

Input/
Output

Input/
Output

Input

Input

—

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60-P63

P70-P73

—

BP0-7

—

—

—

P30

P31

—

—

—

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

*4

*4

*4

—

*5

Input

Input

Input

Input

—

B -C

E-B

E-B

E-B

F -A

F -B

M -C

B

B -C

B -C

F -A

F -A

G-A

G-C

G-B

—

E-B

E-B

Y

Z

—

Pin Name Input/Output

Also Served
As

Functon When Reset

Input/

Output

Circuit

TYPE*

1

3.2 NON PORT PINS

Timer/event counter external event pulse Input

Timer/event counter output

Clock output

Fixed frequency output (for buzzer or for trim­ming the system clock)

Serial clock input/output

Serial data output
Serial bus input/output

Serial data input
Serial bus input/output

Edge detection vector interrupt input (both
rising and falling edge detection are effective)

Edge detection vector
interrupt input (detection
edge can be selected)

Edge detection testable
input (rising edge detection)

Clock synchronous

Asynchronous

Asynchronous

µ

PD75328

Also Served
As

To connect the crystal/ceramic oscillator to
the main system clock generator. When
inputting the external clock, input the
external clock to pin X1, and the reverse
phase of the external clock to pin X2.

To connect the crystal oscillator to the
subsystem clock generator.
When the external clock is used, pin XT1
inputs the external clock. In this case, pin
XT2 must be left open.
Pin XT1 can be used as a 1-bit input pin.

System reset input

No connection

Positive power supply

GND

X1, X2

—

——

—

XT1, XT2

—

—

—

—

Input

—

—

—

RESET

NC *

2

VDD

VSS

—

B

—

—

—

—

—

—

—

*1: Circles indicate schmidt trigger inputs.

2: When sharing the printed circut board with the

µ

PD75P328, the NC pin must be connected to

V

DD.

3: These pins are provided for future system expansion. At present, these pins are used only as

pins P30 and P31.

4: For these display output, V

LCX indicated below are selected as the input source.

S12 to S31: V

LC1, COM0 to COM2: VLC2, COM3: VLC0

However, display output level varies depending on the particular display output and VLCX
external circuit.

Example: Since BP0-7 are connected to each other within the µPD75328 as shown in the diagram

below, the output level of BP0-7 depends on the size of R

1, R2 and R3.

5: Step-down resistor network provided : Low level

Step-down resistor network not provided : High impedance

—

—

—

PD75328

µ

ON

ON

BP

BP

V

DD

R

2

R

3

V

LC1

R

1

1

0

11

Pin Name Input/Output Function When Reset

(cont'd)

Input/

Output

Circuit

TYPE*

1

12

µ

PD75328

3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the

µ

PD75328.

TYPE A (for TYPE E–B)

TYPE D (for TYPE E –

B, F

TYPE B

TYPE E–B

IN

V

DD

P–ch

N–ch

Input buffer of CMOS standard

data

output
disable

OUT

P–ch

N–ch

Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)

IN

Schmitt trigger input with hysteresis characteristics

data

output
disable

Type D

Type A

P.U.R.
enable

V

DD

P.U.R.

P–ch

IN/OUT

P.U.R. : Pull–Up Resistor

P.U.R.
enable

V

DD

P.U.R.

P–ch

TYPE B–C

TYPE F–A

IN

data

output
disable

Type D

Type B

P.U.R.
enable

V

DD

P.U.R.

P–ch

IN/OUT

P.U.R. : Pull–Up ResistorP.U.R. : Pull

–Up Resistor

Schmitt trigger input with hysteresis characteristics

A)

–

VDD

13

µ

PD75328

P-ch

TYPE M–C

data

output
disable

P.U.R.
enable

V

DD

P.U.R.

IN/OUT

P–ch

N-ch

TYPE F–B

TYPE M

data

output
disable

P.U.R.
enable

V

DD

IN/OUT

Middle voltage input buffer

(resistive voltage: +10 V)

P.U.R. : Pull–Up Resistor

data

output
disable

P.U.R.
enable

V

DD

P.U.R.

P–ch

N-ch

P-ch

output
disable

(P)

output
disable

(N)

V

DD

(Mask option)

P.U.R. : Pull–Up Resistor

IN/OUT

TYPE G–C

TYPE G–A

P.U.R. : Pull–Up Resistor

TYPE G–B

V

DD

V

LC0

V

LC0

V

LC1

V

LC2

SEG
data/Bit Port data

P-ch

N-ch

OUT

N-ch

V

LC1

V

LC2

P-ch

P-ch

N-ch

OUT

N-ch

V

LC0

V

LC1

V

LC2

P-ch

N-ch

SEG
data

COM
data

OUT

P-ch N-ch

N-ch P-ch

N-ch

14

µ

PD75328

Pin Recommended Connections
P00/INT4 Connect to VSS
P01/SCK
P02/SO/SB0 Connect to VSS or VDD
P03/SI/SB1
P10/INT0-P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30-P33 Input : Connect to VSS or VDD
P40-P43 Output: Open
P50-P53
P60-P63
P70-P73
P80-P83
S12-S23
S24/BP0-S31/BP7 Open
COM0-COM3
VLC0-VLC2 Connect to VSS
BIAS Connect to VSS only when All of the VLC0-VLC2

pins are unused, otherwise, open.
XT1 Connect to VSS or VDD
XT2 Open
AVREF Connect to VSS
AVSS Connect to VSS
AN0-AN5 Connect to VSS or VDD

3.4 RECOMMENDED PROCESSING OF UNUSED PINS

Connect to VSS

TYPE Y

N–ch

IN

P–ch

AV

SS

V

DD

V

DD

AV

SS

Sampling

C

+

–

input
enable

Reference voltage
(from a voltage tap of series
resistor string)

TYPE Z

IN

AV

SS

Reference voltage

15

µ

PD75328

3.5 SELECTION OF MASK OPTION

The following mask operations are available and can be specified for each pin.

Table 3-1 Mask Option Selection

Pin Mask Option Remarks

P40-P43,
P50-P53

With voltage dividing Without voltage dividing Specification in 4-bit
resistor for LCD drive resistor for LCD drive units
power source power source

With feed back resistor Without feed back resistor

XT1, XT2 (when using the subsystem (when using the subsystem

clock) clock)

With pull-up resistor Without pull-up resistor

Specification in bit units

3.6 NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test
mode, in which the internal fuctions of the µPD75328 are tested, is provided to the P00/INT4 and RESET
pins.

If a voltage exceeding VDD is applied to either of these pins, the µPD75328 is put into test mode.
Therefore, even when the

µ

PD75328 is in normal operation, if noise exceeding the VDD is input into any

of these pins, the

µ

PD75328 will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked
up and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise
cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

• Connect a diode having a low V

F across

P00/INT4 and RESET, and V

DD.

• Connect a capacitor across P00/INT4 and

RESET, and VDD.

VLC0-VLC2
BIAS

VDD

VDD

P00/INT4, RESET

VDD

VDD

P00/INT4, RESET

Low VF

diode

★

16

µ

PD75328

Fig. 4-1 Program Memory Map

4. MEMORY CONFIGURATION

• Program memory (ROM) ... 8064 words × 8 bits

• 0000H, 0001H : Vector table to which address from which program is started is written after reset

• 0002H-000BH : Vector table to which address from which program is started is written after interrupt

• 0020H-007FH : Table area referenced by GETI instruction

• Data memory

• Data area .... 512 words × 4 bits (000H–1FFH)

• Peripheral hardware area .... 128 words × 4 bits (F80H–FFFH)

765

MBE 0 0

MBE 0 0

MBE 0 0

MBE 0 0

MBE 0 0

MBE 0 0

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 5 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 5 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 5 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH
0800H

0FFFH
1000H

1F7FH

GETI instruction reference table

0

BRCB

! caddr

instruction

branch

address

CALLF

!faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(–15 to –1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

17

µ

PD75328

Data area

Static RAM

(512 x 4)

Stack area

(8 x 4)

000H

007H

256 x 4

(248 x 4)

0FFH

100H

1EBH

Bank 0

256 x 4

(236 x 4)

Not provided

128 x 4

F80H

FFFH

Peripheral hardware area

Bank 15

Bank 1

(20 x 4)

1ECH

1FFH

General-purpose

register

area

Display

data

memory

008H

Fig. 4-2 Data Memory Map

18

µ

PD75328

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

I/O ports are classified into the following 4 kinds:

• CMOS input (PORT0, 1) : 8

• CMOS input/output (PORT2, 3, 6, 7, and 8) : 20

• CMOS output (BP0-BP7) : 8

• N-ch open-drain input/output (PORT4, 5) : 8

Total : 44

Table 5-1 Port Function

Remarks

Multiplexed with INT4,
SCK, SO/SB0, and SI/SB1

Multiplexed with INT0­INT2 and TI0

Multiplexed with PTO0,
PCL, and BUZ

Multiplexed with KR4-KR7

—

Multiplexed with LCDCL
and SYNC

Multiplexed with KR0-KR3

Can be connected to a
pull-up resistor in 1-bit
units by using mask
option.

—

Port Name

PORT0

PORT1

PORT2

PORT7
PORT8

PORT3

PORT6

PORT4

*

PORT5

*

BP0-BP7

Function

4-bit input

4-bit Input/Output

4-bit Input/Output
(N-ch open-drain,
10 V)

1-bit output

Operation and Feature

Can be always read or tested regardless of
operation mode of multiplexed pin.

Can be set in input or output mode in 4-bit units.
Ports 6 and 7 are used in pairs to input/output data
in 8-bit units.

Can be set in input or output mode in 1-bit units.

Can be set in input or output mode in 4-bit units.
Ports 4 and 5 are used in pairs to input/output data
in 8-bit units.

Output data in 1-bit units. Can be used as LCD drive
segment output pins S24-S31 through software.

*: Can directly drive LED.

19

µ

PD75328

5.2 CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC)

and system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.

• 0.95

µ

s, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

• 122

µ

s (subsystem clock: 32.768 kHz)

*: instruction execution.

Remarks 1: f

X = Main system clock frequency

2: f

XT = Subsystem clock frequency

3: Φ= CPU clock
4: PCC: Processor clock control register
5: SCC: System clock control register
6: One clock cysle (t

CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 10. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

VDD

VDD

XT1

XT2

X1

X2

f

XT

fX

LCD controller
/driver
Watch timer

Subsystem

clock

oscillator

Main system

clock

oscillator

1/2 1/16

1/8 to 1/4096

Frequency divider

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· LCD controller/driver

· A/D converter

· INT0 noise rejecter circuit

· Clock output circuit

Internal bus

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

HALT*

STOP*

4

PCC2, PCC3

clear signal

STOP F/F

QS

R

Q

S

R

HALT F/F

Oscillator

disable

signal

Frequency

divider

1/4

Selector

Selector

Φ

· CPU

· INT0 noise
rejecter circuit

· Clock output
circuit

Wait release
signal from BT

RESET signal
Standby release

signal from interrupt
control circuit

★

20

µ

PD75328

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the

remote control output, peripheral LSIs, etc.

Fig. 5-2 Clock Output Circuit Configuration

Remarks:

A measures to prevent outputting narrow width pulse when selecting clock output
enable/disable is taken.

Selector

Output
buffer

PCL/P22

Bit 2 of PMGBPORT2.2

Port 2 input/
output mode
specification
bit

P22 output
latch

Internal bus

CLOM3 0 CLOM1 CLOM0 CLOM

4

Φ

f

X

/2

3

fX/2

4

fX/2

6

From the

clock

generator