NEC UPD75048GC-XXX-AB8, UPD75048CW-XXX Datasheet

The mark ★ shows major revised points.

Document No. IC - 2518C

(O. D. No. IC - 7931C) Date Published February 1994 P Printed in Japan

 NEC Corporation 1990

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75048

4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATIONS

• Consumer electronics products, telephones, cameras, automobile audio equipment, electronics measurement

equipment, etc.

ORDERING INFORMATION

Part Number Package Quality grade

µ

PD75048CW-xxx 64-pin plastic shrink DIP (750 mil) Standard

µ

PD75048GC-xxx-AB8 64-pin plastic QFP ( 14mm) Standard

Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

DESCRIPTION

The µPD75408 is a 4-bit single-chip microcomputer whose data processing capability is comparative to that

of an 8-bit microcomputer.

The

µ

PD75048 employs a CPU whose minimum instruction execution time is 0.95 µs, and contains the EEPROM, A/D converter, multi-function timer, and high performance hardware to provide high cost to performance ratio.

Detailed functions are described in the following user's manual. Read this manual when designing your

system.

µ

PD75048 User's Manual: IEU-704

FEATURES

• Built-in EEPROM: 1024 x 4 bits (data memory area)

• Built-in 8-bit resolution A/D converter (successive

approximation): 8 channels

• Capable of operating at low voltage: V

DD = 2.7 to

6.0 V

• Reference voltage can be arbitrarily specified between AV

REF+ and AVREF-.

• Built-in multi-function timer which can provide the

following functions:

• 8-bit timer

• PWM output

• 16-bit free running timer

• 16-bit integration type A/D converter counter

• I/O ports: 48 pins

• Middle voltage N-ch open drain input/output ports: 12 pins

• 43 I/O lines can be provided with internal pulldown resistors

• PROM version is available:

µ

PD75P048

(One-time PROM)

2

µ

PD75048

FUNCTIONAL OUTLINE

Item Function Instructions 41 Instruction Exe- • With main system clock: 0.95, 1.91, 15.3 µs (at 4.19 MHz)

cution Time • With subsystem clock: 122 µs (at 32.768 kHz)

Program memory (ROM) : 8064 x 8 bits

Internal Memory

Data memory (RAM) : 512 x 4 bits Data memory (EEPROM) : 1024 x 4 bits

• Retains data in case of power failure

EEPROM

• Number of writes: 100,000 times

• Write time: 10 ms

• Write end, overwrite interrupt functions

General-Purpose • 4-bit manipulation: 8 (X, A, B, C, D, E, H, L) Register • 8-bit manipulation: 4 (XA, BC, DE, HL)

• Bit accumulator (CY)

Accumulator • 4-bit accumulator (A)

• 8-bit accumulator (XA)

• Abundant bit manipulation instructions

• Efficient 4-bit data manipulation instructions

Instruction Set

• 8-bit data manipulation instructions

• GETI instruction executing 2-/3-byte instruction with a single byte 12 Input pin Via software,

24 CMOS I/O pin (direct LED drive: 4)

w/pull-up resistor: 27

I/O Line 48

w/pull-down resistor: 4

12 Medium-voltage N-ch By mask option,

open-drain I/O (direct LED drive) w/pull-up resistor: 12

• 8-bit timer/event counter

• Clock source: 4 steps

• Can count events

• 8-bit basic interval timer

• Reference time generation: 1.95, 7.82, 31.3, 250 ms (at 4.19 MHz)

• Can be used as watchdog timer

• Clock timer

Timer 4 chs • Generates 0.5-second time intervals

• Count clock source: main system clock or subsystem clock (selectable)

• Clock fast forward mode (generates 3.9-ms time intervals)

• Buzzer output (2, 4, 32 kHz)

• Multi-function timer Can be used as:

• 8-bit timer

• PWM output

• 16-bit free-running timer

• Counter for 16-bit integral A/D converter

• Three modes:

8-bit Serial • 3-line serial I/O mode ... MSB/LSB first (selectable) Interface • 2-line serial I/O mode

• SBI mode

Bit Sequential Special bit manipulation memory: 16 bits Buffer • Ideal for remote controller

Timer/event counter output (PTO0): output of square wave at specified frequency

Clock Output

Clock output (PCL): Φ/, fx/23, fx/24, fx/2

6

Function

Buzzer output (BUZ): 2, 4, 32 kHz (with main system clock or subsystem clock)

3

µ

PD75048

(cont'd)

Item Function

8-bit resolution A/D converter (successive approximation type): 8 channels

A/D Converter

• Low-voltage operation: VDD = 2.7 – 6.0 V

• Reference voltage setting range: AVREF+ – AVREF–

2.5 V ≤ (AVREF+) – (AVREF–) ≤ 6.0 V

Vector Interrupt External: 3, Internal: 6 Test Input External: 1, Internal: 1 System Clock • Ceramic/crystal oscillator circuit for main system clock oscillation

Oscillator Circuit • Crystal oscillator circuit for subsystem clock oscillation

Standby Function

• STOP mode: main system clock oscillation stops

• HALT mode: system clock oscillation continues (clock supply to CPU stops)

Package

• 64-pin plastic shrink DIP (750 mil)

• 64-pin plastic QFP ( 14 mm)

4

µ

PD75048

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 5

2. BLOCK DIAGRAM ......................................................................................................................8

3. PIN FUNCTIONS ........................................................................................................................9

3.1 PORT PINS ........................................................................................................................................9

3.2 NON PORT PINS ............................................................................................................................ 11

3.3 PIN INPUT/OUTPUT CIRCUIT ...................................................................................................... 13

3.4 SELECTION OF MASK OPTIONS................................................................................................. 16

3.5 PROCESSING OF UNUSED PINS ................................................................................................ 17

4. MEMORY CONFIGURATION ................................................................................................. 18

5. EEPROM....................................................................................................................................21

6. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 22

6.1 PORT ............................................................................................................................................... 22

6.2 CLOCK GENERATOR CIRCUIT ..................................................................................................... 23

6.3 CLOCK OUTPUT CIRCUIT............................................................................................................. 24

6.4 BASIC INTERVAL TIMER .............................................................................................................. 25

6.5 WATCH TIMER ............................................................................................................................... 26

6.6 TIMER/EVENT COUNTER............................................................................................................. 27

6.7 SERIAL INTERFACE....................................................................................................................... 29

6.8 A/D CONVERTER .......................................................................................................................... 31

6.9 MULTI-FUNCTION TIMER (MFT) ................................................................................................. 32

6.10 BIT SEQUENTIAL BUFFER ........................................................................................................... 34

7. INTERRUPT FUNCTIONS ....................................................................................................... 34

8. STANDBY FUNCTIONS .......................................................................................................... 36

9. RESET FUNCTION .................................................................................................................. 37

10. INSTRUCTION SET ................................................................................................................. 39

11. ELECTRICAL SPECIFICATIONS ............................................................................................. 45

12. PERFORMANCE CURVE......................................................................................................... 59

13. PACKAGE DRAWINGS ........................................................................................................... 61

14. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 63

APPENDIX A. COMPARISON BETWEEN µPD75048 AND 75028/75008 FUNCTIONS ..........64

APPENDIX B. DEVELOPMENT TOOLS ....................................................................................... 65

5

µ

PD75048

1. PIN CONFIGURATION (TOP VIEW)

• 64-PIN PLASTIC SHRINK DIP (750 mil)

SB1/SI/P03

SB0/SO/P02

SCK/P01

INT4/P00

BUZ/P23

PCL/P22

PCO/P21

PTO0/P20 MAT/P103 MAZ/P102

MAI/P101

MAR/P100

RESET

X1

X2

IC

XT1

XT2

V

DD

AVDD

AVREF+

AVREF–

AN7 AN6 AN5

AN4 AN3/P113 AN2/P112

AN1/P111

AN0/P110

AV

SS

TI0/P13

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

V

SS

P30 P31 P32 P33 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2

µPD75048CW–

· · ·

IC : Internally Connected (Connect directly to VDD)

XXX

6

µ

PD75048

• 64-PIN PLASTIC QFP ( 14 mm)

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PPO/P21

PCL/P22

BUZ/P23

INT4/P00

SCK/P01

SB0/SO/P02

SB1/SI/P03

V

SS

P30

P31

P32

P33

P40

P41

P42

P43

AN6

AN5

AN4

AN3/P113

AN2/P112

AN1/P111

AN0/P110

AV

SS

TI0/P13

P12/INT2

P11/INT1

P10/INT0

P93

P92

P91

P90

P83

P82

P81

P80

P73/KR7

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

P53

P52

P51

P50

AN7

AV

REF

–

AV

REF

+

AV

DD

V

DD

XT2

XT1

IC

X2

X1

RESET

MAR/P100

MAI/P101

MAZ/P102

MAT/P103

PTO0/P20

µPD75048GC–

· · ·

–AB8

IC : Internally Connected (Connect directly to VDD)

XXX AB8

7

µ

PD75048

PIN IDENTIFICATION

P00-03 : Port0 : Port 0 P10-13 : Port1 : Port 1 P20-23 : Port2 : Port 2 P30-33 : Port3 : Port 3 P40-43 : Port4 : Port 4 P50-53 : Port5 : Port 5 P60-63 : Port6 : Port 6 P70-73 : Port7 : Port 7 P80-83 : Port8 : Port 8 P90-93 : Port9 : Port 9 P100-103 : Port10 : Port 10 P110-113 : Port11 : Port 11 KR0-7 : Key Return : Key interrupt input SCK : Serial Clock : Serial clock input/output SI : Serial Input : Serial data input SO : Serial Output : Serial data output SB0, 1 : Serial Bus 0, 1 : Serial bus input/output RESET : Reset Input : Reset input TI0 : Timer Input 0 : External event pulse input PTO0 : Programmable Timer Output 0 : Timer/event counter output BUZ : Buzzer Clock : Arbitrary frequency output PCL : Programmable Clock : Clock output INT0,1,4 : External Vectored Interrupt 0, 1, 4 : External vector interrupt input INT2 : External Test Input 2 : External test input X1, 2 : Main System Clock Oscillation 1, 2 : Main system clock oscillation pin XT1, 2 : Subsystem Clock Oscillation 1, 2 : Subsystem clock oscillation pin MAR : Reference Integration Control : Reference integration signal output MAI : Integration Control : Integration signal output MAZ : Autozero Control : Autozero signal output MAT : External Comparate Timing Input : External comparator signal input PPO : Programmable Pulse Output ... : Pulse output ... MFT timer mode

: MFT timer mode

AN0-7 : Analog Input 0-7 : Analog input AV

REF+ : Analog Reference (+) : Analog reference voltage (+) input (AVDD)

AV

REF- : Analog Reference (-) : Analog reference voltage (-) input (AVSS)

AV

DD : Analog VDD : A/D converter positive power supply

AV

SS : Analog VSS : A/D converter GND

V

DD : Positive Power Supply : Positive power supply

V

SS : Ground : GND

Remarks

: MFT: Multi-function timer

MFT A/D mode

8

µ

PD75048

BIT SEQ. BUFFER

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT 10

PORT 11

P00–P03

P10–P13

P20–P23

P30–P33

P40–P43

P50–P53

P60–P63

P70–P73

P80–P83

P90–P93

P100–P103

P110–P113

SP

BANK

CY

DATA MEMORY

GENERAL REG.

RAM

512 × 4 BITS

EEPROM

1024 × 4 BITS

CPU CLOCK

Φ

STAND BY CONTROL

CLOCK GENERATOR

MAIN

SUB

CLOCK

DIVIDER

CLOCK OUTPUT CONTROL

fx/2

N

PCL/P22

XT1 XT2

X1

X2

RESETV

SS

V

DD

DECODE

AND

CONTROL

ROM

PROGRAM

MEMORY

8064×8 BITS

ALU

PROGRAM COUNTER

BASIC INTERVAL TIMER

TIMER /COUNTER

#0

INTBT

INTT0

SERIAL INTERFACE

INTCSI

INTERRUPT CONTROL

WATCH TIMER

INTW

A/D CONVERTER

MULTI– FUNCTION TIMER

INTMFT

PPO/P21

MAT/P103

MAZ/P102

MAI/P101

MAR/P100

AN0–AN3/P110–P113

AN4–AN7

AV

SS

AV

REF

–

AV

REF

+

AV

DD

BUZ/P23

KR0–KR3/P60–P63 KR4–KR7/P70–P73

INT4/P00

INT2/P12

INT1/P11

INT0/P10

SCK/P01

SO/SB0/P02

SI/SB1/P03

PTO0/P20

TI0/P13

4

8

2. BLOCK DIAGRAM

9

µ

PD75048

3. PIN FUNCTIONS

3.1 PORT PINS

Input/

Output

Circuit

TYPE*

1

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30*

2

P31*

2

P32*

2

P33*

2

P40-43*

2

P50-53*

2

Pin Name

Input/Output Function 8-Bit I/O When Reset

Also Served As

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

INT4

SCK

SO/SB0

SO/SB1

INT0

INT1

INT2

TI0

PTO0

PPO

PCL

BUZ

—

4-bit input/output port(PORT0) Pull up resistros can be specified in 3-bit units for the P01 to P03 pins by software.

With noise elimination function

4-bit input port(PORT1) Internal pull-up resistors can be specified in 4-bit units by software.

4-bit input/output port(PORT2) Internal pull-up resistors can be specified in 4-bit units by software.

Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.

N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in 4-bit units (by mask option). Resistive voltage is 10V in the opendrain mode.

N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode.

Input

B

F -A

F -B

M -C

B -C

E -B

M

X

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

High level (with internal pull-up register) or high impedance

10

µ

PD75048

P60

P61

P62

P63

P70

P71

P72

P73

P80-83

P90-93

P100

P101

P102

P103

P110

P111

P112

P113

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

—

MAR

MAI

MAZ

MAT

AN0

AN1

AN2

AN3

Also Served

As

(cont'd)

Input/

Output

Circuit

TYPE*

1

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input

Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.

Input

F -A

4-bit input/output port(PORT7) Internal pull-up resistors can be specified in 4-bit units by software.

Input

F -A

Input

4-bit input/output port(PORT8) Internal pull-up resistors can be specified in 4-bit units by software.

E-B

Input

E-D

X

4-bit input/output port(PORT9) Internal pull-down resistors can be specified in 4-bit units by software.

N-ch open-drain 4-bit input/output port (PORT10) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode.

M

4-bit input port(PORT11)

Input

Y-A

X

*1: Circles indicate Schmitt trigger inputs.

Pin Name Input/Output Function 8-Bit I/O When Reset

High level (with internal pull-up resistor) or high impedance

11

µ

PD75048

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60-63

P70-73

P100

P101

P102

P103

P21

Pin Name Input/Output

Also Served As

Functon When Reset

Input/

Output

Circuit

TYPE*

1

3.2 NON PORT PINS

Input Input/

Output Input/

Output

Input

Input/ Output

Timer/event counter external event pulse input

Timer/event counter output

Clock output

Arbitrary frequency output(for buzzer or for trimming the system clock)

Serial clock input/output

Serial data output Serial bus input/output

Serial data input Serial bus input/output

Edge detection vector interrupt input (both rising and falling edge detection are effective)

Edge detection vector interrupt input (detection edge is selectable)

Edge detection vector interrupt input (rising edge is detected.)

Clock synchronous

Asynchronous

Parallel falling edge detection testable input

In the MFT integration type A/ D converter mode

In the MFT timer mode

Reference integration signal output

Integration signal output

Auto zero signal output

Comparator input

Timer pulse output

Input

*2

Input

B - C

E - B

F - A

F - B

M - C

B

B - C

F - A

M

E - B

*1:

Circles indicate Schmitt trigger inputs.

2:

High level (with internal pull-up resistor) or high impedence

Remarks:

MFT: Multi-function timer

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0-KR3

KR4-KR7

MAR

MAI

MAZ

MAT

PPO

12

µ

PD75048

—

(cont'd)

Input/

Output

Circuit

TYPE*

1

Also Served

As

Input

—

Pins only for A/D converter

Input

—

Y-A

Y

Z-A

—

8-bit analog input

Reference voltage input (AVDD side)

Reference voltage input (AVSS side)

Positive power supply

GND

A crystal/ceramic resonator for the main system clock is connected across these pins. When using the external clock, the X1 pin inputs the external clock, and the X2 pin inputs the reverse phase of the external clock signal.

Input

—

A crystal resonator for the subsystem clock is connected across these pins. When using the external clock, the XT1 pin inputs the external clock, and the XT2 pin inputs the reverse phase of the external clock signal. The XT1 pin can be used as a 1-bit input(test) pin.

System reset input

B

—

Internally Connected. Should be connected directly to VDD.

Positive power supply

GND

—

*1: Circles indicate Schmitt trigger inputs.

Input

Pin Name Input/Output Function When Reset

AN0-AN3

AN4-AN7

AVREF+

AVREF-

AVDD

AVSS

X1, X2

XT1, XT2

RESET

IC

VDD

VSS

13

µ

PD75048

3.3 PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the µPD75048.

TYPE A (for TYPE E–B)

TYPE D (for TYPE E–B, F-A)

TYPE B

TYPE E–B

IN

V

DD

P–ch

N–ch

Input buffer of CMOS standard

data

output disable

OUT

P–ch

N–ch

Push–pull output that can be set in the output high–impedance state (both P–ch and N–ch are off)

IN

Schmitt trigger input with hysteresis characteristics

data

output disable

Type D

Type A

P.U.R. enable

V

DD

P.U.R.

P–ch

IN/OUT

P.U.R. : Pull–Up Resistor

V

DD

14

µ

PD75048

P.U.R. enable

V

DD

P.U.R.

P–ch

TYPE B–C

TYPE E–D

TYPE F–A

TYPE M–C

IN

data

output disable

P.U.R. enable

V

DD

P.U.R.

IN/OUT

P.U.R. : Pull–Up Resistor

P–ch

data

output disable

Type D

Type B

P.U.R. enable

V

DD

P.U.R.

P–ch

IN/OUT

P.U.R. : Pull–Up Resistor

N-ch

P.U.R. : Pull–Up Resistor P.D.R. : Pull–Down Resistor

P.U.R. enable

P.D.R.

N–ch

data

output disable

Type D

IN/OUT

Type A

15

µ

PD75048

TYPE F–B

TYPE Y

TYPE M

TYPE Y–A

data

output disable

P.U.R. enable

V

DD

IN/OUT

Middle voltage input buffer

(resistive voltage: +10 V)

N-ch (resistive voltage: +10 V)

P.U.R. : Pull–Up Resistor

data

output disable

P.U.R. enable

V

DD

P.U.R.

P–ch

N-ch

P-ch

output disable

(P)

output disable

(N)

V

DD

(Mask Option)

P.U.R. : Pull–Up Resistor

N–ch

IN

P–ch

AV

SS

AV

DD

AV

DD

AV

SS

Sampling

C

+

–

input enable

Reference voltage (from a voltage tap of series resistor string)

N–ch

IN

P–ch

AV

SS

AV

DD

AV

DD

AV

SS

Sampling

C

+

–

Reference voltage (from a voltage tap of series resistor string)

Input buffer

IN instruction

IN/OUT

16

µ

PD75048

AV

REF

+

AV

REF

–

Reference voltage

TYPE Z–A

3.4 SELECTION OF MASK OPTIONS

The following mask options are available:

Pin Mask Option

P40 - P43, 1 w/pull-up resistor 2 w/o pull-up resistor P50 - P53, (can be specified bitwise) (can be specified bitwise) P100 - P103

1 w/feedback resistor 2 w/o feedback resistor

XT1, XT2

(with subsystem clock used) (without subsystem clock used)

17

µ

PD75048

3.5 PROCESSING OF UNUSED PINS

Pin Recommended Condition P00/INT4 Connect to Vss P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PPO P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 Input: Connect to VSS or VDD P70/KR4-P73/KR7 Output:Open P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 AVREF+ AVREF- Connect to VSS AVSS AVDD Connect to VDD XT1 Connect to VSS or VDD XT2 Open IC Connect directly to VDD

Connect to VSS

Connect to VSS or VDD

★

18

µ

PD75048

4. MEMORY CONFIGURATION

• Program memory (ROM)...8064 x 8 bits (0000H-1F7FH)

• 0000H, 0001H: Vector table to which address from which program is started is written after reset

• 0002H-000FH: Vector table to which address from which program is started is written after interrupt

• 0020H-007FH: Table area referenced by GETI instruction

• Data memory

• Data area

Static RAM....512 x 4 bits (000H-1FFH)

EEPROM....1024 x 4 bits (400H-7FFH)

• Peripheral hardware area....128 x 4 bits (F80H-FFFH)

19

µ

PD75048

Fig. 4-1 Program Memory Map

765

MBE 0 0

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 5 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 5 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 5 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

INTMFT start address (upper 5 bits)

INTMFT start address (lower 8 bits)

INTEE/INTOW start address (upper 5 bits)

INTEE/INTOW start address (lower 8 bits)

MBE 0 0

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

0020H

007FH 0080H

07FFH 0800H

0FFFH 1000H

1F7FH

GETI instruction reference table

0

BRCB

! caddr

instruction

branch

address

CALLF ! faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction subroutine

entry address

BR $addr

instruction

relational

branch address

(–15 to –1, +2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

BRCB

! caddr

instruction

branch

address

20

µ

PD75048

Data memory

(8 × 4)

256 × 4

(248 × 4)

256 × 4

Unmapped

256 × 4

Unmapped

128 × 4

Memory bank

000H

007H

0FFH 100H

1FFH

400H

4FFH 500H

5FFH 600H

6FFH 700H

7FFH

F80H

FFFH

0

1

4

5

6

7

15

General-purpose

register area

Stack area

Data area Static RAM (512 × 4)

Data area EEPROM (1024 × 4)

Peripheral hardware area

Fig. 4-2 Data Memory Map

21

µ

PD75048

5. EEPROM

The µPD75048 contains the 1024-word x 4-bit EEPROM (Electrically Erasable PROM). The EEPROM of the

µ

PD75048 has the following characteristics.

• The EEPROM can retain its contents even if the power is turned off.

• In the same manner as the static RAM, data can be manipulated (auto-erase/write/read) in 4-bit or 8-bit units by using a memory manipulation instruction

• The contens of EEPROM are automatically erased or written by hardware, so that the overhead of the software is alleviated.

• Write time .... 10 ms.

• Number of write operation100,000 times (guaranteed).

• Write operation can be controlled by interrupt.

• When write operation is completed an interrupt occurs.

• When overwrite is executed. (Write operation is executed during write operation)

• Whether or not the EEPROM is possible to be written can be checked by individually checking the write status flag.