Page 1
MM54HC164/MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM54HC164/MM74HC164 utilizes advanced silicongate CMOS technology. It has the high noise immunity and
low consumption of standard CMOS integrated circuits. It
also offers speeds comparable to low power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip flop. Inputs A
& B permit complete control over the incoming data. A low
at either or both inputs inhibits entry of new data and resets
the first flip flop to the low level at the next clock pulse. A
high level on one input enables the other input which will
then determine the state of the first flip flop. Data at the
serial inputs may be changed while the clock is high or low,
but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out
of the 8-Bit register during the positive going transition of
the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
Features
Y
Typical operating frequency: 50 MHz
Y
Typical propagation delay: 19 ns (clock to Q)
Y
Wide operating supply voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 80 mA maximum (74HC
Series)
Y
Fanout of 10 LS-TTL loads
and ground.
CC
MM54HC164/MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
January 1988
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5315– 1
Top View
Order Number MM54HC164 or MM74HC164
Truth Table
Inputs Outputs
Clear Clock A B QAQB... Q
LXXXLL L
HLXXQ
H
H
H
HeHigh Level (steady state), LeLow Level (steady state)
e
X
Irrelevant (any input, including transitions)
e
Transition from low to high level.
u
Q
AO,QBO,QHO
indicated steady state input conditions were established.
e
Q
the clock; indicated a one-bit shift.
The level of QAor QGbefore the most recentutransition of
An,QGn
HH H Q
u
LX L Q
u
XL L Q
u
e
the level of QA,QB,orQH, respectively, before the
AOQBO
An
An
An
Q
Q
Q
Q
TL/F/5315– 2
H
HO
Gn
Gn
Gn
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5315
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C
C
2
Page 3
AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REM
t
S
t
H
t
W
Maximum Operating 30 MHz
Frequency
Maximum Propagation 19 30 ns
Delay, Clock to Output
Maximum Propagation 23 35 ns
Delay, Clear to Output
Minimum Removal Time,
Clear to Clock
Minimum Setup Time 12 20 ns
Data to Clock
Minimum Hold Time 1 5 ns
Clock to Data
Minimum Pulse Width 10 16 ns
Clear or Clock
e
A
b
20 ns
25§C, C
Guaranteed
e
L
Limit
15 pF, t
r
e
Units
e
t
6ns
f
AC Electrical Characteristics C
e
L
Symbol Parameter Conditions V
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REM
t
S
t
H
t
W
t
THL,tTLH
tr,t
f
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Operating 2.0V 5 4 3 MHz
Frequency 4.5V 27 21 18 MHz
Maximum Propagation 2.0V 115 175 218 254 ns
Delay, Clock to Output 4.5V 13 35 44 51 ns
Maximum Propagation 2.0V 140 205 256 297 ns
Delay, Clear to Output 4.5V 28 41 51 59 ns
Minimum Removal Time 2.0Vb70 0 0 ns
Clear to Clock 4.5V
Minimum Setup Time 2.0V 25 100 125 150 ns
Data to Clock 4.5V 14 20 25 30 ns
Minimum Hold Time 2.0Vb25 5 5 ns
Clock to Data 4.5V 0 5 5 5 ns
Minimum Pulse Width 2.0V 22 80 100 120 ns
Clear or Clock 4.5V 11 16 20 24 ns
Maximum Output 2.0V 75 95 110 ns
Rise and Fall Time 4.5V 15 19 22 ns
Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
Power Dissipation (per package) 5.0V 150 pF
Capacitance (Note 5)
Maximum Input 5 10 10 10 pF
Capacitance
D
e
CC
e
t
6 ns (unless otherwise specified)
r
f
e
T
25§C
A
eb
T
A
74HC 54HC
40 to 85§CT
eb
A
55 to 125§C
50 pF, t
Typ Guaranteed Limits
6.0V 31 24 20 MHz
6.0V 20 30 38 44 ns
6.0V 24 35 44 51 ns
b
30 0 0 ns
b
6.0V
20 0 0 ns
6.0V 12 17 21 25 ns
6.0V 1 5 5 5 ns
6.0V 10 14 18 20 ns
6.0V 13 16 19 ns
6.0V 400 400 400 ns
2
e
CPDV
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
Page 4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC164J or MM74HC164J
NS Package Number J14A
Molded Dual-In-Line Package (N)
MM54HC164/MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
LIFE SUPPORT POLICY
Order Number MM74HC164N
NS Package Number N14A
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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Tel: 1(800) 272-9959 Deutsch Tel: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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