National Semiconductor MM54HC181, MM74HC181 Service Manual

MM54HC181/MM74HC181
Arithmetic Logic Units/Function Generators

General Description

These arithmetic logic units (ALU)/function generators uti­lize advanced silicon-gate CMOS technology. They possess
the high noise immunity and low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 10 LS-TTL loads.

The MM54HC181/MM74HC181 are arithmetic logic unit
(ALU)/function generators that have a complexity of 75
equivalent gates on a monolithic chip. These circuits per­form 16 binary arithmetic operations on two 4-bit words as
shown in Tables 1 and 2. These operations are selected by
the four function-select lines (S0, S1, S2, S3) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal car­ries must be enabled by applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
made available in these devices for fast, simultaneous carry
generation by means of two cascade-outputs (pins 15 and

17) for the four bits in the package. When used in conjunc­tion with the MM54HC182 or MM74HC182, full carry look­ahead circuits, high-speed arithmetic operations can be per­formed. The method of cascading HC182 circuits with these
ALU’s to provide multi-level full carry look-ahead is illustrat­ed under typical applications data for the MM54HC182/
MM74HC182.

If high speed is not of importance, a ripple-carry input (C
and a ripple-carry output (C
the ripple-carry delay has also been minimized so that arith­metic manipulations for small word lengths can be per­formed without external circuitry.

Features

Y

Full look-ahead for high-speed operations on
long words

Y

Arithmetic operating modes:
Addition
Subtraction
Shift operand a one position magnitude comparison
Plus twelve other arithmetic operations

Y

Logic function modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations

Y

Wide operating voltage range: 2V –6V

Y

Low input current: 1 mA maximum

Y

Low quiescent current: 80 mA maximum

January 1988

a

4) are available. However,

n

MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators

)

n

Connection Diagram

Dual-In-Line Package

Top View

Order Number MM54HC181 or MM74HC181

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/5320

TL/F/5320– 1

Pin Designations

Designation Pin Nos. Function

A3, A2, A1, A0 19, 21, 23, 2 Word A Inputs

B3, B2, B1, B0 18, 20, 22, 1 Word B Inputs

S3, S2, S1, S0 3, 4, 5, 6

C

n

M8

F3, F2, F1, F0 13, 11, 10, 9 Function Outputs

AeB 14 Comparator Outputs

P15

a

C

4 16 Inv. Carry Output

n

G17

V

CC

GND 12 Ground

7 Inv. Carry Input

24 Supply Voltage

Function-Select

Inputs

Mode Control

Input

Carry Propagate

Output

Carry Generate

Output

General Description (Continued)

These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown below.

Subtraction is accomplished by 1’s complement addition
where the 1’s complement of the subtrahend is generated
internally. The resultant output is AÐBÐ1, which requires
an end-around or forced carry to produce AÐB.

The 181 can also be utilized as a comparator. The A

e

output is internally decoded from the function outputs (F0,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A
mode with C

e

A

B output is open-drain so that it can be wire-AND con-

e

B). The ALU should be in the subtract

e

H when performing this comparison. The

n

nected to give a comparison for more than four bits. The
carry output (C
magnitude information. Again, the ALU should be placed in

) can also be used to supply relative

na4

the subtract mode by placing the function select inputs S3,
S2, S1, S0 at L, H, H, L, respectively.

These circuits have been designed to not only incorporate
all of the designer’s requirements for arithmetic operations,

Pin Number 2 1 23 22 21 20 19 18 9 10 11 13 7 16 15 17

Active-High Data (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 CnC

Active-Low Data (Table 1) A0B0A1B1A2B2A3B3F0F1F2F3CnC

but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select in­puts (S0, S1, S2, S3) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic func­tions are detailed in Tables 1 and 2 and include exclusive­OR, NAND, AND, NOR, and OR functions.

B

ALU SIGNAL DESIGNATIONS

The MM54HC181/MM74HC181 can be used with the signal
designations of either

Figure 1orFigure 2

The logic functions and arithmetic operations obtained with
signal designations as in

Figure 1

are given in Table 1; those
obtained with the signal designations of
in Table 2.

The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to V

and ground.

CC

.

Figure 2

na4

na4

are given

XY

P G

FIGURE 1

Input Output Active-High Data Active-Low Data

C

n

HH A
HL A
LH A
LL A

a

C

4 (Figure 1) (Figure 2)

n

s

BA

l

BA

k

BA

t

BA

Selection

MeHM
Logic

S3 S2 S1 S0 Functions C

e

H (no carry) C

n

LLLLFeA FeAF
LLLHF
LLHLFeABF
LLHHFe0F
LHLLF

eAa

BFeAaBF

e

a

A

e

e

AB FeA Plus AB FeA Plus AB Plus 1

Minus 1 (2’s Compl) FeZero

LHLHFeB Fe(AaB) Plus AB Fe(AaB) Plus AB Plus 1
LHHLF
LHHHF

e

AZBFeA Minus B Minus 1 FeA Minus B

e

AB FeAB Minus 1 FeAB
HLL LFeAaBFeA Plus AB FeA Plus AB Plus 1
HLLHFeAZBFeA Plus B FeA Plus B Plus 1

TL/F/5320– 2

HLHLF

e

BF
HLHHFeAB FeAB Minus 1 FeAB
HHL LFe1F
HHL HF
HHHLF
HHHHF

*Each bit is shifted to the next more significant position.

eAa
eAa
e

AF

e(Aa

e

A Plus A* FeA Plus A Plus 1
BFe(AaB) Plus A Fe(AaB) Plus A Plus 1
BFe(AaB) Plus A Fe(AaB) Plus A Plus 1

e

A Minus 1 FeA

t

B

k

B

l

B

s

B

Table I

Active High Data

e

L; Arithmetic Operations

e

L (with carry)

n

e

A Plus 1

e

(AaB) Plus 1

B F

e(Aa

B) Plus 1

B) Plus AB Fe(AaB) Plus AB Plus 1

2

General Description (Continued)

Selection

S3 S2 S1 S0 Functions C

LLLLFeA FeA Minus 1 FeA
LLLHF
LLHLFeAaBFeAB Minus 1 Fe(AB)
LLHHFe1F
LHLLF
LHLHFeB FeAB Plus (AaB) FeAB Plus (AaB) Plus 1
LHHLF
LHHHF
HLLLF
HLLHFeAaBFeA Plus B FeA Plus B Plus 1
HLHLF
HLHHFeAaBFeAaBF
HHL LFe0F
HHLHF
HHHLF
HHHHF

*Each bit is shifted to the next more significant position.

eAa

eAa
eAa
e

e

e
e
e

TL/F/5320– 3

FIGURE 2

Table II

Active Low Data

MeHM

e

L; Arithmetic Operations

Logic

e

L (no carry) C

n

e

AB FeAB Minus 1 FeAB

e

Minus 1 (2’s Compl) FeZero

BFeA Plus (AaB)F

e

H (with carry)

n

e

A Plus (AaB) Plus 1

BFeA Minus B Minus 1 FeA Minus B
BFeAaB Fe(AaB Plus 1

ABF

BF

e

A Plus (AaB) FeA Plus (AaB) Plus 1

e

AB Plus (AaB) FeAB Plus (AaB) Plus 1

e

A Plus A* FeA Plus A Plus 1

e

(AaB) Plus 1

AB FeAB Plus A FeAB Plus A Plus 1
AB FeAB Plus A FeAB Plus A Plus 1
AF

e

AF

e

A Plus 1

Number Package Count Carry Method

of

Bits

Typical

Addition Times

Arithmetic/ Look Ahead
Logic Units Carry Generators

Between

ALU’s

1 to 4 20 ns 1 0 None
5 to 8 30 ns 2 0 Ripple

9 to 16 30 ns 3 or 4 1 Full Look-Ahead

17 to 64 50 ns 5 to 16 2 to 5 Full Look-Ahead

3