National Semiconductor MM54HC173, MM74HC173 Service Manual
MM54HC173/MM74HC173
TRI-STATE
General Description
The MM54HC173/MM74HC173 is a high speed TRI-STATE
QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate CMOS technology. It possesses the low power consumption and high noise immunity of standard CMOS integrated circuits, and can operate at speeds comparable to
the equivalent low power Schottky device. The outputs are
buffered, allowing this circuit to drive 15 LS-TTL loads. The
large output drive capability and TRI-STATE feature make
this part ideally suited for interfacing with bus lines in a bus
oriented system.
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The TRI-STATE outputs allow the device
to be used in bus organized systems. The outputs are
placed in the TRI-STATE mode when either of the two output disable pins are in the logic ‘‘1’’ level. The input disable
allows the flip-flops to remain in their present states without
having to disrupt the clock. If either of the 2 input disables
are taken to a logic ‘‘1’’ level, the Q outputs are fed back to
Quad D Flip-Flop
É
January 1988
the inputs, forcing the flip flops to remain in the same state.
Clearing is enabled by taking the CLEAR input to a logic ‘‘1’’
level. The data outputs change state on the positive going
edge of the clock.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
Y
Typical propagation delay: 18 ns
Y
Wide operating supply voltage range: 2 –6V
Y
TRI-STATE outputs
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 80 mA maximum (74HC)
Y
High output drive current: 6 mA minimum
MM54HC173/MM74HC173 TRI-STATE Quad D Flip-Flop
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC173 or MM74HC173
TL/F/5317– 1
Truth Table
Inputs
Clear Clock
HX X X X L
LL X XXQ
L
L
L
L
When either M or N (or both) is (are) high the output is disabled to the high-impedance state: however, sequential operation of the flip-flops is not
affected.
Hehigh level (steady state)
e
L
low level (steady state)
e
low-to-high level transition
u
e
X
don’t care (any input including transitions)
e
Q
the level of Q before the indicated steady state input condi-
O
tions were established
Data Enable Data
G1 G2 D
HXXQ
u
XHXQ
u
LLLL
u
LLHH
u
Output
Q
0
0
0
TRI-STATE
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
is a registered trademark of National Semiconductor Corp.
É
TL/F/5317
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
)
b
0.5 toa7.0V
b
1.5 to V
b
CC
0.5 to V
CC
b
65§Ctoa150§C
a
a
g
g
g
1.5V
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
6.0 mA 4.5V 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
I
CC
Maximum Input V
Current
Maximum TRI-STATE V
Output Leakage EnableeV
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
and VILoccur at V
IH
e
IN
OUT
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
6.0 mA 4.5V 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
VCCor GND 6.0V
IH
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5.0
Min Max Units
V
§
§
Units
b
b
40
55
A
eb
55 to 125§C
g
g
CC
a
85
a
125
1.0 mA
10 mA
C
C
2
Loading...