National Semiconductor MM54HC165, MM74HC165 Service Manual
MM54HC165/MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM54HC165/MM74HC165 high speed PARALLEL-IN/
SERIAL-OUT SHIFT REGISTER utilizes advanced silicongate CMOS technology. It has the low power consumption
and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from Q
clocked. Parallel inputs to each stage are enabled by a low
to QHwhen
A
level at the SHIFT/LOAD input. Also included is a gated
CLOCK input and a complementary output from the eighth
bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel load-
ing is inhibited as long as the SHIFT/LOAD input is high.
When taken low, data at the parallel inputs is loaded directly
into the register independent of the state of the clock.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
Features
Y
Typical propagation delay: 20 ns (clock to Q)
Y
Wide operating supply voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent supply current: 80 mA maximum
(74HC Series)
Y
Fanout of 10 LS-TTL loads
and ground.
CC
MM54HC165/MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
January 1988
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC165 or MM74HC165
TL/F/5316– 1
Function Table
Inputs Internal
Shift/ Clock
Load Inhibit
Clock Serial
Parallel
A...H QAQ
L X X X a...h a b h
HLLX XQ
HL
HL
HXHQANQ
u
LXLQANQ
u
HHXX XQA0QB0Q
HeHigh Level (steady state), LeLow Level (steady state)
e
X
Irrelevant (any input, including transitions)
e
Transition from low to high level
u
Q
A0,QB0,QH0
indicated steady-state input conditions were established.
Q
AN,QGN
the clock; indicates a one-bit shift.
e
The level of QA,QB,orQH, respectively, before the
e
The level of QAor QGbefore the most recentutransition of
Outputs
B
A0QB0QH0
Output
Q
H
GN
GN
H0
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5316
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current V
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
CC
e
IN
OUT
V
CC
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
2–6V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
e
2–6V
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C
C
2
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