National Semiconductor MM54HC155, MM74HC155 Service Manual

MM54HC155/MM74HC155 Dual 2-To-4
Line Decoder/Demultiplexers

General Description

The MM54HC155/MM74HC155 is a high speed silicon-gate
CMOS decoder/demultiplexer. It utilizes advanced silicon­gate CMOS technology and features dual 1-line-to-4-line
demultiplexers with independent strobes and common bina­ry-address inputs. When both sections are enabled by the
strobes, the common address inputs sequentially select and
route associated input data to the appropriate output of
each section. The individual strobes permit activating or in­hibiting each of the 4-bit sections as desired. Data applied
to input C1 is inverted at its outputs and data applied to C2
is non-inverted at its outputs. The inverter following the C1
data input permits use as a 3-to-8-line decoder, or 1-to-8­line demultiplexer, without gating.

All inputs to the decoder are protected from damage due to
electrostatic discharge by diodes to V

and Ground.

CC

The device is capable of driving 10 low power Schottky TTL
equivalent loads.

The MM54HC155/MM74HC155 is functionally and pin
equivalent to the 54LS155/74LS155 with the advantage of
reduced power consumption.

Features

Y

Applications

Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer

Y

Typical propagation delay: 22 ns

Y

Low quiescent current: 80 mA maximum
(74HC series)

Y

Wide operating range: 2V–6V

MM54HC155/MM74HC155 Dual 2-To-4 Line Decoder/Demultiplexers

January 1988

Connect and Logic Diagram

Order Number MM54HC155 or

MM74HC155

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/8364

TL/F/8364– 1

Truth Tables

Select Strobe Data

B A G1 C1 1Y0 1Y1 1Y2 1Y3

XX H X HHHH

LL L H L H H H
LH L H H L H H
HL L H H H L H
HH L H H H H L
XX X L HHHH

Select Strobe Data

B A G2 C2 2Y0 2Y1 2Y2 2Y3

XX H X HHHH

LL L L L H H H
LH L L H L H H
HL L L H H L H
HH L L H H H L
XX X H HHHH

Inputs Outputs

Select

IC B A IG 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3

XXX H HHHHHHHH
LLL L LHHHHHHH
LLH L H LHHHHHH
LHL L HH LHHHHH

LHH L HHHLHHHH
HLL L HHHHLHHH
HLH L HHHHHL HH
HHL L HHHHHHL H
HHH L HHHHHHHL

ICeinputs C1 and C2 connected together

e

inputs G1 and G2 connected together

IG

e

high level Lelow level Xedon’t care

H

2-to-4-Line Decoder

or 1-Line to 4-line Demultiplexer

Inputs Outputs

Inputs Outputs

3-Line-to-8-Line Decoder

or 1-Line-to-8-Line Demultiplexer

Strobe

Or Data

(0) (1) (2) (3) (4) (5) (6) (7)

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

)

DC Input Voltage (VIN)

DC Output Voltage (V

OUT

)

Clamp Diode Current (IIK,IOK)20mA

DC Output Current, per pin (I

)25mA

OUT

DC VCCor GND Current, per Pin (ICC)50mA

Storage Temperature Range (T

STG

)

b

1.5V to V

b

b

0.5V toa7.0V

CC

0.5 to V

CC

b

65§Ctoa150§C

a

1.5V

a

0.5V

Operating Conditions

Supply Voltage (V
DC Input or Output Voltage

(V

IN,VOUT

Operating Temperature Range (T

MM74HC
MM54HC

Input Rise/Fall Time V

(t

)V

r,tf

)26V

CC

)0V

CC
CC

V

CC

Power Dissipation (PD)

(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temp. (T

) (Soldering 10 sec) 260§C

I

DC Electrical Characteristics (Note 4)

Symbol Parameter Conditions V

CCTA

e

25§CT

Typ Guaranteed Limits

V

Minimum High Level 2.0V 1.5 1.5 1.5 V

IH

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

V

Maximum Low Level 2.0V 0.5 0.5 0.5 V

IL

Input Voltage** 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

V

V

I

I

Minimum High Level V

OH

Output Voltage

Maximum Low Level V

OL

Output Voltage

Maximum Input V

IN

Current

Maximum Quiescent V

CC

Supply Current I

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified, all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:

Note 4: For a power supply of 5V

with this supply. Worst case V

) occur for CMOS at the higher voltage and so the 6.0V values should be used.

I

OZ

**V

limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.

IL

IH

e

VIHor V

IN

s

I

20 mA 4.5V 4.5 4.4 4.4 4.4 V

l

l

OUT

e

V

VIHor V

IN

s

I

4.0 mA 6.0V 5.7 5.48 5.34 5.2 V

l

l

OUT

s

I

5.2 mA

l

l

OUT

e

VIHor V

IN

s

I

20 mA 4.5V 0 0.1 0.1 0.1 V

l

l

OUT

e

V

VIHor V

IN

s

I

4.0 mA 6.0V 0.2 0.26 0.33 0.4 V

l

l

OUT

s

I

5.2 mA

l

l

OUT

e

VCCor GND 6.0V

IN

e

VCCor GND 6.0V 8.0 80 160 mA

IN

e

0 mA

OUT

g

10% the worst case output voltages (VOHand VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing

and VILoccur at V

e

CC

2.0V 2.0 1.9 1.9 1.9 V

IL

6.0V 6.0 5.9 5.9 5.9 V

4.5V 4.2 3.98 3.84 3.7 V

IL

2.0V 0 0.1 0.1 0.1 V

IL

6.0V 0 0.1 0.1 0.1 V

4.5V 0.2 0.26 0.33 0.4 V

IL

g

0.1

b

12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§.

5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICCand

74HC 54HC

eb

40§toa85§CT

A

g

1.0

Min Max Unit

)

A

b

A

b55a

eb

e

2.0V 1000 ns

e

4.5V 500 ns

e

6.0V 400 ns

CC

40a85 C

125 C

55§toa125§C

g

1.0 mA

V

Units

2