MSI MS-7636 Schematic P31
5
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PageTitle
Cover Sheet
Block Diagram/Device Map/GPIO Table/history
CPU-CLK/Control/MISC/PEG
D D
CPU-Power
DDR III DIMM 1 / 2
,CPU-GND
,CPU-Memory
1
2, 3, 4, 5
6
,9,78
10,11
MS-7636
CPU:
INTEL - Lynnfield/ Clarkdale LGA 1156
Ver: 1.3
uATX(244mm X 240mm)
System Chipset:
CLK GEN ICS4105
PCH-PCI-E/PCI/DMI/USB/CLK
PCH-SATA/HOST/FAN/GPIO/Display
PCH-SMB/LPC/AUDIO/RTC/SPI/JTAG/RST
PCH-POWER,GND/NVRAM
PCIE x16 & x1, x1 Slots
C C
PCI SLOT
LAN-RTL8111DL
Audio Codec ALC889
JMB-368 IDE*1
VGA - D-Sub
DVI-D
USB
B B
ATX F_Panel/EMI/TPM/Buzzer/KB
ACPI Controller (uPI solution)
DDR Power - uP6103 1-Phase
PCH Power - 1P05-Linear
CPU_VTT Power - uP6103_1 Phase
GPU Power -ISL6314_1-Phase
CPU Power - uP6206 3-Phase
CPU XDP
Manual & Option parts
A A
5
12
13
14
15
16,17
18SIO-Fintek F71889F/Print Port/COM1/COM2
19
20
21
22
23
24
25
26SATA conn / FAN Control
27
28
29
30
31
32
33
34
35
36
4
INTEL-IBEXPEAK PCH (H - 55)
OnBoard Chipset:
Clock Gen:ICS 4105B
HD Audio Codec:ALC889
LAN:RTL8111D 10/100/1000
SIO:F71889
Flash ROM: 64 Mb SPI (CHIP)
Main Memory:
DDRIII (800/1066/1333MHz) * 4 (Dual Channel)
Expansion Slots:
PCI Express (X16) Slot * 1
PCI Express (X1) Slot * 2
PCI Slot *1
PWM:
Controller: uP6206
( 3-Phase use STD MOS -- 95W )
ACPI:
uPI+SIO
Other:
SATA(SATA2-300MB/s) *6
USB2.0 *10 (Rear*4 / Front*6)
PRINT Header *1
COM pin header *2
TPM Header *1
on BOARD BUZZER
D-SUB *1
DVI PORT*1
HDMI PORT*1
3
IDE X1 JMB-368
OV by uP6264 or SIO
uP6103 (CPU_VTT)
Linear (PCH)
uP6103(DDR)
GPU Power -ISL6314
BOM SKUs
H55:chiset
S:solid cap
EL:EL cap
G:giga lan 8111DL
M:Miga lan 8103EL
6: 6 ports
DVI: DVI Stuff
2
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MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
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Friday, March 19, 2010
Friday, March 19, 2010
Friday, March 19, 2010
Cover Sheet
Cover Sheet
Cover Sheet
MS-7636
1
Sheet ofDate:
13
Sheet ofDate:
13
Sheet ofDate:
13
1.3
1.3
1.3
8
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INTEL CONFIDENTIAL
4
3
2
1
D D
INTEL
PCIE
SLOT
16X
16X
FDI LINK X8
LGA 1156
DMI X4
DDRIII 1066,1333
128bit
DDRIII 1066,1333
UNBUFFERED
DDRIII DIMM1
UNBUFFERED
DDRIII DIMM2
DDRIII FIRST LOGICAL DIMM
IBEXPEAK
C C
DVI
VGA
PORT:B
RGB
PCIE
PCIE X1
SLOT
PCIE X1
SLOT
JMB-368
GIGA LAN
PCH
USB-2USB-6 USB-3USB-4USB-5
B B
USB-7
USB-8 USB-9
USB-1
USB-0
USB 2.0
H55
HD AUDIO I/F
IDE*1
Audio Codec
SPI ROM
SPI I/F
SATA II I/F
SATA#0 SATA#1 SATA#2 SATA#3
SATA#4
PCI BUS
SATA#5
PCI SLOT
#1
A A
KB/ MOUSE
COM1/Print Port
5
4
LPC I/F
SIO
MICRO-STAR INT'L CO.,LTD
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MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
MSI
MSI
MSI
Size
Size
Size
Document Description Rev
Document Description Rev
Document Description Rev
Custom
Custom
Custom
Date:
Friday, March 19, 2010
Date:
Friday, March 19, 2010
Date:
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Friday, March 19, 2010
MS-7636
Block Diagram
Block Diagram
Block Diagram
1
23
23
23
Sheet of
Sheet of
Sheet of
1.3
1.3
1.3
8
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DDR DIMM config.
Device
CHA DIMM1
CHB DIMM2
D D
Address Clock
10100001B
10100000B
MEM_MA_CLK_H0/L0 H1/L1
MEM_MB_CLK_H0/L0 H1/L1
4
3
2
1
PCI Config.
DEVICE
PCI Slot 1
TPM
MCP1 INT Pin
PCI_INT#A
PCI_INT#B
PCI_INT#C
PCI_INT#D
REQ#/GNT#
PCI_REQ0#
PCI_GNT0#
IDSEL
AD16
CLOCK
PCH
CLKOUT_PCI<0>
PCH
CLKOUT_PCI<3>
SIO
PCH
CLKOUT_PCI<2>
PCI RESET DEVICE
C C
Signals
PCIRST#_PCH
PLTRST_BU1#
PLTRST_BU2#
PLTRST_BU3#
PLTRST# SIO
B B
IBEXPEAK
Target
PCISLOT1
JMB368 IDE
PCIE*16 / *1
LAN&TPM
A A
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MS-7636
MS-7636
Device Map
Device Map
Device Map
MS-7636
1.3
1.3
1.3
Sheet ofDate:
338
Sheet ofDate:
338
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338
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4
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Friday, March 19, 2010
Friday, March 19, 2010
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5
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D D
C C
4
3
2
1
B B
A A
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
5
4
MSI
MSI
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Size Document Description Rev
Size Document Description Rev
C
C
C
Friday, March 19, 2010
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Friday, March 19, 2010
GPIO Table
GPIO Table
GPIO Table
MS-7636
1
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Sheet ofDate:
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1.3
1.3
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History
1.2009-10-13 Change VCC_SENSE to CPU_VCC_SENSE
2.2009-10-13 Add HDMI circuit,change USB circuit,JSP1 circuit update
3.2009-10-13 update NCT3016 circuit ,add VTIN3 circuit for VRM MOS
4.2009-10-18 Add C589 C590
D D
5.2009-10-18 Add R561 R562 For HDMI HPDET
6.2009-10-20 Add R602,Swap HDMI wire for layout
7.2009-10-21 NCT3016 circuit update:add R637 Q65 R592,Change U27 pin16 tp NCT_GPIO16,delete C121
8.2009-10-21A NCT3016 citcui update:add Q85,chang SATA1&SATA2 to SATA1_2
9.2009-10-23 change JUSB2 & JUSB1 for layout
10.2009-10-23A NCT3016 circuit update:add R850
11.2009-10-24 delete VCCGATE and DUALGATE circuit
12.2009-10-26 delete C534
13.2009-10-26 Swap RN40
MS-7636-1.3
C C
1.2010-02-23 Add MH7 MH8 MH9 R545
B B
A A
MICRO-STAR INT'L CO.,LTD
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MS-7636
MS-7636
5
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MSI
MSI
MSI
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Size Document Description Rev
Size Document Description Rev
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C
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Friday, March 19, 2010
History
History
History
MS-7636
1
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Sheet ofDate:
Sheet ofDate:
1.3
1.3
1.3
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8
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AA8/Y8 ,these signals for 120 MHz from the Intel?5 Series Chipset CLKOUT_DP_P /CLKOUT_BCLK1_P and CLKOUT_DP_N / CLKOUT_BCLK1_N. Leave as NC
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on the PCH and connect directly to GND at the processor. 120MHz clock is used for embedded DisplayPort which is no supported on Desktop designs.
CLK133M_CPU_P13
CLK133M_CPU_N13
CK_DMI_P13
CK_DMI_N13
BACK SIDE
D D
R178 X_49.9R/1%R178 X_49.9R/1%
CPU_VTT
CPU_PWRGD15
VTT_PGD30,35
MEM_PWRGD15
H_PECI14,18
H_THERMTRIP#14
PM_SYNC14
R296 20R/1%R296 20R/1%
R299 20R/1%R299 20R/1%
R321 100R/1%R321 100R/1%
R322 24.9R/1%R322 24.9R/1%
R324 130R/1%R324 130R/1%
R325 49.9/1%R325 49.9/1%
R214 49.9/1%R214 49.9/1%
C C
SKTOCC#18
代翴 璉
CPU_VTT
B B
R358
R358
X_3K
X_3K
R353
R353
X_3K
X_3K
R352
R352
X_3K
X_3K
CFG 0~5 HAVE INTERNAL PULL-UPS
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board. Refer to the Platform
Design Guide for pull-down recommendations
when logic low is desired.
CFG[0]: PCI Express Bifurcation:
- With all Intel?5 Series Chipsets except P55
and P57 SKUs:
Reserved (Only 1 x16 PCI Express
supported by default)
- With Intel?5 Series Chipsets P55 and P57
SKUs only:
1 = 1 x16 PCI Express
0 = 2 x8 PCI Express
- With Workstation and Server Ibex Peak:
1 = 1 x16 PCI Express
0 = 2 x8 PCI Express
CFG[1]: Reserved (Lynnfield processor PCI
Express Port Bifurcation)
CFG[2]: Reserved configuration lands. A test
point may be placed on the board for this
land.
CFG[3]: PCI Express* Static Lane
Numbering Reversal. A test point may be
placed on the board for this land. Lane
reversal will be applied across all 16 lanes.
1: No Reversal
0: Reversal
In the case of Bifurcation with NO Lane Reversal,
the physical lane mapping is as follows:
Lanes 15:8 => Port 1 Lanes 7:0
Lanes 7:0 => Port 0 Lanes 7:0
In the case of Bifurcation WITH Lane Reversal, the
physical lane mapping is as follows:
Lanes 15:8 => Port 0 Lanes 0:7
A A
Lanes 7:0 => Port 1 Lanes 0:7
CFG[6:4]: Reserved configuration lands. A
test point may be placed on the board for
this land.
CFG[17:7]: Reserved configuration lands.
Intel does not recommend a test point on the
board for this land.
PEG CONFIG TABLE
SEL2
SEL1 SEL0 PCIE CONFIG
1
1
1
1
5
CK_DMI_P
CK_DMI_N
H_TDO_TDI_M
TP1TP1
VTT_PGD
MEM_PWRGD
H_PECI
H_CATERR#
H_PROCHOT#
H_THERMTRIP#
PM_SYNC
H_COMP2
H_COMP3
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_COMP1
H_COMP0
SKTOCC#
H_MCP_CFG0
H_MCP_CFG1
H_MCP_CFG2
H_MCP_CFG3
H_MCP_CFG4
H_MCP_CFG5
H_MCP_CFG6
H_MCP_CFG7
H_MCP_CFG8
TP31TP31
H_MCP_CFG9
TP30TP30
H_MCP_CFG10
TP37TP37
H_MCP_CFG11
TP35TP35
H_MCP_CFG12
TP32TP32
H_MCP_CFG13
TP39TP39
H_MCP_CFG14
TP34TP34
H_MCP_CFG15
H_MCP_CFG16
TP38TP38
H_MCP_CFG17
TP33TP33
H_MCP_CFG0
H_MCP_CFG1
H_MCP_CFG2
H_MCP_CFG3
H_MCP_CFG4
H_MCP_CFG5
H_MCP_CFG6
H_MCP_CFG7
H_MCP_CFG15
1 1 X 16
0 2 X 8
5
Follow DG&CRB
X_COPPER
X_COPPER
CP3
CP3
X_COPPER
X_COPPER
CP2
CP2
CPU_VTT
R381
R381
X_3K
X_3K
R362
R362
X_3K
X_3K
R361
R361
X_3K
X_3K
R363
R363
X_3K
X_3K
R368
R368
X_3K
X_3K
R364
R364
X_3K
X_3K
R365
R365
X_3K
X_3K
R379
R379
X_3K
X_3K
R359 X_3KR359 X_3K
CLK133M_CPU_P
CLK133M_CPU_N
For DP port
CPURST#
PROC_PWROK
VCCP_PWRGD
TP_GFX_DPRSLPVR
TP36TP36
PM_EXT_TS0
PM_EXT_TS1
CPU1E
CPU1E
AA7
BCLK[0]
AA6
BCLK[0]*
AA3
PEG_CLK
AA4
PEG_CLK*
Y8
BCLK[1]*
AA8
BCLK[1]
AF37
TDI_M
AF38
TD0_M
AF34
RSTIN*
AH36
PROC_PWROK
AH35
VCCPWRGOOD
AG37
VTTPWRGOOD
AH37
SM_DRAMPWROK
AG35
PECI
AG39
CATERR*
AH34
PROCHOT*
AF35
THERMTRIP*
AH39
PM_SYNC
AB5
PM_EXT_TS[0]*
AB4
PM_EXT_TS[1]*
B11
COMP2
C11
COMP3
AG1
SM_RCOMP[0]
AD1
SM_RCOMP[1]
AE1
SM_RCOMP[2]
AF2
COMP1
AF36
COMP0
AK38
SKTOCC*
E8
CFG0
G8
CFG1/RSVD
E10
CFG2/RSVD
F10
CFG3/PEG_LANE_REVERSAL
H10
CFG4/RSVD
H9
CFG5/VSS
E9
CFG6/FC_E9
F9
CFG7/FC_F9
G12
CFG8/FC_G12
H12
CFG9/FC_H12
K10
CFG10/FC_K10
K8
CFG11/FC_K8
J12
CFG12/FC_J12
L8
CFG13/FC_L8
K9
CFG14/FC_K9
K12
CFG15/FC_K12
H7
CFG16/FC_H7
L11
CFG17/FC_L11
A4
RSVD
B3
RSVD
C2
RSVD
D1
RSVD
J10
GFX_DPRSLPVR/RSVD
AV38
VSS
AK12
RSVD
AK13
RSVD
AK14
RSVD
AL12
RSVD
AM15
RSVD
AM16
RSVD
AM18
RSVD
AM19
RSVD
AM20
RSVD
AM21
RSVD
AU40
RSVD
AV1
RSVD
AV39
RSVD
AW2
RSVD
AW38
RSVD
AY37
RSVD
N12-160A010-F02
H_CATERR#
PM_SYNC
H_PECI
CPU_RESET_OUT#
H_THERMTRIP#
H_PROCHOT#
XDP_CPU_PRDY#
R211 51RR211 51R
R202
R202
R203
R203
R199 51RR199 51R
R213
R213
R204
R204
R212
R212
MISC
MISC
5 OF 12
5 OF 12
X_51R
X_51R
X_51R
X_51R
X_51R
X_51R
51R
51R
4
VID[0]/MSID[0]
VID[1]/MSID[1]
VID[2]/MSID[2]
VID[3]/MSID[3]
VID[4]/MSID[4]
VID[5]/MSID[5]
VID[6]
VID[7]
GFX_VR_EN
GFX_IMON/RSVD
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
FC_AE38
VTT_SELECT
FC_AG40
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
VAXG_SENSE
VSSAXG_SENSE
ISENSE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TRST*
PRDY*
PREQ*
DBR*
BCLK_ITP*
BCLK_ITP
TAPPWRGOOD
RESET_OBS*
BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
BPM[4]*
BPM[5]*
BPM[6]*
BPM[7]*
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
51R
51R
4
H_VID0
U40
H_VID1
U39
H_VID2
U38
H_VID3
U37
H_VID4
U36
H_VID5
U35
H_VID6
U34
H_VID7
U33
CPU_PSI
AG38
PSI*
TDO
TDI
TCK
TMS
CPU_TDO
CPU_TDI
CPU_TMS
CPU_TCK
CPU_TRST#
demo board empty
check list not empty
F12
F6
G10
B12
E12
E11
C12
G11
J11
AE38
AF39
AG40
T35
T34
AE35
AE36
A13
B13
T40
AL18
AK18
T39
M12
L12
AL15
AL14
AM38
AM37
AN37
AN40
AM39
AJ38
AK37
AL40
AK40
AK39
AK34
AL39
AL33
AL32
AK33
AK32
AM31
AL30
AK30
AK31
AL17
AM17
AM25
AL29
AM30
AK29
AK28
AM29
AM28
AL27
AK27
AM26
AM27
AL26
AK26
AK25
GFX_VR_EN
GFX_IMON
H_GFX_VID0
H_GFX_VID1
H_GFX_VID2
H_GFX_VID3
H_GFX_VID4
H_GFX_VID5
H_GFX_VID6
TP_MCP_VCCVTT_VID0
TP_MCP_VCCVTT_VID2
CPU_VCC_SENSE
CPU_VSS_SENSE
GFX_VCC_SENSE_R
GFX_VSS_SENSE_R
VCCP_IMAX
CPU_TDO
CPU_TDI
CPU_TCK
CPU_TMS
CPU_TRST#
XDP_CPU_PRDY#
XDP_CPU_PREQ#
FP_RST#
XDP_CPU_BCLK_N
XDP_CPU_BCLK_P
XDP_CPU_PWRGD
CPU_RESET_OUT#
XDP_CPU_BPM_N0
XDP_CPU_BPM_N1
XDP_CPU_BPM_N2
XDP_CPU_BPM_N3
XDP_CPU_BPM_N4
XDP_CPU_BPM_N5
XDP_CPU_BPM_N6
XDP_CPU_BPM_N7
R196
R196
R201 51RR201 51R
R207 51RR207 51R
R217
R217
R209
R209
H_VID0
35
H_VID1
35
Follow MS7588-1.0
R210
R210
X_1KR1%0402
X_1KR1%0402
R380 0RR380 0R
R3940RR394
0R
R3830RR383
0R
X_0R0402
X_0R0402
R35
R1900RR190
0R
R35
demo board no connect
if not use XDP,add Test point
CPU_VTT
B
Q30
Q30
C E
3904_SOT23
3904_SOT23
CPU_VTT
R1
R1
X_1KR1%0402
X_1KR1%0402
Follow MS7588-1.0
B
CE
Q7
Q7
X_N-SST3904_SOT23
X_N-SST3904_SOT23
CPU_VTT
51R
51R
51R
51R
51R
51R
H_PROCHOT#
CPU_PSI
3
H_VID[7..2]
35
CPU_VTT
GFX_VR_EN
34
H_GFX_VID[6..0]
TP2TP2
VTT_SELECT 33
TP3TP3
CPU_VCC_SENSE
CPU_VSS_SENSE
GFX_VCC_SENSE
GFX_VSS_SENSE
VCCP_IMAX
Follow MS7588-1.0
36
CPU_TDO
36
CPU_TDI
36
CPU_TCK
CPU_TMS
36
CPU_TRST#
XDP_CPU_PRDY#
XDP_CPU_PREQ#
FP_RST#
15,29,36
XDP_CPU_BCLK_N 36
XDP_CPU_BCLK_P 36
XDP_CPU_PWRGD
CPU_RESET_OUT#
XDP_CPU_BPM_N0 36
XDP_CPU_BPM_N1
XDP_CPU_BPM_N2
XDP_CPU_BPM_N3
XDP_CPU_BPM_N4
XDP_CPU_BPM_N5
XDP_CPU_BPM_N6
XDP_CPU_BPM_N7
PSI# 35
3
34
35
35
34
34
35
36
36
36
36
36
36
36
36
36
36
36
36
SIO_TRIP# 14,18
EXP_A_RXP_019
EXP_A_RXN_019
EXP_A_RXP_119
EXP_A_RXN_119
EXP_A_RXP_219
EXP_A_RXN_219
EXP_A_RXP_319
EXP_A_RXN_319
EXP_A_RXP_419
EXP_A_RXN_419
EXP_A_RXP_519
EXP_A_RXN_519
EXP_A_RXP_619
EXP_A_RXN_619
EXP_A_RXP_719
EXP_A_RXN_719
EXP_A_RXP_819
EXP_A_RXN_819
EXP_A_RXP_919
EXP_A_RXN_919
EXP_A_RXP_1019
EXP_A_RXN_1019
EXP_A_RXP_1119
EXP_A_RXN_1119
EXP_A_RXP_1219
EXP_A_RXN_1219
EXP_A_RXP_1319
EXP_A_RXN_1319
EXP_A_RXP_1419
EXP_A_RXN_1419
EXP_A_RXP_1519
EXP_A_RXN_1519
DMI_RX013
DMI_RX0#13
DMI_RX113
DMI_RX1#13
DMI_RX213
DMI_RX2#13
DMI_RX313
DMI_RX3#13
FDI_FSYNC014
FDI_LSYNC014
FDI_FSYNC114
FDI_LSYNC114
FDI_INT14
CPU reset
DMI_RX0
DMI_RX0#
DMI_RX1
DMI_RX1#
DMI_RX2
DMI_RX2#
DMI_RX3
DMI_RX3#
FDI_FSYNC0
FDI_LSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_INT
2
CPU1C
CPU1C
AM14
AM13
AK15
AK16
C9
D9
B8
C8
A7
A6
B6
C6
A5
B5
B4
C4
C3
D3
D2
E2
E1
F1
G3
G2
G1
H1
J3
J2
J1
K1
L2
L3
P3
P4
T3
T4
R1
T1
U3
U2
U1
V1
W3
W2
AC4
AD4
AC3
AD3
AC2
PEG_RX[0]
PEG_RX[0]*
PEG_RX[1]
PEG_RX[1]*
PEG_RX[2]
PEG_RX[2]*
PEG_RX[3]
PEG_RX[3]*
PEG_RX[4]
PEG_RX[4]*
PEG_RX[5]
PEG_RX[5]*
PEG_RX[6]
PEG_RX[6]*
PEG_RX[7]
PEG_RX[7]*
PEG_RX[8]
PEG_RX[8]*
PEG_RX[9]
PEG_RX[9]*
PEG_RX[10]
PEG_RX[10]*
PEG_RX[11]
PEG_RX[11]*
PEG_RX[12]
PEG_RX[12]*
PEG_RX[13]
PEG_RX[13]*
PEG_RX[14]
PEG_RX[14]*
PEG_RE[15]
PEG_RX[15]*
DMI_RX[0]
DMI_RX[0]*
DMI_RX[1]
DMI_RX[1]*
DMI_RX[2]
DMI_RX[2]*
DMI_RX[3]
DMI_RX[3]*
RSVD
RSVD
RSVD
RSVD
CPU1D
CPU1D
FDI_FSYNC[0]
FDI_LSYNC[0]
DISPLAY
DISPLAY
LINK
LINK
FDI_FSYNC[1]
FDI_LSYNC[1]
FDI_INT
4 OF 12
4 OF 12
PEG
PEG
PEG_TX[10]*
PEG_TX[11]*
PEG_TX[12]*
PEG_TX[13]*
PEG_TX[14]*
PEG_TX[15]*
DMI
DMI
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
3 OF 12
3 OF 12
VDDIO
VDDIO
FDI_TX[0]
FDI_TX[0]*
FDI_TX[1]
FDI_TX[1]*
FDI_TX[2]
FDI_TX[2]*
FDI_TX[3]
FDI_TX[3]*
FDI_TX[4]
FDI_TX[4]*
FDI_TX[5]
FDI_TX[5]*
FDI_TX[6]
FDI_TX[6]*
FDI_TX[7]
FDI_TX[7]*
PEG_TX[0]
PEG_TX[0]*
PEG_TX[1]
PEG_TX[1]*
PEG_TX[2]
PEG_TX[2]*
PEG_TX[3]
PEG_TX[3]*
PEG_TX[4]
PEG_TX[4]*
PEG_TX[5]
PEG_TX[5]*
PEG_TX[6]
PEG_TX[6]*
PEG_TX[7]
PEG_TX[7]*
PEG_TX[8]
PEG_TX[8]*
PEG_TX[9]
PEG_TX[9]*
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
DMI_TX[0]
DMI_TX[0]*
DMI_TX[1]
DMI_TX[1]*
DMI_TX[2]
DMI_TX[2]*
DMI_TX[3]
DMI_TX[3]*
PEG_RBIAS
C7
D7
E7
E6
E5
F5
F3
F4
G6
G5
H4
H3
F7
G7
J6
J5
K3
K4
H8
J8
L6
L5
M4
M3
K7
L7
N6
N5
M8
N8
R5
R6
DMI_TX0
L1
DMI_TX0#
M1
DMI_TX1
N3
DMI_TX1#
N2
DMI_TX2
N1
DMI_TX2#
P1
DMI_TX3
R2
DMI_TX3#
R3
D11
C10
B10
A11
U6
U5
V4
V3
U8
U7
W8
W7
W5
W4
R8
R7
Y4
Y3
Y6
Y5
GRCOMP
GRBIAS
Break-out:10mil width, 6 mil space
Other Area:10mil width, 15 mil space
FDI_TX0
FDI_TX0#
FDI_TX1
FDI_TX1#
FDI_TX2
FDI_TX2#
FDI_TX3
FDI_TX3#
FDI_TX4
FDI_TX4#
FDI_TX5
FDI_TX5#
FDI_TX6
FDI_TX6#
FDI_TX7
FDI_TX7#
1
EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_TX0
DMI_TX0#
DMI_TX1 13
DMI_TX1#
DMI_TX2 13
DMI_TX2#
DMI_TX3
DMI_TX3#
R297
R297
750/1%
750/1%
FDI_TX0
FDI_TX0#
FDI_TX1
FDI_TX1#
FDI_TX2
FDI_TX2#
FDI_TX3
FDI_TX3#
FDI_TX4
FDI_TX4#
FDI_TX5
FDI_TX5#
FDI_TX6
FDI_TX6#
FDI_TX7
FDI_TX7#
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
13
13
13
13
13
13
R304
R304
49.9/1%
49.9/1%
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
reserve
3VSB
R182
R182
10K/1%
10K/1%
R188 10K/1%R188 10K/1%
PLTRST#15,18,36
2
5
2
Q26
Q26
3904_SOT363
3904_SOT363
CPU_VTTCPU_VTT
C80
C80
1
CPURST#PLTRST#
R193
R193
X_665R/1%
X_665R/1%
63
63
63
Sheet of
Sheet of
Sheet of
1.3
1.3
1.3
8
8
8
R192
R197
R197
150R
150R
6
1
3
4
CPURST#
MSI
MSI
MSI
Size
Size
Size
Custom
Custom
Custom
Date:
Date:
Date:
R192
X_1.3K/1%
X_1.3K/1%
X_100p/16X
X_100p/16X
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
MS-7636
Document Description Rev
Document Description Rev
Document Description Rev
CPU-CNTL/CLK/MISC
CPU-CNTL/CLK/MISC
CPU-CNTL/CLK/MISC
Friday, March 19, 2010
Friday, March 19, 2010
Friday, March 19, 2010
5
www.vinafix.vn
CPU1A
MEM_MA_ADD[15..0]10
D D
MEM_MA_WE_L10
MEM_MA_CAS_L10
MEM_MA_RAS_L10
MEM_MA_BANK010
MEM_MA_BANK110
MEM_MA_BANK210
MEM_MA_CS_L010
MEM_MA_CS_L110
MEM_MA_CS_L210
MEM_MA_CS_L310
MEM_MA_CKE010
MEM_MA_CKE110
MEM_MA_CKE210
MEM_MA_CKE310
MEM_MA_ODT010
MEM_MA_ODT110
MEM_MA_ODT210
MEM_MA_ODT310
C C
MEM_MA_CLK_H010
MEM_MA_CLK_L010
MEM_MA_CLK_H110
MEM_MA_CLK_L110
MEM_MA_CLK_H210
MEM_MA_CLK_L210
MEM_MA_CLK_H310
MEM_MA_CLK_L310
B B
A A
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_RAS_L
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_CS_L0
MEM_MA_CS_L1
MEM_MA_CS_L2
MEM_MA_CS_L3
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA_CKE2
MEM_MA_CKE3
MEM_MA_ODT0
MEM_MA_ODT1
MEM_MA_ODT2
MEM_MA_ODT3
MEM_MA_CLK_H0
MEM_MA_CLK_L0
MEM_MA_CLK_H1
MEM_MA_CLK_L1
MEM_MA_CLK_H2
MEM_MA_CLK_L2
MEM_MA_CLK_H3
MEM_MA_CLK_L3
DDR3_DRAMRST#
5
AW18
AY15
AV15
AU15
AW14
AY13
AV14
AW13
AU14
AW12
AT19
AU13
AW11
AU24
AT11
AR10
AT22
AU22
AT20
AV20
AU19
AU12
AV21
AW24
AU21
AU23
AU10
AW10
AV10
AY10
AV23
AV24
AW23
AY24
AR22
AR21
AP18
AN18
AN21
AP21
AP19
AN19
AV8
AK22
AM22
AL23
AK23
AL10
AM10
AP10
AN10
AR11
AP11
AK9
AL9
AK11
AM11
CPU1A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_WE*
SA_CAS*
SA_RAS*
SA_BA[0]
SA_BA[1]
SA_BA[2]
SA_CS[0]*
SA_CS[1]*
SA_CS[2]*
SA_CS[3]*
SA_CKE[0]
SA_CKE[1]
SA_CKE[2]
SA_CKE[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_CK[0]
SA_CK[0]*
SA_CK[1]
SA_CK[1]*
SA_CK[2]
SA_CK[2]*
SA_CK[3]
SA_CK[3]*
SM_DRAMRST*
SA_CS[4]*
SA_CS[5]*
SA_CS[6]*
SA_CS[7]*
SA_DQS[8]
SA_DQS[8]*
SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]
DDR_A
DDR_A
1 OF 12
1 OF 12
SA_DQS[0]
SA_DQS[0]*
SA_DQS[1]
SA_DQS[1]*
SA_DQS[2]
SA_DQS[2]*
SA_DQS[3]
SA_DQS[3]*
SA_DQS[4]
SA_DQS[4]*
SA_DQS[5]
SA_DQS[5]*
SA_DQS[6]
SA_DQS[6]*
SA_DQS[7]
SA_DQS[7]*
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
4
MEM_MA_DQS_H0
AK3
MEM_MA_DQS_L0
AJ3
MEM_MA_DQS_H1
AP2
MEM_MA_DQS_L1
AP3
MEM_MA_DQS_H2
AU4
MEM_MA_DQS_L2
AU3
MEM_MA_DQS_H3
AY6
MEM_MA_DQS_L3
AW6
MEM_MA_DQS_H4
AR28
MEM_MA_DQS_L4
AT29
MEM_MA_DQS_H5
AV32
MEM_MA_DQS_L5
AW32
MEM_MA_DQS_H6
AW36
MEM_MA_DQS_L6
AV35
MEM_MA_DQS_H7
AR39
MEM_MA_DQS_L7
AR38
MEM_MA_DM0
AJ2
MEM_MA_DM1
AN1
MEM_MA_DM2
AU1
MEM_MA_DM3
AV6
MEM_MA_DM4
AN29
MEM_MA_DM5
AW31
MEM_MA_DM6
AU35
MEM_MA_DM7
AT38
MEM_MA_DATA0
AH1
MEM_MA_DATA1
AJ4
MEM_MA_DATA2
AL2
MEM_MA_DATA3
AL1
MEM_MA_DATA4
AG2
MEM_MA_DATA5
AH2
MEM_MA_DATA6
AK1
MEM_MA_DATA7
AK2
MEM_MA_DATA8
AN3
MEM_MA_DATA9
AN2
MEM_MA_DATA10
AR3
MEM_MA_DATA11
AR2
MEM_MA_DATA12
AM3
MEM_MA_DATA13
AM2
MEM_MA_DATA14
AP1
MEM_MA_DATA15
AR4
MEM_MA_DATA16
AT4
MEM_MA_DATA17
AU2
MEM_MA_DATA18
AW3
MEM_MA_DATA19
AW4
MEM_MA_DATA20
AT3
MEM_MA_DATA21
AT1
MEM_MA_DATA22
AV2
MEM_MA_DATA23
AV4
MEM_MA_DATA24
AW5
MEM_MA_DATA25
AY5
MEM_MA_DATA26
AU8
MEM_MA_DATA27
AY8
MEM_MA_DATA28
AU5
MEM_MA_DATA29
AV5
MEM_MA_DATA30
AV7
MEM_MA_DATA31
AW7
MEM_MA_DATA32
AN27
MEM_MA_DATA33
AT28
MEM_MA_DATA34
AP28
MEM_MA_DATA35
AP30
MEM_MA_DATA36
AN26
MEM_MA_DATA37
AR27
MEM_MA_DATA38
AR29
MEM_MA_DATA39
AN30
MEM_MA_DATA40
AU30
MEM_MA_DATA41
AU31
MEM_MA_DATA42
AV33
MEM_MA_DATA43
AU34
MEM_MA_DATA44
AV30
MEM_MA_DATA45
AW30
MEM_MA_DATA46
AU33
MEM_MA_DATA47
AW33
MEM_MA_DATA48
AW35
MEM_MA_DATA49
AY35
MEM_MA_DATA50
AV37
MEM_MA_DATA51
AU37
MEM_MA_DATA52
AY34
MEM_MA_DATA53
AW34
MEM_MA_DATA54
AV36
MEM_MA_DATA55
AW37
MEM_MA_DATA56
AT39
MEM_MA_DATA57
AT40
MEM_MA_DATA58
AN38
MEM_MA_DATA59
AN39
MEM_MA_DATA60
AU38
MEM_MA_DATA61
AU39
MEM_MA_DATA62
AP39
MEM_MA_DATA63
AP40
DDR3_DRAMRST#
4
R257
R257
C180
C180
X_0.1u/16X
X_0.1u/16X
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
VCC_DDR VCC_DDR
1K/1%
1K/1%
B
10
10
10
10
10
10
10
10
MEM_MA_DATA[63..0]
R270
R270
470R
470R
R268
R268
R258
R258
R269
R269
CE
Q48
Q48
2N3904
2N3904
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
470R
470R
470R
470R
X_0R
X_0R
10
B
B
3
MEM_MB_ADD[15..0]11
MEM_MB_CS_L011
MEM_MB_CS_L111
MEM_MB_CS_L211
MEM_MB_CS_L311
MEM_MB_CLK_H211
MEM_MB_CLK_L211
MEM_MB_CLK_H311
MEM_MB_CLK_L311
CE
VCC_DDR
CE
3
MEM_MB_WE_L11
MEM_MB_CAS_L11
MEM_MB_RAS_L11
MEM_MB_BANK011
MEM_MB_BANK111
MEM_MB_BANK211
MEM_MB_CKE011
MEM_MB_CKE111
MEM_MB_CKE211
MEM_MB_CKE311
MEM_MB_ODT011
MEM_MB_ODT111
MEM_MB_ODT211
MEM_MB_ODT311
MEM_MB_CLK_H011
MEM_MB_CLK_L011
MEM_MB_CLK_H111
MEM_MB_CLK_L111
R262
R262
150R
150R
Q45
Q45
2N3904
2N3904
R260
R260
150R
150R
Q44
Q44
2N3904
2N3904
DDR3_DRAMRST#B
R261
R261
X_0R
X_0R
DDR3_DRAMRST#A 10
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MB_RAS_L
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_CS_L0
MEM_MB_CS_L1
MEM_MB_CS_L2
MEM_MB_CS_L3
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB_CKE2
MEM_MB_CKE3
MEM_MB_ODT0
MEM_MB_ODT1
MEM_MB_ODT2
MEM_MB_ODT3
MEM_MB_CLK_H0
MEM_MB_CLK_L0
MEM_MB_CLK_H1
MEM_MB_CLK_L1
MEM_MB_CLK_H2
MEM_MB_CLK_L2
MEM_MB_CLK_H3
MEM_MB_CLK_L3
11
AU20
AU18
AV18
AU17
AY18
AV17
AW17
AU16
AT17
AY16
AY25
AW16
AW15
AW28
AY12
AV11
AU26
AW27
AW26
AU25
AW25
AV12
AY27
AW29
AV26
AV29
AW8
AU9
AU27
AU29
AV27
AU28
AR17
AR16
AT15
AR15
AN17
AN16
AR19
AR18
AM23
AM24
AL24
AK24
AR14
AR13
AR12
AT13
AN15
AP14
AM12
AN12
AN14
AP13
AY9
AV9
CPU1B
CPU1B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_WE*
SB_CAS*
SB_RAS*
SB_BA[0]
SB_BA[1]
SB_BA[2]
SB_CS[0]*
SB_CS[1]*
SB_CS[2]*
SB_CS[3]*
SB_CKE[0]
SB_CKE[1]
SB_CKE[2]
SB_CKE[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_CK[0]
SB_CK[0]*
SB_CK[1]
SB_CK[1]*
SB_CK[2]
SB_CK[2]*
SB_CK[3]
SB_CK[3]*
SB_CS[4]*
SB_CS[5]*
SB_CS[6]*
SB_CS[7]*
SB_DQS[8]
SB_DQS[8]*
SB_ECC_CB[0]
SB_ECC_CB[1]
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]
DDR_B
DDR_B
2 OF 12
2 OF 12
2
MEM_MB_DQS_H0
AF4
SB_DQS[0]
SB_DQS[0]*
SB_DQS[1]
SB_DQS[1]*
SB_DQS[2]
SB_DQS[2]*
SB_DQS[3]
SB_DQS[3]*
SB_DQS[4]
SB_DQS[4]*
SB_DQS[5]
SB_DQS[5]*
SB_DQS[6]
SB_DQS[6]*
SB_DQS[7]
SB_DQS[7]*
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
MSI
MSI
MSI
2
MEM_MB_DQS_L0
AE5
MEM_MB_DQS_H1
AH6
MEM_MB_DQS_L1
AJ5
MEM_MB_DQS_H2
AN6
MEM_MB_DQS_L2
AM6
MEM_MB_DQS_H3
AR8
MEM_MB_DQS_L3
AP8
MEM_MB_DQS_H4
AT25
MEM_MB_DQS_L4
AR24
MEM_MB_DQS_H5
AP32
MEM_MB_DQS_L5
AR32
MEM_MB_DQS_H6
AR36
MEM_MB_DQS_L6
AR37
MEM_MB_DQS_H7
AL37
MEM_MB_DQS_L7
AM36
MEM_MB_DM0
AE4
MEM_MB_DM1
AH4
MEM_MB_DM2
AM7
MEM_MB_DM3
AT7
MEM_MB_DM4
AN24
MEM_MB_DM5
AN32
MEM_MB_DM6
AM33
MEM_MB_DM7
AK35
MEM_MB_DATA0
AD7
MEM_MB_DATA1
AD6
MEM_MB_DATA2
AH8
MEM_MB_DATA3
AJ8
MEM_MB_DATA4
AC7
MEM_MB_DATA5
AC6
MEM_MB_DATA6
AF5
MEM_MB_DATA7
AE6
MEM_MB_DATA8
AG5
MEM_MB_DATA9
AH7
MEM_MB_DATA10
AK6
MEM_MB_DATA11
AL4
MEM_MB_DATA12
AG6
MEM_MB_DATA13
AG4
MEM_MB_DATA14
AJ7
MEM_MB_DATA15
AK7
MEM_MB_DATA16
AL6
MEM_MB_DATA17
AN5
MEM_MB_DATA18
AP6
MEM_MB_DATA19
AR5
MEM_MB_DATA20
AL5
MEM_MB_DATA21
AM4
MEM_MB_DATA22
AN7
MEM_MB_DATA23
AP5
MEM_MB_DATA24
AT6
MEM_MB_DATA25
AR7
MEM_MB_DATA26
AR9
MEM_MB_DATA27
AM8
MEM_MB_DATA28
AN8
MEM_MB_DATA29
AR6
MEM_MB_DATA30
AL8
MEM_MB_DATA31
AT9
MEM_MB_DATA32
AN23
MEM_MB_DATA33
AP23
MEM_MB_DATA34
AR25
MEM_MB_DATA35
AR26
MEM_MB_DATA36
AT23
MEM_MB_DATA37
AP22
MEM_MB_DATA38
AP25
MEM_MB_DATA39
AT26
MEM_MB_DATA40
AT32
MEM_MB_DATA41
AP31
MEM_MB_DATA42
AR33
MEM_MB_DATA43
AM32
MEM_MB_DATA44
AT31
MEM_MB_DATA45
AR31
MEM_MB_DATA46
AR34
MEM_MB_DATA47
AT33
MEM_MB_DATA48
AR35
MEM_MB_DATA49
AT36
MEM_MB_DATA50
AN33
MEM_MB_DATA51
AP36
MEM_MB_DATA52
AP34
MEM_MB_DATA53
AT35
MEM_MB_DATA54
AN34
MEM_MB_DATA55
AP37
MEM_MB_DATA56
AL35
MEM_MB_DATA57
AM35
MEM_MB_DATA58
AJ36
MEM_MB_DATA59
AJ37
MEM_MB_DATA60
AN35
MEM_MB_DATA61
AM34
MEM_MB_DATA62
AJ35
MEM_MB_DATA63
AL36
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
CPU-Memory
CPU-Memory
CPU-Memory
Friday, March 19, 2010
Friday, March 19, 2010
Friday, March 19, 2010
MS-7636
MS-7636
MS-7636
1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DATA[63..0]
Sheet ofDate:
Sheet ofDate:
Sheet ofDate:
1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
1.3
1.3
73
73
73
1.3
8
8
8
11
5
www.vinafix.vn
CPU1F
CPU1F
CPU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CPU
POWER
POWER
6 OF 12
6 OF 12
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H26
H28
H29
H31
H32
H34
H35
H37
H38
H40
J18
J19
J21
J22
J24
J25
J27
J28
J30
J31
J33
J34
J36
J37
J39
J40
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
L17
L19
L20
L22
L23
L25
L26
L28
L29
L31
L32
L34
L35
L37
L38
L40
M17
M19
M21
M22
M24
M25
M27
M28
M30
M33
M34
M36
M37
M39
M40
N33
N35
N36
N38
N39
P33
P34
P35
P36
P37
P38
P39
P40
R33
R34
R35
R36
R37
R38
R39
R40
VCC1_8
A23
A24
A26
A27
A33
A35
A36
A38
D D
C C
B B
B23
B25
B26
B28
B29
B31
B32
B34
B35
B37
B38
C23
C24
C25
C27
C28
C30
C31
C33
C34
C36
C37
C39
C40
D23
D24
D26
D27
D29
D30
D32
D33
D35
D36
D38
D39
E22
E23
E25
E26
E28
E29
E31
E32
E34
E35
E37
E38
E40
F21
F22
F24
F25
F27
F28
F30
F31
F33
F34
F36
F37
F39
F40
G20
G21
G23
G24
G26
G27
G29
G30
G32
G33
G35
G36
G38
G39
H19
H20
H22
H23
H25
AA33
AA34
AA35
AA36
AA37
AA38
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AE33
AE34
AE39
AE40
AF33
AG33
AJ31
AJ32
AJ21
AJ25
AJ27
AJ29
AK20
AK21
AL20
AL21
AC8
AE8
AJ17
AJ19
AK19
AC5
AJ23
AG8
AF8
AF7
CPU1G
CPU1G
V33
V34
V35
V36
V37
V38
V39
V40
Y33
Y34
Y35
Y36
Y37
Y38
VTT_01
VTT_02
VTT_03
VTT_04
VTT_05
VTT_06
VTT_07
VTT_08
VTT_09
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_60
VCCPLL_01
VCCPLL_02
VCCPLL_03
7 OF 12
7 OF 12
CPU
CPU
POWER
POWER
4
CPU1H
CPU1H
A14
VAXG_01
A15
VAXG_02
A17
VAXG_03
A18
VAXG_04
B14
VAXG_05
B15
VAXG_06
B17
VAXG_07
B18
VAXG_08
C14
VAXG_09
C15
VAXG_10
C17
VAXG_11
C18
VAXG_12
C20
VAXG_13
C21
VAXG_14
D14
VAXG_15
D15
VAXG_16
D17
VAXG_17
D18
VAXG_18
D20
VAXG_19
D21
VAXG_20
E14
VAXG_21
E15
VAXG_22
E17
VAXG_23
E18
VAXG_24
E20
VAXG_25
F14
VAXG_26
F15
VAXG_27
F17
VAXG_28
F18
VAXG_29
F19
VAXG_30
G14
VAXG_31
G15
VAXG_32
G17
VAXG_33
G18
VAXG_34
H14
VAXG_35
H15
VAXG_36
H17
VAXG_37
J14
VAXG_38
J15
VAXG_39
J16
VAXG_40
K14
VAXG_41
K15
VAXG_42
K16
VAXG_43
L14
VAXG_44
L15
VAXG_45
L16
VAXG_46
M14
VAXG_47
M15
VAXG_48
M16
VAXG_49
CPU
CPU
POWER
POWER
8 OF 12
8 OF 12
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
T6
T7
T8
V7
V8
AB7
3
VCC_DDR
2
GPU_CORE Decoupling
CPU_VTTVCCPVCCP CPU_VTTCPU_VTT GPU_CORE
CPU1I
CPU1I
L10
VTT_67
M10
VTT_68
M11
VTT_69
M9
VTT_70
N7
VTT_71
P6
VTT_72
P7
VTT_73
P8
VTT_74
T2
VTT_75
V2
VTT_76
V6
VTT_77
W1
VTT_78
W6
VTT_79
GPU_CORE
C175 22u/6.3X/8C175 22u/6.3X/8
C160 22u/6.3X/8C160 22u/6.3X/8
C166
C166
X_4.7u/10X/12
X_4.7u/10X/12
C559
C559
X_22u/6.3X/8
X_22u/6.3X/8
背面
C560 X_22u/6.3X/8C560 X_22u/6.3X/8
C557
C557
X_22u/6.3X/8
X_22u/6.3X/8
C556
C556
X_22u/6.3X/8
X_22u/6.3X/8
CPU SOCKET CAVITY CAPS
AJ11
VDDQ_01
AJ13
VDDQ_02
AJ15
VDDQ_03
AT18
VDDQ_04
AT21
VDDQ_05
AT10
VDDQ_06
AU11
VDDQ_07
AV13
VDDQ_08
AV16
VDDQ_09
AV19
VDDQ_10
AV22
AV25
AV28
AW9
AY11
AY14
AY17
AY23
AY26
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
CPU
CPU
POWER
POWER
9 OF 12
9 OF 12
CPU_VTT Decoupling
CPU_VTT CPU_VTT
C171
C123
C123
22u/6.3X/8
22u/6.3X/8
C172
C172
22u/6.3X/8
22u/6.3X/8
C171
22u/6.3X/8
22u/6.3X/8
C136 22u/6.3X/8C136 22u/6.3X/8
C117
C117
22u/6.3X/8
22u/6.3X/8
C149 22u/6.3X/8C149 22u/6.3X/8
C174 22u/6.3X/8C174 22u/6.3X/8C555 X_22u/6.3X/8C555 X_22u/6.3X/8
C147 22u/6.3X/8C147 22u/6.3X/8 C552 X_22u/6.3X/8C552 X_22u/6.3X/8
C141
C141
22u/6.3X/8
22u/6.3X/8
C128
C128
C154
C154
22u/6.3X/8
22u/6.3X/8
22u/6.3X/8
22u/6.3X/8
1
VCC_DDR-Decoupling
VCC_DDR
C158
C158
C164
22u/6.3X/8
22u/6.3X/8
C164
22u/6.3X/8
22u/6.3X/8
C558
C558
X_22u/6.3X/8
X_22u/6.3X/8
CPU SOCKET CAVITY CAPS
背面
C549
C549
C553
C553
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
C554
C554
X_22u/6.3X/8
X_22u/6.3X/8
C561
C561
X_22u/6.3X/8
X_22u/6.3X/8
CPU SOCKET CAVITY CAPS
CPU_VCCP-Decuig
VCCP
C152
C152
C151
22u/6.3X/8
22u/6.3X/8
C542 X_22u/6.3X/8C542 X_22u/6.3X/8
C551
C551
X_22u/6.3X/8
X_22u/6.3X/8
C151
22u/6.3X/8
22u/6.3X/8
C144 22u/6.3X/8C144 22u/6.3X/8
C540
C540
X_22u/6.3X/8
X_22u/6.3X/8
C131
C131
22u/6.3X/8
22u/6.3X/8
C546
C546
X_22u/6.3X/8
X_22u/6.3X/8
C153
C153
22u/6.3X/8
22u/6.3X/8
C132
C132
22u/6.3X/8
22u/6.3X/8
C118
C118
22u/6.3X/8
22u/6.3X/8
0603
C543
C543
X_1u/10Y/6
X_1u/10Y/6
C120
C120
22u/6.3X/8
22u/6.3X/8
C545
C545
X_1u/10Y/6
X_1u/10Y/6
C134
C134
22u/6.3X/8
22u/6.3X/8
C550
C550
X_1u/10Y/6
X_1u/10Y/6
C548
C548
X_1u/10Y/6
X_1u/10Y/6
VCC1_8
C173
C173
22u/6.3X/8
22u/6.3X/8
C142
C142
22u/6.3X/8
22u/6.3X/8
C536
C536
C537
C537
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
C143 22u/6.3X/8C143 22u/6.3X/8
背面
C547 X_22u/6.3X/8C547 X_22u/6.3X/8
C119
C119
C133
C133
22u/6.3X/8
22u/6.3X/8
22u/6.3X/8
22u/6.3X/8
C535
C535
C541
C541
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
X_22u/6.3X/8
A A
CPU SOCKET CAVITY CAPS
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
MSI
MSI
MSI
Size
Size
Size
Custom
Custom
Custom
Date:
Friday, March 19, 2010
Date:
Friday, March 19, 2010
Date:
5
4
3
2
Friday, March 19, 2010
MS-7636
Document Description Rev
Document Description Rev
Document Description Rev
CPU-Power
CPU-Power
CPU-Power
1
83
83
83
Sheet of
Sheet of
Sheet of
1.3
1.3
1.3
8
8
8
5
www.vinafix.vn
4
3
2
1
CPU1J
CPU1J
A16
VSS
A25
VSS
A28
VSS
A34
VSS
A37
VSS
D D
C C
B B
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AE37
AF40
AG34
AG36
AH33
AH38
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28
AJ30
AJ33
AJ34
AJ40
AK10
AK17
AK36
AL11
AL13
AL16
AL19
AL22
AL25
AL28
AL31
AL34
AL38
AM40
AN13
AN20
AN22
AN25
AN28
AN31
AN36
AP12
AP15
AP16
AP17
AP20
AP24
AP26
AP27
AP29
AP35
AC1
AD5
AD8
AE3
AE7
AF1
AF6
AH5
AG7
AH3
AK5
AK8
AM1
AK4
AM5
AM9
AN4
AN9
AA5
VSS
AB3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB6
VSS
AB8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ6
VSS
AJ9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL3
VSS
VSS
VSS
VSS
AL7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP33
AP38
AP4
AP7
AP9
AR1
AR20
AR23
AR40
AT12
AT14
AT16
AT2
AT24
AT27
AT30
AR30
AT34
AT37
AT5
AU32
AT8
AV3
AV31
AV34
AU36
AU6
AY33
AY36
AY4
AY7
B16
B24
B27
B30
B33
B36
B7
B9
C13
C16
C19
C22
C26
C29
C32
C35
C38
C5
D10
D12
D13
D16
D19
D22
D25
D28
D31
D34
D37
D4
D40
D5
D6
D8
E13
E16
E19
E21
E24
E27
E3
E30
E33
E36
E39
E4
F11
F13
F16
F2
F20
F23
F26
F29
F32
F35
F38
F8
G13
W33
W34
CPU1K
CPU1K
G16
VSS
G19
VSS
G22
VSS
G25
VSS
G28
VSS
G31
VSS
G34
VSS
G37
VSS
G4
VSS
G40
VSS
G9
VSS
H11
VSS
H13
VSS
H16
VSS
H18
VSS
H2
VSS
H21
VSS
H24
VSS
H27
VSS
H30
VSS
H33
VSS
H36
VSS
H39
VSS
H5
VSS
H6
VSS
J13
VSS
J17
VSS
J20
VSS
J23
VSS
J26
VSS
J29
VSS
J32
VSS
J35
VSS
J38
VSS
J4
VSS
J7
VSS
J9
VSS
K11
VSS
K13
VSS
K19
VSS
K2
VSS
K22
VSS
K25
VSS
K28
VSS
K31
VSS
K34
VSS
K37
VSS
K40
VSS
K5
VSS
K6
VSS
L13
VSS
L18
VSS
L21
VSS
L24
VSS
L27
VSS
L30
VSS
L33
VSS
L36
VSS
L39
VSS
L4
VSS
L9
VSS
M13
VSS
M18
VSS
M2
VSS
M20
VSS
M23
VSS
M26
VSS
M29
VSS
M32
VSS
M35
VSS
M38
VSS
M5
VSS
M6
VSS
M7
VSS
N34
VSS
N37
VSS
N4
VSS
N40
VSS
P2
VSS
P5
VSS
R4
VSS
T33
VSS
T36
VSS
T37
VSS
T38
VSS
T5
VSS
U4
VSS
V5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
W35
W36
W37
W38
Y7
B39
VREF_DQ_B
TP_CGC DIMM_VREFA
TP29TP29
NOTE:R310,R316 STUFFED,IF DDR3 DIMM
VREFDQ OPTION 2 UNSTUFFED.
FOLLOW DDR3 DIMM VREFDQ Platform
Design Guide Change Option 3
FOLLOW WW11, 18 2009.
Havendale and Clarkdale must stuff.
Channel A and B Output DDR3 DIMM DQ Reference
Voltage. NOTE: This signal is reserved for possible future
use, and may not be driven on initial steppings. Refer to
the Platform Design Guide for DIMM DQ VREF
implementation details.
stuff or unstuff ?????
VREF_DQ_A
close to DIMM
R320
R320
R323 X_0RR323 X_0R
X_0R
X_0R
DIMM_VREFB
AG3
AH40
AJ39
AN11
A12
AD2
AE2
AF3
AU7
AY3
CPU1L
CPU1L
VDDIO
VDDIO
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
RSVD
RSVD
RSVD
RSVD
NC/SPARE
NC/SPARE
12 OF 12
12 OF 12
GND
10 OF 12
10 OF 12
A A
5
4
11 OF 12
11 OF 12
GND
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
MSI
MSI
MSI
Size
Size
Size
Custom
Custom
Custom
Date:
Friday, March 19, 2010
Date:
Friday, March 19, 2010
Date:
3
2
Friday, March 19, 2010
MS-7636
Document Description Rev
Document Description Rev
Document Description Rev
CPU-GND
CPU-GND
CPU-GND
1
93
93
93
Sheet of
Sheet of
Sheet of
1.3
1.3
1.3
8
8
8
5
www.vinafix.vn
4
3
2
1
DDRIII DIMM_A1 DDRIII DIMM_A2
VCC_DDR
DIMM1
DIMM1
3
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
18
DQ10
19
DQ11
131
DQ12
132
DQ13
137
DQ14
138
DQ15
21
DQ16
22
DQ17
27
DQ18
28
DQ19
140
DQ20
141
DQ21
146
DQ22
147
DQ23
30
DQ24
31
DQ25
36
DQ26
37
DQ27
149
DQ28
150
DQ29
155
DQ30
156
DQ31
81
DQ32
82
DQ33
87
DQ34
88
DQ35
200
DQ36
201
DQ37
206
DQ38
207
DQ39
90
DQ40
91
DQ41
96
DQ42
97
DQ43
209
DQ44
210
DQ45
215
DQ46
216
DQ47
99
DQ48
100
DQ49
105
DQ50
106
DQ51
218
DQ52
219
DQ53
224
DQ54
225
DQ55
108
DQ56
109
DQ57
114
DQ58
115
DQ59
227
DQ60
228
DQ61
233
DQ62
234
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
5VDIMM
U11
U11
1
VCC
2
BUS_SEL
5
SCL
4
SDA
3
GND
X_UP6262AMA8_SOT23-8-RH
X_UP6262AMA8_SOT23-8-RH
54
VDD51VDD
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
VSS
VSS
VSS
VSS
VSS
VSS
107
110
113
116
119
121
OUT1
OUT2
OUT3
124
VSS
127
8
7
6
VSS
VSS
130
VSS
VSS
VSS
133
136
139
VREF_CA_A
VREF_CA_B
170
173
176
179
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
142
145
148
151
C2.2u6.3Y
C2.2u6.3Y
C220p10X
C220p10X
C2.2u6.3Y
C2.2u6.3Y
C2.2u6.3Y
C2.2u6.3Y
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
R237
R237
R231
R231
1KR1%0402
1KR1%0402
R414 1KR1%0402R414 1KR1%0402
R415
R415
1KR1%0402
1KR1%0402
MEM_MA_DATA[63..0]
VCC_DDR
1KR1%0402
1KR1%0402
VCC_DDR
SMBCLK11,12,15,19,21,30,35,36
SMBDATA11,12,15,19,21,30,35,36
5
C102
C102
X_C2.2u6.3Y
X_C2.2u6.3Y
X_18KR1%0402
X_18KR1%0402
R253
R253
SMBCLK
SMBDATA
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
5VDIMM
R246
R246
X_13KR1%0402
X_13KR1%0402
MEM_MA_DATA[63..0]7
D D
VCC3
C75 C0.1u16Y0402C75 C0.1u16Y0402
C C
Place close to DIMM1
VCC_DDR
C92
C92
C169
C169
C30
C30
C177
C177
Place close to DIMM1 with DIMM2
VCC_DDR
C183
C183
Place close to DIMM2
VCC_DDR
C138
C138
C112
C112
B B
UPI VOLTAGE CONSOLE
VREF_CA_A
VREF_CA_A
C124
C124
C0.1u16Y0402
C0.1u16Y0402
UPI VOLTAGE CONSOLE
VREF_DQ_A
VREF_DQ_A
C239
C239
C0.1u16Y0402
C0.1u16Y0402
A A
UPI VOLTAGE CONSOLE(2)
2.083325V
0x66:RH=18K,RL=13K
182
154
183
VDD
VSS
157
4
186
189
VDD
VDD
VSS
VSS
160
163
VREF_CA_A
VREF_CA_B
VCC3
VTT_DDR
191
194
197
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
166
199
202
205
236
VDDSPD
VSS
VSS
208
211
167
79
53
48
187
198
68
120
240
MEM_MA_ADD0
VTT
VTT
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
SMBCLK_DDR11
SMBDATA_DDR11
188
A0
MEM_MA_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MA_ADD2
61
A2
MEM_MA_ADD3
180
A3
MEM_MA_ADD4
59
A4
MEM_MA_ADD5
58
A5
MEM_MA_ADD6
178
A6
MEM_MA_ADD7
56
A7
MEM_MA_ADD8
177
A8
MEM_MA_ADD9
175
A9
MEM_MA_ADD10
70
A10/AP
MEM_MA_ADD11
55
A11
MEM_MA_ADD12
174
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
172
A14
MEM_MA_ADD15 MEM_MA_ADD15
171
A15
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
MEM_MA_DQS_H0
7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
RESET#
CK1(NU)
CK1#(NU)
VREFDQ
VREFCA
VSS
VSS
MEC1
235
239
MEC1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
MEC2
MEM_MA_DQS_L0
6
MEM_MA_DQS_H1
16
MEM_MA_DQS_L1
15
MEM_MA_DQS_H2
25
MEM_MA_DQS_L2
24
MEM_MA_DQS_H3
34
MEM_MA_DQS_L3
33
MEM_MA_DQS_H4
85
MEM_MA_DQS_L4
84
MEM_MA_DQS_H5
94
MEM_MA_DQS_L5
93
MEM_MA_DQS_H6
103
MEM_MA_DQS_L6
102
MEM_MA_DQS_H7
112
MEM_MA_DQS_L7
111
43
42
MEM_MA_DM0
125
126
MEM_MA_DM1
134
135
MEM_MA_DM2
143
144
MEM_MA_DM3
152
153
MEM_MA_DM4
203
204
MEM_MA_DM5
212
213
MEM_MA_DM6
221
222
MEM_MA_DM7
230
231
161
162
MEM_MA_ODT0
195
ODT0
MEM_MA_ODT1
77
ODT1
MEM_MA_CKE0
50
CKE0
MEM_MA_CKE1
169
CKE1
MEM_MA_CS_L0
193
CS0#
MEM_MA_CS_L1
76
CS1#
MEM_MA_BANK0
71
BA0
MEM_MA_BANK1
190
BA1
MEM_MA_BANK2
52
BA2
MEM_MA_WE_L
73
WE#
MEM_MA_RAS_L
192
RAS#
MEM_MA_CAS_L
74
CAS#
168
MEM_MA_CLK_H0
184
CK0
MEM_MA_CLK_L0
185
CK0#
MEM_MA_CLK_H1
63
MEM_MA_CLK_L1
64
VREF_DQ_A
1
VREF_CA_A
67
SMBCLK_DDR
118
SCL
SMBDATA_DDR
238
SDA
237
SA1
117
SA0
MEC2
MEC3
DDEIII-240_BLUE-R
DDEIII-240_BLUE-R
DIMM1(CHANNEL-A)
MEC3
ADDRESS = 0:0 [SA1:SA0]
SMBCLK_DDR
SMBDATA_DDR
MEM_MA_ODT0
MEM_MA_ODT1
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA_CS_L0
MEM_MA_CS_L1
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_WE_L
MEM_MA_RAS_L 7
MEM_MA_CAS_L
MEM_MA_CLK_H0 7
MEM_MA_CLK_L0 7
MEM_MA_CLK_H1
MEM_MA_CLK_L1
C135
C135
C0.1u16Y0402
C0.1u16Y0402
R173 33R0402R173 33R0402
R175 33R0402R175 33R0402
MEM_MA_ADD[15..0]
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2 7
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
C246
C246
C0.1u16Y0402
C0.1u16Y0402
SMBCLK 11,12,15,19,21,30,35,36
SMBDATA
7
DDR3_DRAMRST#A 7
11,12,15,19,21,30,35,36
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
Must stuff R173 R175
3
VCC_DDR VCC3
54
DIMM2
DIMM2
3
DQ0
VDD51VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
107
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
VSS
VSS
VSS
VSS
110
113
116
119
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95
98
101
104
170
173
176
179
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
121
124
127
130
133
136
139
142
145
148
151
2
182
183
186
VDD
VDD
VDD
VSS
VSS
VSS
154
157
160
VTT_DDR
189
191
194
197
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
163
166
199
202
205
236
VDDSPD
VSS
VSS
208
211
167
79
53
48
187
198
68
120
240
MEM_MA_ADD0
VTT
VTT
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
MSI
MSI
MSI
188
A0
MEM_MA_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MA_ADD2
61
A2
MEM_MA_ADD3
180
A3
MEM_MA_ADD4
59
A4
MEM_MA_ADD5
58
A5
MEM_MA_ADD6
178
A6
MEM_MA_ADD7
56
A7
MEM_MA_ADD8
177
A8
MEM_MA_ADD9
175
A9
MEM_MA_ADD10
70
A10/AP
MEM_MA_ADD11
55
A11
MEM_MA_ADD12
174
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
172
A14
171
A15
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
RESET#
CK1(NU)
CK1#(NU)
VREFDQ
VREFCA
VSS
VSS
MEC1
235
239
MEC1
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
MEM_MA_DQS_H2
25
DQS2
MEM_MA_DQS_L2
24
MEM_MA_DQS_H3
34
DQS3
MEM_MA_DQS_L3
33
MEM_MA_DQS_H4
85
DQS4
MEM_MA_DQS_L4
84
MEM_MA_DQS_H5
94
DQS5
MEM_MA_DQS_L5
93
MEM_MA_DQS_H6
103
DQS6
MEM_MA_DQS_L6
102
MEM_MA_DQS_H7
112
DQS7
MEM_MA_DQS_L7
111
43
DQS8
42
MEM_MA_DM0
125
126
MEM_MA_DM1
134
135
MEM_MA_DM2
143
144
MEM_MA_DM3
152
153
MEM_MA_DM4
203
204
MEM_MA_DM5
212
213
MEM_MA_DM6
221
222
MEM_MA_DM7
230
231
161
162
MEM_MA_ODT2
195
ODT0
MEM_MA_ODT3
77
ODT1
MEM_MA_CKE2
50
CKE0
MEM_MA_CKE3
169
CKE1
MEM_MA_CS_L2
193
CS0#
MEM_MA_CS_L3
76
CS1#
MEM_MA_BANK0
71
BA0
MEM_MA_BANK1
190
BA1
MEM_MA_BANK2
52
BA2
MEM_MA_WE_L
73
WE#
MEM_MA_RAS_L
192
RAS#
MEM_MA_CAS_L
74
CAS#
DDR3_DRAMRST#A
168
MEM_MA_CLK_H2
184
CK0
MEM_MA_CLK_L2
185
CK0#
MEM_MA_CLK_H3
63
MEM_MA_CLK_L3
64
VREF_DQ_A
1
VREF_CA_A
67
SMBCLK_DDR
118
SCL
SMBDATA_DDR
238
SDA
237
SA1
117
SA0
MEC2
MEC3
MEC2
MEC3
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Date:
Date:
VCC3
DDEIII-240_PINK-R
DDEIII-240_PINK-R
DIMM2(CHANNEL-A)
ADDRESS = 0:1 [SA1:SA0]
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
DDR3 Chanel-A DIMM1/2
DDR3 Chanel-A DIMM1/2
DDR3 Chanel-A DIMM1/2
Friday, March 19, 2010
Friday, March 19, 2010
Friday, March 19, 2010
C116
C116
C0.1u16Y0402
C0.1u16Y0402
MS-7588
MS-7588
MS-7588
1
MEM_MA_ODT2
MEM_MA_ODT3
MEM_MA_CKE2
MEM_MA_CKE3
MEM_MA_CS_L2
MEM_MA_CS_L3
MEM_MA_CLK_H2 7
MEM_MA_CLK_L2 7
MEM_MA_CLK_H3
MEM_MA_CLK_L3
Sheet of
Sheet of
Sheet of
7
7
7
7
7
7
7
7
C247
C247
C0.1u16Y0402
C0.1u16Y0402
10
10
10
1.3
1.3
1.3
38
38
38
5
www.vinafix.vn
4
3
2
1
DDRIII DIMM_B1 DDRIII DIMM_B2
VCC_DDR
MEM_MB_DATA[63..0]7
54
DIMM3
8
7
6
DIMM3
3
DQ0
VDD51VDD
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
107
110
113
116
119
Vref-DQ : Reference voltage for DQ0
DQS0
DQS7.
Vref-CA : Reference voltage for A0-A15, BA0
ODT1.
RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.
V1_8SET
VREF_DQ_A
VREF_DQ_B
122
123
128
129
131
132
137
138
140
141
146
147
149
150
155
156
200
201
206
207
209
210
215
216
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
101
104
V1_8SET
4
9
10
12
13
18
19
21
22
27
28
30
31
36
37
81
82
87
88
90
91
96
97
99
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95
98
MEM_MB_DATA0
D D
C C
Place close to DIMM3
VCC_DDR
C125
C125
C1u16Y
C1u16Y
Place close to DIMM3 with DIMM4
VCC_DDR
B B
VREF_CA_B
VREF_DQ_B
UPI VOLTAGE CONSOLE(3)
A A
C103
C103
C97
C97
C184
C184
VREF_CA_B
C108
C108
C0.1u16Y0402
C0.1u16Y0402
VREF_DQ_B
C243
C243
C0.1u16Y0402
C0.1u16Y0402
R401
R401
5VDIMM
X_3K/1%
X_3K/1%
C1u16Y
C1u16Y
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
C1u6.3Y0402-RH
R238
R238
R235
R235
1KR1%0402
1KR1%0402
R416
R416
R405
R405
1KR1%0402
1KR1%0402
VCC5 5VDIMM
R407
R407
X_9.1K/1%
X_9.1K/1%
SMBCLK
SMBDATA
1KR1%0402
1KR1%0402
1KR1%0402
1KR1%0402
R428
R428
X_0R
X_0R
R420 X_0RR420 X_0R
R419 X_0RR419 X_0R
5
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
VCC_DDR
C139
C139
X_C0.1u16Y0402
X_C0.1u16Y0402
VCC_DDR
0x68:RH=9.1K,RL=3K
R427
R427
U18
U18
X_0R
X_0R
1
VCC
2
BUS_SEL
5
SCL
4
SDA
3
GND
X_UP6262AMA8
X_UP6262AMA8
OUT1
OUT2
OUT3
170
173
176
179
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
121
124
127
130
133
136
139
142
145
148
151
VCC3
VTT_DDR
182
183
186
189
191
194
197
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
154
157
160
163
166
199
202
205
4
167
79
53
48
187
198
68
120
240
236
MEM_MB_ADD0
VTT
VTT
VDDSPD
VSS
208
211
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
DQ63, CB0 CB7 and PAR_IN. When in single ended mode used for
SMBCLK10,12,15,19,21,30,35,36
SMBDATA10,12,15,19,21,30,35,36
188
A0
MEM_MB_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MB_ADD2
61
A2
MEM_MB_ADD3
180
A3
MEM_MB_ADD4
59
A4
MEM_MB_ADD5
58
A5
MEM_MB_ADD6
178
A6
MEM_MB_ADD7
56
A7
MEM_MB_ADD8
177
A8
MEM_MB_ADD9
175
A9
MEM_MB_ADD10
70
A10/AP
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
RESET#
CK1(NU)
CK1#(NU)
VREFDQ
VREFCA
VSS
VSS
MEC1
235
239
MEC1
MEC2
BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and
SMBCLK
SMBDATA
MEM_MB_ADD11
55
A11
MEM_MB_ADD12
174
A12
MEM_MB_ADD13
196
A13
MEM_MB_ADD14
172
A14
171
A15
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
25
MEM_MB_DQS_L2
24
MEM_MB_DQS_H3
34
MEM_MB_DQS_L3
33
MEM_MB_DQS_H4
85
MEM_MB_DQS_L4
84
MEM_MB_DQS_H5
94
MEM_MB_DQS_L5
93
MEM_MB_DQS_H6
103
MEM_MB_DQS_L6
102
MEM_MB_DQS_H7
112
MEM_MB_DQS_L7
111
43
42
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
143
144
MEM_MB_DM3
152
153
MEM_MB_DM4
203
204
MEM_MB_DM5
212
213
MEM_MB_DM6
221
222
MEM_MB_DM7
230
231
161
162
MEM_MB_ODT0
195
ODT0
MEM_MB_ODT1
77
ODT1
MEM_MB_CKE0
50
CKE0
MEM_MB_CKE1
169
CKE1
MEM_MB_CS_L0
193
CS0#
MEM_MB_CS_L1
76
CS1#
MEM_MB_BANK0
71
BA0
MEM_MB_BANK1
190
BA1
MEM_MB_BANK2
52
BA2
MEM_MB_WE_L
73
WE#
MEM_MB_RAS_L
192
RAS#
MEM_MB_CAS_L
74
CAS#
168
MEM_MB_CLK_H0
184
CK0
MEM_MB_CLK_L0
185
CK0#
MEM_MB_CLK_H1
63
MEM_MB_CLK_L1
64
VREF_DQ_B
1
VREF_CA_B VREF_CA_B
67
SMBCLK_DDR SMBCLK_DDR
118
SCL
SMBDATA_DDR
238
SDA
237
SA1
SA0
MEC2
MEC3
MEC3
VCC3
117
DDEIII-240_BLUE-R
DDEIII-240_BLUE-R
DIMM3(CHANNEL-B)
ADDRESS = 1:0 [SA1:SA0]
C0.1u16Y0402
C0.1u16Y0402
SMBCLK_DDR
SMBDATA_DDR
MEM_MB_ADD[15..0]
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2 7
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_ODT0
MEM_MB_ODT1
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB_CS_L0
MEM_MB_CS_L1
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_WE_L
MEM_MB_RAS_L 7
MEM_MB_CAS_L
DDR3_DRAMRST#B 7
MEM_MB_CLK_H0 7
MEM_MB_CLK_L0 7
MEM_MB_CLK_H1
MEM_MB_CLK_L1
C111
C111
3
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
C255
C255
C0.1u16Y0402
C0.1u16Y0402
SMBCLK_DDR
SMBDATA_DDR
MEM_MB_DATA0
7
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
10
10
VCC_DDR VCC3
54
DIMM4
DIMM4
3
DQ0
VDD51VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
107
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
VSS
VSS
VSS
VSS
110
113
116
119
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95
98
101
104
170
173
176
179
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
121
124
127
130
133
136
139
142
145
148
151
2
182
183
186
VDD
VDD
VDD
VSS
VSS
VSS
154
157
160
VTT_DDR
189
191
194
197
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
163
166
199
202
205
236
VDDSPD
VSS
VSS
208
211
167
79
53
48
187
198
68
120
240
MEM_MB_ADD0
VTT
VTT
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
MSI
MSI
MSI
188
A0
MEM_MB_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MB_ADD2
61
A2
MEM_MB_ADD3
180
A3
MEM_MB_ADD4
59
A4
MEM_MB_ADD5
58
A5
MEM_MB_ADD6
178
A6
MEM_MB_ADD7
56
A7
MEM_MB_ADD8
177
A8
MEM_MB_ADD9
175
A9
MEM_MB_ADD10
70
A10/AP
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
RESET#
CK1(NU)
CK1#(NU)
VREFDQ
VREFCA
VSS
VSS
MEC1
235
239
MEC1
MEM_MB_ADD11
55
A11
MEM_MB_ADD12
174
A12
MEM_MB_ADD13
196
A13
MEM_MB_ADD14
172
A14
MEM_MB_ADD15MEM_MB_ADD15
171
A15
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
MEM_MB_DQS_H0
7
DQS0
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
DQS1
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
25
DQS2
MEM_MB_DQS_L2
24
MEM_MB_DQS_H3
34
DQS3
MEM_MB_DQS_L3
33
MEM_MB_DQS_H4
85
DQS4
MEM_MB_DQS_L4
84
MEM_MB_DQS_H5
94
DQS5
MEM_MB_DQS_L5
93
MEM_MB_DQS_H6
103
DQS6
MEM_MB_DQS_L6
102
MEM_MB_DQS_H7
112
DQS7
MEM_MB_DQS_L7
111
43
DQS8
42
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
143
144
MEM_MB_DM3
152
153
MEM_MB_DM4
203
204
MEM_MB_DM5
212
213
MEM_MB_DM6
221
222
MEM_MB_DM7
230
231
161
162
MEM_MB_ODT2
195
ODT0
MEM_MB_ODT3
77
ODT1
MEM_MB_CKE2
50
CKE0
MEM_MB_CKE3
169
CKE1
MEM_MB_CS_L2
193
CS0#
MEM_MB_CS_L3
76
CS1#
MEM_MB_BANK0
71
BA0
MEM_MB_BANK1
190
BA1
MEM_MB_BANK2
52
BA2
MEM_MB_WE_L
73
WE#
MEM_MB_RAS_L
192
RAS#
MEM_MB_CAS_L
74
CAS#
DDR3_DRAMRST#B
168
MEM_MB_CLK_H2
184
CK0
MEM_MB_CLK_L2
185
CK0#
MEM_MB_CLK_H3
63
MEM_MB_CLK_L3
64
VREF_DQ_B
1
67
118
SCL
SMBDATA_DDR
238
SDA
237
SA1
117
SA0
MEC2
MEC3
DDEIII-240_PINK-R
DDEIII-240_PINK-R
DIMM4(CHANNEL-B)
MEC2
MEC3
ADDRESS = 1:1 [SA1:SA0]
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
Size
Size
Size
Document Description Rev
Document Description Rev
Document Description Rev
Custom
Custom
Custom
DDR3 Chanel-B DIMM3/4
DDR3 Chanel-B DIMM3/4
DDR3 Chanel-B DIMM3/4
Friday, March 19, 2010
Friday, March 19, 2010
Friday, March 19, 2010
VCC3
C0.1u16Y0402
C0.1u16Y0402
MS-7588
MS-7588
MS-7588
1
MEM_MB_ODT2
MEM_MB_ODT3
MEM_MB_CKE2
MEM_MB_CKE3
MEM_MB_CS_L2
MEM_MB_CS_L3
MEM_MB_CLK_H2 7
MEM_MB_CLK_L2 7
MEM_MB_CLK_H3
MEM_MB_CLK_L3
C115
C115
Sheet ofDate:
Sheet ofDate:
Sheet ofDate:
7
7
7
7
7
7
7
7
C249
C249
C0.1u16Y0402
C0.1u16Y0402
11 38
11 38
11 38
1.3
1.3
1.3
5
www.vinafix.vn
4
3
2
1
CLOCK GEN STRAPING
FS4
FS3
FS2
FSB
FSA
CPU
B0b4
B0b3
B0b2
B0b1
0
0
3VSB VCC3
R524
R524
X_4.7K
SMBCLK
SMBDATA
C408
C408
0.1u/16X
0.1u/16X
C386
C386
0.1u/16X
0.1u/16X
R613
R613
R609
R609
X_4.7K
C387
C387
0.1u/16X
0.1u/16X
R5140RR514
1K/1%
1K/1%
R5560RR556
R568 0RR568 0R
C375
C375
0.1u/16X
0.1u/16X
33R
33R
X_1K/1%
X_1K/1%
R506
D D
VCC3
C C
VCC3
SLP_S5#15,18,30
SLP_S4#15,30,31,36
WDT#18,29,30
VRM_PGD15,30,35
FB6
FB6
X_FB80/8
X_FB80/8
CP9
CP9
X_COPPER
X_COPPER
FB4
FB4
X_FB80/8
X_FB80/8
CP7
CP7
X_COPPER
X_COPPER
CK_14P8M_PCH13
R506
X_1K/1%
X_1K/1%
R531
R531
WDT#
SMBCLK10,11,15,19,21,30,35,36
SMBDATA10,11,15,19,21,30,35,36
C414
C414
10u/10Y/8
10u/10Y/8
C374
C374
10u/10Y/8
10u/10Y/8
CK_14P8M_PCH FSA_14P8_REF
0R
0R
C402
C402
0.1u/16X
0.1u/16X
FSLB
DOC_0
DOC_1
TP7TP7
R541
R541
4.7K
4.7K
VCC3_CLK1
C411
C411
0.1u/16X
0.1u/16X
VCC3_CLK2
C376
C376
0.1u/16X
0.1u/16X
CK_RESET#
U29
U29
30
*RLATCH/RESET_IN#/RESET#
17
VTTPWRGD/WOL_STOP#
31
DOC_0**
32
DOC_1**
1
SCLK
2
SDATA
15
24_12M
16
48M/FSLB
29
25M
3
VDDCPU
7
VDDPCIEX
11
VDD96
22
VDDREF
25
VDDSATA
28
VDD25
19
REF/FSLA
CPUT_LR
CPUC_LR
PCIEXT_LR
PCIEXC_LR
DOT96T_LR
DOT96C_LR
SATACLKT_LR
SATACLKC_LR
GNDCPU
GNDPCIEX
GND96
GNDREF
GNDSATA
GND25
5
6
9
10
13
14
24
23
20
X1
21
X2
4
8
12
18
26
27
CLKGEN133M_P_R
CLKGEN133M_N_R
CLK100M_DMI_P_R
CLK100M_DMI_N_R
CLK96M_DOT_P_R
CLK96M_DOT_N_R
CLK100M_SATA_P_R
CLK100M_SATA_N_R
R5810RR581
R5860RR586
R6080RR608
R6180RR618
R6110RR611
R6100RR610
R5470RR547
R554 0RR554 0R
0R
0R
0R
0R
0R
0R
0R
Place damping resistor close to clock-gen
XTAL1
XTAL2
Y2
Y2
14.318MHZ16P_D
14.318MHZ16P_D
1 2
C397
C397
C394
C394
22p/50N
22p/50N
22p/50N
22p/50N
CLKGEN133M_P
CLKGEN133M_N
CLK100M_DMI_P
CLK100M_DMI_N 13
CLK96M_DOT_P
CLK96M_DOT_N
CLK100M_SATA_P
CLK100M_SATA_N
FSLB
13
13
13
Pin16: 48MHz clock output. / 3.3V tolerant input
13
for CPU frequency selection. Low voltage
threshold inputs, see input electrical
characteristics for Vil_FS and Vih_FS values.
Pin19: 14.318 MHz reference clock./ 3.3V
13
tolerant input for CPU frequency selection.
Refer to input electrical characteristics for
13
13
Vil_FS and Vih_FS values.
0
0
0
R612
R612
R627
R627
00
0
0
001
0
0
0
1
11
0
0
VCC3 VCC3
X_4.7K
X_4.7K
4.7K
4.7K
B0b0
Mhz
100.00
133.33
200.00
166.66
FSA_14P8_REF
Spread
%
-0.5
-0.5
-0.5
-0.5
R601
R601
R595
R595
4.7K
4.7K
X_4.7K
X_4.7K
ICS9LPRS4105B
ICS9LPRS4105B
X_0R
X_0R
0R
X_0R
X_0R
VCC3
VCC3
B B
DOC_1
R535
R535
SIO_GPIO27
DOC_0
SIO_GPIO26
R5160RR516
R536
R536
R505 0RR505 0R
SIO_GPIO2718
SIO_GPIO2618
A A
5
R526
R526
8.2K/4
8.2K/4
R527
R527
8.2K/4
8.2K/4
OC_SW1
OFF / ON
2A22B
ON
ON
ON
ON
1A11B
4
N73-0200081-D02
4
OFF
OFF
OFF
OFF
OC_SW1
OC_SW1
3
SW-DIPP2-RH
SW-DIPP2-RH
( Default ) OFF / OFF
OFF / ON
ON / OFF
ON / ON
OFF=1 ; ON=0
DOC
01
133 MHz ( default )
1
1
142 MHz
1
0
150 MHz
0
1
166 MHz
0
0
TABLE
CPU FREQUENCY
3
EMI
CK_14P8M_PCH
C413
C413
X_10p/50N
X_10p/50N
2
DOC_0**:Dynamic Over Clocking pin: real time
frequency selection 0: Normal; 1: Frequency will
transition to a preprogrammed value in the I2C.
MSI
MSI
MSI
OC
DOC_0
DOC_1
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7636
MS-7636
Size
Size
Size
Document Description Rev
Document Description Rev
Document Description Rev
Custom
Custom
Custom
Date:
Friday, March 19, 2010
Date:
Friday, March 19, 2010
Date:
Friday, March 19, 2010
MS-7636
CLK ICS9LRS4105B
CLK ICS9LRS4105B
CLK ICS9LRS4105B
X_4.7K
X_4.7K
R548
R548
R549 X_4.7KR549 X_4.7K
1
12 38
12 38
12 38
Sheet of
Sheet of
Sheet of
1.3
1.3
1.3
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