MSI MS-7511V1.3 7511V1.3
5
4
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PageTitle
MS-7511
ATX(305mm X 220mm)
D D
CPU:
AMD AM2/AM2+ Socket940
System Chipset:
North Bridge --South Bridge --- NA
OnBoard Chipset:
Clock Gen:NA
AZALIA Codec:ALC888
C C
LAN Chip: REL8211BL
SIO:Fintek 71882(with smart fan control-3/4 pin co-lay)
Flash ROM:8MB SPI (MCP)
Main Memory:
DDRII* 4 (Dual Channel)
Expansion Slots:
PCI Express (X16) Slot * 1
B B
PCI Express (X1) Slot * 2
PCI Slot * 3
PWM:
Controller:STL6740L+6741
ACPI:
UPI solution
Other:
FDD *1
SATA(SATA2-300MB/s) * 6
A A
USB2.0 *10 (Rear*4 Front*6)
COM PORT *1
LPT PORT *1
5
MCP78
4
3
Cover Sheet 1
Block Diagram 2
Device Map
GPIO Table 4
Clock Distribution
CPU:AM2+
DDR2 DIMM(Dual Channel)
MCP78
SIO FINTEK 71882
Serial/Parallel Port/DLED
Azalia ALC888
LAN Realtek 8211BL
1394 JMicron 381
PCIEX16 &X1 SLOT
PCI Slot 1&2&3
VGA&DVI CONNECTOR
USB CONNECTORS
IDE&FAN CONNECTORS
ACPI UPI Solution&POS
Chip Core&VCC_DDR
VRM ST6740+6741
Fintek75125&UP6262
ATX/Front Panel
For EMI
MANUAL PARTS
Power Delivery
POWER OK MAP
RESET MAP
MB power Sequence
History
Title
Title
Title
COVER SHEET
COVER SHEET
COVER SHEET
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
Date: Sheet
Date: Sheet
2
Date: Sheet
3
5
6,7,8
9,10,11
12 ~ 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
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140Thursday, April 24, 2008
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140Thursday, April 24, 2008
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140Thursday, April 24, 2008
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UNBUFFERED DDR
CHANNEL_A DIMM2,4
240-PIN DDRII
UNBUFFERED DDR
CHANNEL_B DIMM1,3
240-PIN DDRII
CRT
DVI
DDR 667/800
DDRII
DDR 667/800
VGA CON
DVI CON
AMD
VRM ST 6740L+6741
3+1-Phase PWM
D D
Fintek 75125
/uP6262 OV
PCIE X16
PCIE X1 *2
1394 JMicron 381
PCIE X16
PCIE X1
PCIE X1
HyperTransport
AM2+_940
1G
nVIDIA
LINK0
16x16
MCP78
C C
Rear port x 4
USB2.0
Front port x 6
RGMII
AC LINK
SATA-II Link
Giga LAN_ Realtek8211BL
Azalia CODEC
ALC888(8CH)
SATA-II Port
#1~2 #3~4 #5~6
PCI BUS
B B
A A
5
PCI SLOT x3
ACPI
UPI SOLUTION
Fintek 882
KB &
FLOPPY
LPT
*1 *1 *1 *1
4
MOUSE
SERIAL
PORTS
FAN
CONTROL
LPC
TPM Pin
Header
3
SPI SPI
Header
SPI FLASH ROMSPI Pin
8M
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
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DDR DIMM Config.
DEVICE
DIMM 1
CH-A
D D
DIMM 3
10100000B
10100010B
CH-A
DIMM 2
CH-B
DIMM 4
CH-B
USB
C C
Rear
Front
B B
10100001B
10100011B
Port DATA +/-
LAN_USB1
USB1
JUSB1
JUSB2
JUSB3
JUSB4
CLOCKADDRESS
MEM_MA0_CLK_H0/L0
A0H
MEM_MA0_CLK_H1/L1
MEM_MA0_CLK_H2/L2
MEM_MA1_CLK_H0/L0
A2H
MEM_MA1_CLK_H1/L1
MEM_MA1_CLK_H2/L2
MEM_MB0_CLK_H0/L0
A4H
MEM_MB0_CLK_H1/L1
MEM_MB0_CLK_H2/L2
MEM_MB1_CLK_H0/L0
A6H
MEM_MB1_CLK_H1/L1
MEM_MB1_CLK_H2/L2
OC#
USB0USB0+
USB1USB1+
USB2USB2+
USB3USB3+
USB4USB4+
USB5USB5+
USB6USB6+
USB7USB7+
USB8USB8+
USB9USB9+
USB10USB10+
USB11USB11+
USB_OC0
USB_OC1
USB_OC3
USB_OC4
USB_OC5
PCI Config.
DEVICE MCP1 INT Pin
PCI_INT#X
PCI Slot 1
PCI_INT#Y
PCI_INT#Z
PCI_INT#W
PCI_INT#W
PCI Slot 2
PCI_INT#X
PCI_INT#Y
PCI_INT#Z
PCI_INT#Z
PCI Slot 3
PCI_INT#W
PCI_INT#X
PCI_INT#Y
TPM
Chipset
LPC
REQ#/GNT#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI DEVICE RESET MAP
MCP78
Signals
PCI_RESET#0
PCI_RESET#1
PCI_RESET#2
LPC_RESET#
Target
PCISLOT1
PCISLOT2
PCISLOT3
SIO/TPM
IDSEL
AD21
AD22
AD23
CLOCK
PCI_CLKSLOT1
(PCI_CLK0)
PCI_CLKSLOT2
(PCI_CLK1)
PCI_CLKSLOT3
(PCI_CLK2)
PCICLK_TPM
(TPM_CLK)
PCI_CLKIN
(PCICLK4)
LPC_CLK
LPC_SIO24MSIO
CPU VID TABLE
VID
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000 1.1500V
10001
10010
10011 1.0750V
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
VOLTAGE
1.5500V
1.5250V
1.5000V
1.4750V
1.4500V
1.4250V
1.4000V
1.3750V
1.3500V
1.3250V
1.3000V
1.2750V
1.2500V
1.2250V
1.2000V
1.1750V
1.1250V
1.1000V
1.0500V
1.0250V
1.0000V
0.9750V
0.9500V
0.9250V
0.9000V
0.8750V
0.8500V
0.8250V
0.8000V
0.7750V
IDE_RESET# IDE
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
DEVICE MAP
DEVICE MAP
DEVICE MAP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
5
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Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
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340Thursday, April 24, 2008
340Thursday, April 24, 2008
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D D
C C
4
3
2
1
B B
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
GPIO TABLE
GPIO TABLE
GPIO TABLE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
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Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
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440Thursday, April 24, 2008
440Thursday, April 24, 2008
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AMD
HT_CPU_RXCLK[1:0]#
D D
HT_CPU_RXCLK[1:0]
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
CPUCLK_IN[1:0]
CPUCLK_IN[1:0]#
NVIDIA
CLKOUT_200MHZ
CLKOUT_200MHZ#
C C
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
HT_CPU_RXCLK[1:0]
HT_CPU_RXCLK[1:0]#
AM2+
MEMORY_A0_CLK[2:0]
MEMORY_A0_CLK[2:0]#
MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]#
MCP78
PE0_REFCLK
PE0_REFCLK#
PE2_REFCLK
PE2_REFCLK#
PE3_REFCLK
PE3_REFCLK#
PE1_REFCLK
PE1_REFCLK#
BUF_SIO
LPC_CLK0
3 PAIR MEM CLK
3 PAIR MEM CLK
LPC_SIO24M
LPC_CLK
DIMM1-CHADIMM2-CHB
Dual Chanel
PEX_X16
PEX_X1
PEX_X1
JMicron 381
SIO
PCI_CLK0
B B
SPI_CLK
SPI ROM
32.768 KHZ
A A
25 MHZ
5
RTC_XTAL
XTAL_IN
XTAL_OUT
4
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN
HDA_BITCLK
MII_TXCLK
MII_RXCLK
BUF_25MHZ
PCI_CLK0
PCI_CLK1
PCI_CLK2
TPM_CLK)
HDA_BITCLK
MII_TXCLK
BUF_25MHZ
3
MII_RXCLK
PCI_SLOT1
PCI_SLOT2
PCI_SLOT3
TPM
HEADER
HDA
CODEC
HDA_BITCLK
LAN
PHY
MII_TXCLK
MII_RXCLK
BUF_25MHZ
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
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540Thursday, April 24, 2008
540Thursday, April 24, 2008
540Thursday, April 24, 2008
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HT_CADIN_H[15..0]12
HT_CADIN_L[15..0]12
HT_CADOUT_H[15..0]12
HT_CADOUT_L[15..0]12
D D
HT_CLKIN_H112
HT_CLKIN_L112
HT_CLKIN_H012
HT_CLKIN_L012
HT_CTLIN_H112
HT_CTLIN_L112
HT_CTLIN_H012
HT_CTLIN_L012
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
C C
B B
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
U12A
U12A
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
HT_CLKOUT_H1 12
HT_CLKOUT_L1 12
HT_CLKOUT_H0 12
HT_CLKOUT_L0 12
HT_CTLOUT_H1 12
HT_CTLOUT_L1 12
HT_CTLOUT_H0 12
HT_CTLOUT_L0 12
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3HT_CADIN_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
Layout : Place R114
within 0.5 inch of CPU
CPU_CLK12
CPU_CLK#12
VCC_DDR
C89 C3900p16X0402-RHC89 C3900p16X0402-RH
C94
C94
C3900p16X0402-RH
C3900p16X0402-RH
8/4/8
R148
R148
39.2R1%0402
39.2R1%0402
R154
R154
Layout : 12:4:12
within 1 inch of CPU
39.2R1%0402
39.2R1%0402
VCC_DDR
VCC_DDR
THERMDC_CPU19
THERMDA_CPU19
VDDA_25
R114
R114
169R1%0402
169R1%0402
R145 1KR0402R145 1KR0402
R146 X_1KR0402R146 X_1KR0402
TP23TP23
TP16TP16
TP15TP15
TP22TP22
R490 300R0402R490 300R0402
COREFB+31,32
COREFB-31
TP11TP11
CPU_M_VREF
R106 300R0402R106 300R0402
R110 300R0402R110 300R0402
TP7TP7
TP8TP8
TP10TP10
TP5TP5
TP12TP12
L1
L1
80L3A-100_0805
80L3A-100_0805
CPUCLKIN
CPUCLKIN#
LDT_PWRGD
LDT_STOP#
LDT_RST#
CPU_PRESENT_L
THERM_SIC
THERM_SID
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB+
COREFBCPU_VTT_SENSE
CPU_MEMZN
CPU_MEMZP
CPU_TEST25_H
CPU_TEST25_L
VDDA25
C71
C71
CPU_TEST19
CPU_TEST18
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
CPU_TEST12
C73
C73
C0.22u16X
C0.22u16X
C4.7u10Y0805
C4.7u10Y0805
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AK6
AL10
AJ10
AH10
AL9
A5
G2
G1
E12
F12
AH11
AJ11
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
C77
C77
C3300p50X0402
C3300p50X0402
U12D
U12D
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
THERMTRIP_L
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
VCC_DDR
R19
R19
1KR0402
1KR0402
VID5
D2
VID4
D1
VID3
C1
VID2
E3
VID1
E2
VID0
E1
CPU_THRIP#
AK7
CPU_PROCHOT#
AL7
CPU_TDO
AK10
CPU_DBRDY
B6
CPU_VDDIOFB_H
AK11
CPU_VDDIOFB_L
AL11
CPU_PSI_L
F1
HTREF1
V8
HTREF0
V7
TEST29_H
C11
TEST29_L
D11
CPU_TEST24
AK8
CPU_TEST23
AH8
CPU_TEST22
AJ9
CPU_TEST21
AL8
CPU_TEST20
AJ8
J10
H9
CPU_TEST27
AK9
CPU_TEST26
AK5
G7
D4
R157 300R0402R157 300R0402
CRB: AMD DG TEST[21,26] NC or TP
R488
R488
R20
R20
1KR0402
1KR0402
TP20TP20
TP6TP6
TP21TP21
CPU_PSI_L 31
R115
R115
80.6R1%0402
80.6R1%0402
Layout : Route 80ohm diff. impedence
Place within 0.5 inch of CPU
TP19TP19
TP14TP14
R489 300R0402R489 300R0402
R147 300R0402R147 300R0402
TP13TP13
TP18TP18
Layout : Place at
controller
X_1KR0402
X_1KR0402
VID5 32
VID4 32
VID3 32
VID2 32
VID1 8,32
CPU_THRIP# 12
CPU_PROCHOT# 12
CPU_VDDIOFB_H 30
Layout : Place within
1.0 inch of CPU
C214
C214
C1000p50X0402
C1000p50X0402
VID0 32
C215
C215
C1000p50X0402
C1000p50X0402
VCC_DDR
1.2V_HT
R155 44.2R1%0402-RHR155 44.2R1%0402-RH
R151 44.2R1%0402-RHR151 44.2R1%0402-RH
VCC_DDR
RN5
RN5
1
Layout:15mil width Place
VCC_DDR
within 0.5 inch of CPU
C85
C85
C0.1U16X0402
C0.1U16X0402
CPU_M_VREF
C90
C90
C1000p50X0402
C1000p50X0402
2
R108
R108
15R1%0805
15R1%0805
R107
R107
15R1%0805
15R1%0805
A A
5
4
3
LDT_RST#12
LDT_PWRGD12,31,32
LDT_STOP#12
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
LDT_RST#
LDT_PWRGD
LDT_STOP#
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
PU HT I/F
PU HT I/F
PU HT I/F
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
3
5
7
8P4R-300R-RH
8P4R-300R-RH
R156 X_1KR0402R156 X_1KR0402
R111 510R0402R111 510R0402
R113 510R0402R113 510R0402
1
2
4
6
8
640Thursday, April 24, 2008
640Thursday, April 24, 2008
640Thursday, April 24, 2008
VCC_DDR
of
of
of
5
4
3
2
1
MEM_MA_DQS_L[7..0]9,10
MEM_MA_DQS_H[7..0]9,10
MEM_MA_DM[7..0]9,10
MEM_MA_DATA[63..0]9,10 MEM_MB_DATA[63..0]9,10
D D
C C
B B
MEM_MA_ADD[15..0]9,10,11 MEM_MB_ADD[15..0]9,10,11
U12B
MEM_MA0_CLK_H29,11
MEM_MA0_CLK_L29,11
MEM_MA0_CLK_H19,11
MEM_MA0_CLK_L19,11
MEM_MA0_CLK_H09,11
MEM_MA0_CLK_L09,11
MEM_MA0_CS_L19,11
MEM_MA0_CS_L09,11
MEM_MA0_ODT09,11
MEM_MA1_CLK_H210,11
MEM_MA1_CLK_L210,11
MEM_MA1_CLK_H110,11
MEM_MA1_CLK_L110,11
MEM_MA1_CLK_H010,11
MEM_MA1_CLK_L010,11
MEM_MA1_CS_L110,11
MEM_MA1_CS_L010,11
MEM_MA1_ODT010,11
MEM_MA_CAS_L9,10,11
MEM_MA_WE_L9,10,11
MEM_MA_RAS_L9,10,11
MEM_MA_BANK29,10,11
MEM_MA_BANK19,10,11
MEM_MA_BANK09,10,11
MEM_MA_CKE110,11
MEM_MA_CKE09,11
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CS_L1
MEM_MA1_CS_L0
MEM_MA1_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
U12B
AG21
AG20
G19
H19
U27
U26
AC25
AA24
AC28
AE20
AE19
G20
G21
V27
W27
AD27
AA25
AC27
AB25
AB27
AA26
N25
Y27
AA27
L27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MB0_CLK_H29,11
MEM_MB0_CLK_L29,11
MEM_MB0_CLK_H19,11
MEM_MB0_CLK_L19,11
MEM_MB0_CLK_H09,11
MEM_MB0_CLK_L09,11
MEM_MB0_CS_L19,11
MEM_MB0_CS_L09,11
MEM_MB0_ODT09,11
MEM_MB1_CLK_H210,11
MEM_MB1_CLK_L210,11
MEM_MB1_CLK_H110,11
MEM_MB1_CLK_L110,11
MEM_MB1_CLK_H010,11
MEM_MB1_CLK_L010,11
MEM_MB1_CS_L110,11
MEM_MB1_CS_L010,11
MEM_MB1_ODT010,11
MEM_MB_CAS_L9,10,11
MEM_MB_WE_L9,10,11
MEM_MB_RAS_L9,10,11
MEM_MB_BANK29,10,11
MEM_MB_BANK19,10,11
MEM_MB_BANK09,10,11
MEM_MB_CKE110,11
MEM_MB_CKE09,11
MEM_MB_DQS_H[7..0]9,10
MEM_MB_DQS_L[7..0]9,10
MEM_MB_DM[7..0]9,10
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CS_L1
MEM_MB1_CS_L0
MEM_MB1_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
U12C
U12C
AJ19
AK19
A18
A19
U31
U30
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
PU MEM I/F
PU MEM I/F
PU MEM I/F
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
of
740Thursday, April 24, 2008
740Thursday, April 24, 2008
740Thursday, April 24, 2008
5
VCCP_NB
VCCP
D D
VCCP_NB
C C
B B
PLACE on CPU bottom side
VCCP
C572
C572
C10u6.3X50805
C10u6.3X50805
VCC_DDR
C552
A A
C552
C10u6.3X50805
C10u6.3X50805
A4
A6
AA8
AA10
AA12
AA14
AA16
AA18
AB7
AB9
AB11
AC4
AC5
AC8
AC10
AD2
AD3
AD7
AD9
AE10
AF7
AF9
AG4
AG5
AG7
AH2
AH3
B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8
E10
F5
F7
F9
F11
G6
G8
G10
G12
H7
H11
H23
J8
J12
J14
J16
J18
J20
J22
J24
K7
K9
K11
K13
K15
K17
K19
K21
K23
L4
L5
L8
L10
L12
Y17
Y19
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
VCCP
C568
C568
C10u6.3X50805
C10u6.3X50805
C554
C554
C555
C555
X_C10u6.3X50805
X_C10u6.3X50805
5
U12F
U12F
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C599
C599
C600
C600
C0.22u10X
C0.22u10X
C551
C551
C10u6.3X50805
C10u6.3X50805
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C584
C584
C593
C593
C1u16Y
C1u16Y
X_C0.22u10X
X_C0.22u10X
C561
C561
X_C0.22u10X
X_C0.22u10X
X_C10u6.3X50805
X_C10u6.3X50805
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
C579
C579
C1u16Y
C1u16Y
X_C4.7u6.3X5
X_C4.7u6.3X5
C564
C564
C562
C562
C0.22u10X
C0.22u10X
X_C2.2u6.3X5
X_C2.2u6.3X5
CPU_SLOTOCC# 32
C601
C601
C597
C597
C10000p10X0402
C10000p10X0402
C10000p10X0402
C10000p10X0402
C559
C559
C180p50N0402
C180p50N0402
VCCP
VCCP_NB
4
C563
C563
4
U12G
U12G
L14
VDD
L16
VDD
L18
VDD
M2
VDD
M3
VDD
M7
VDD
M9
VDD
M11
VDD
M13
VDD
M15
VDD
M17
VDD
M19
VDD
N8
VDD
N10
VDD
N12
VDD
N14
VDD
N16
VDD
N18
VDD
P7
VDD
P9
VDD
P11
VDD
P13
VDD
P15
VDD
P17
VDD
P19
VDD
R4
VDD
R5
VDD
R8
VDD
R10
VDD
R12
VDD
R14
VDD
R16
VDD
R18
VDD
R20
VDD
T2
VDD
T3
VDD
T7
VDD
T9
VDD
T11
VDD
T13
VDD
T15
VDD
T17
VDD
T19
VDD
T21
VDD
U8
VDD
U10
VDD
U12
VDD
U14
VDD
U16
VDD
U18
VDD
U20
VDD
V9
VDD
V11
VDD
V13
VDD
V15
VDD
V17
VDD
V19
VDD
V21
VDD
W4
VDD
W5
VDD
W8
VDD
W10
VDD
W12
VDD
W14
VDD
W16
VDD
W18
VDD
W20
VDD
Y2
VDD
Y3
VDD
Y7
VDD
Y9
VDD
Y11
VDD
Y13
VDD
Y15
VDD
Y21
VDD
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
C560
C560
X_C10u16Y1206
X_C10u16Y1206
X_C10u6.3X50805
X_C10u6.3X50805
VTT_DDR
C553
C553
X_C10u6.3X50805
X_C10u6.3X50805
C558
C558
X_C10u6.3X50805
X_C10u6.3X50805
C93
C93
C607
C607
C0.22u10X
C0.22u10X
AK20
VSS
AK22
VSS
AK24
VSS
AK26
VSS
AK28
VSS
AK30
VSS
AL5
VSS
B4
VSS
B9
VSS
B11
VSS
B14
VSS
B16
VSS
B18
VSS
B20
VSS
B22
VSS
B24
VSS
B26
VSS
B28
VSS
B30
VSS
C3
VSS
D14
VSS
D16
VSS
D18
VSS
D20
VSS
D22
VSS
D24
VSS
D26
VSS
D28
VSS
D30
VSS
E11
VSS
F4
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
G9
VSS
G11
VSS
H8
VSS
H10
VSS
H12
VSS
H14
VSS
H16
VSS
H18
VSS
H22
VSS
H24
VSS
H26
VSS
H28
VSS
H30
VSS
J4
VSS
J5
VSS
J7
VSS
J9
VSS
J11
VSS
J13
VSS
J15
VSS
J17
VSS
J19
VSS
J21
VSS
J23
VSS
K2
VSS
K3
VSS
K8
VSS
K10
VSS
K12
VSS
K14
VSS
K16
VSS
K18
VSS
K20
VSS
K22
VSS
Y18
VSS
C556
C556
X_C10u16Y1206
X_C10u16Y1206
C10000p10X0402
C10000p10X0402
VCCP
C566
C566
C565
C565
X_C10000p10X0402
X_C10000p10X0402
X_C10000p10X0402
X_C10000p10X0402
3
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
1
2
3
4
5
6
7
8
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
2
3
4
5
6
7
8
VTT_DDR
1.2V_HT
1.2V_HT
U12H
U12H
C236
C236
C83
C83
C1u16Y
C1u16Y
C10u6.3X50805
C10u6.3X50805
C210
C210
C0.22u16X
C0.22u16X
C229
C229
X_C4.7u10Y0805
X_C4.7u10Y0805
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C66
C66
X_C4.7u6.3X5
X_C4.7u6.3X5
C212
C212
X_C0.22u16X
X_C0.22u16X
C226
C226
C4.7u10Y0805
C4.7u10Y0805
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
C240
C240
X_C4.7u6.3X5
X_C4.7u6.3X5
C234
C234
X_C0.22u16X
X_C0.22u16X
C230
C230
X_C4.7u6.3X5
X_C4.7u6.3X5
C216
C216
X_C0.22u16X
X_C0.22u16X
C227
C227
C1u16Y
C1u16Y
C219
C219
C232
C232
X_C0.22u16X
X_C0.22u16X
VCC_DDR
C60
C60
C61
C61
C1u16Y
C1u16Y
X_C4.7u6.3X5
X_C4.7u6.3X5
X_C0.22u16X
X_C0.22u16X
C237
C237
C0.22u16X
C0.22u16X
1.2V_HT
VTT_DDR
L25
L26
L31
L30
W26
W25
AE27
U24
V24
AE28
Y31
Y30
AG31
V31
W31
AF31
C70
C70
X_C4.7u6.3X5
X_C4.7u6.3X5
C225
C225
C4.7u10Y0805
C4.7u10Y0805
C218
C218
X_C180p50N0402
X_C180p50N0402
2
U12I
U12I
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4
D12
VTT
C12
VTT
B12
VTT
A12
VTT
AB24
VDDIO
AB26
VDDIO
AB28
VDDIO
AB30
VDDIO
AC24
VDDIO
AD26
VDDIO
AD28
VDDIO
AD30
VDDIO
AF30
VDDIO
M24
VDDIO
M26
VDDIO
M28
VDDIO
M30
VDDIO
P24
VDDIO
P26
VDDIO
P28
VDDIO
P30
VDDIO
T24
VDDIO
T26
VDDIO
T28
VDDIO
T30
VDDIO
V25
VDDIO
V26
VDDIO
V28
VDDIO
V30
VDDIO
Y24
VDDIO
Y26
VDDIO
Y28
VDDIO
Y29
VDDIO
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
U12E
U12E
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
C68
C68
C0.22u10X
C0.22u10X
C221
C221
X_C180p50N0402
X_C180p50N0402
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
C79
C79
C76
C76
C88
C88
C0.22u10X
C0.22u10X
X_C0.22u10X
X_C0.22u10X
X_C0.22u10X
X_C0.22u10X
VCCP VCC_DDR
C98 X_C2.2u6.3X5C98 X_C2.2u6.3X5
VCCP VCCP_NB
C86 X_C2.2u6.3X5C86 X_C2.2u6.3X5
C81 X_C2.2u6.3X5C81 X_C2.2u6.3X5
2
E20
B19
AL4
AK4
AK3
F2
F3
G4
G3
G5
AD25
AE24
AE25
AJ18
AJ20
C18
C20
G24
G25
H25
V29
W30
C242
C242
C10000p10X0402
C10000p10X0402
1
H6
VLDT_B1
H5
VLDT_B2
H2
VLDT_B3
H1
VLDT_B4
AK12
VTT
AJ12
VTT
AH12
VTT
AG12
VTT
AL12
VTT
K24
VSS
K26
VSS
K28
VSS
K30
VSS
L7
VSS
L9
VSS
L11
VSS
L13
VSS
L15
VSS
L17
VSS
L19
VSS
L21
VSS
L23
VSS
M8
VSS
M10
VSS
M12
VSS
M14
VSS
M16
VSS
M18
VSS
M20
VSS
M22
VSS
N4
VSS
N5
VSS
N7
VSS
N9
VSS
N11
VSS
N13
VSS
N15
VSS
R144 0R0402R144 0R0402
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
VLDT_RUN_B
VTT_DDR
VCC_DDR
R149
R149
X_1KR0402
X_1KR0402
VCCP_NB_SENSE 31,32
VCCP_NB# 31
CPU_CORETYPE# 31,32
R118 X_300R0402R118 X_300R0402
R119 X_300R0402R119 X_300R0402
VCCP_NB
C75
C75
C10u6.3X50805
C10u6.3X50805
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
PU PWR&GND
PU PWR&GND
PU PWR&GND
C125
C125
C136
C136
C4.7u6.3X5
C4.7u6.3X5
C10000p10X0402
C10000p10X0402
CPU_THERM_ALERT# 17
VCC_DDR
VID1 6,32
C74
C74
C91
C91
C0.22u10X
C0.22u10X
X_C10u6.3X50805
X_C10u6.3X50805
VCC_DDR
C2
C2
C1
C1
X_C10u6.3X50805
X_C10u6.3X50805
X_C10u6.3X50805
X_C10u6.3X50805
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
C113
C113
C118
C118
C10000p10X0402
C10000p10X0402
X_C10000p10X0402
X_C10000p10X0402
C87
C87
C97
C97
C1u16Y
C1u16Y
X_C0.22u10X
X_C0.22u10X
C3
C3
X_C10u6.3X50805
X_C10u6.3X50805
of
840Monday, April 28, 2008
840Monday, April 28, 2008
840Monday, April 28, 2008
C95
C95
C10000p10X0402
C10000p10X0402
5
4
3
2
1
MEM_MA_DQS_H[7..0]7,10
MEM_MA_DQS_L[7..0]7,10
MEM_MA_DATA[63..0]7,10
MEM_MA_ADD[15..0]7,10,11
MEM_MA_DM[7..0]7,10
D D
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
C C
B B
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
DIMM1
DIMM1
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
VCC_DDR
102
68
19
55
3
4
9
2
5
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC2
NC1
RC118RC0
VDD51VDD56VDD62VDD72VDD78VDD
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
124
170
191
194
181
175
75
VDD
VDD
VDD
VDD
VDDQ
VDDQ53VDDQ59VDDQ64VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
127
130
133
136
139
142
145
148
151
154
157
197
172
VDDQ
VDDQ69VDDQ
VSS
VSS
VSS
160
163
166
VCC3
187
184
189
67
178
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
169
198
201
204
207
VDDQ
VSS
210
238
VSS
213
VDDSPD
VSS
VSS
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
228
161
162
167
168
CB5
CB6
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
SCL
SDA
VREF
SA0
SA1
SA2
VSS
VSS
VSS
VSS
DDRII-240_GREEN-RH
DDRII-240_GREEN-RH
231
234
237
CB7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
X1
X2
X3
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
54
190
71
73
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
MEM_MA0_CS_L0
193
MEM_MA0_CS_L1
76
MEM_MA0_CLK_H0
185
MEM_MA0_CLK_L0
186
MEM_MA0_CLK_H1
137
MEM_MA0_CLK_L1
138
MEM_MA0_CLK_H2
220
MEM_MA0_CLK_L2
221
SMB_MEM_CLK
120
SMB_MEM_DATA
119
1
X1
239
240
101
X2
X3
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_RAS_L
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA0_ODT0
MEM_MA_CKE0
VDDR_VREF
MEM_MA_BANK2 7,10,11
MEM_MA_BANK1 7,10,11
MEM_MA_BANK0 7,10,11
MEM_MA_WE_L 7,10,11
MEM_MA_CAS_L 7,10,11
MEM_MA_RAS_L 7,10,11
MEM_MA0_ODT0 7,11
MEM_MA_CKE0 7,11
MEM_MA0_CS_L0 7,11
MEM_MA0_CS_L1 7,11
MEM_MA0_CLK_H0 7,11
MEM_MA0_CLK_L0 7,11
MEM_MA0_CLK_H1 7,11
MEM_MA0_CLK_L1 7,11
MEM_MA0_CLK_H2 7,11
MEM_MA0_CLK_L2 7,11
VDDR_VREF
PLACE CLOSE TO DIMM PIN
MEM_MB_DQS_H[7..0]7,10
MEM_MB_DQS_L[7..0]7,10
MEM_MB_DM[7..0]7,10
MEM_MB_DATA[63..0]7,10
MEM_MB_ADD[15..0]7,10,11
DIMM2
DIMM2
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
VCC_DDR
102
68
19
55
3
4
9
2
5
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC2
NC1
RC118RC0
VDD51VDD56VDD62VDD72VDD78VDD
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
170
191
194
181
175
75
VDD
VDD
VDD
VDD
VDDQ
VDDQ53VDDQ59VDDQ64VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
139
142
145
148
151
154
157
197
172
187
VDDQ
VDDQ69VDDQ
VSS
VSS
VSS
160
163
166
169
VDDQ
VSS
VCC3
C247
C247
X_C0.1u16Y0402
X_C0.1u16Y0402
184
189
67
178
VDDQ
VDDQ
VSS
VSS
VSS
198
201
204
207
VDDQ
VSS
210
VSS
238
VDDSPD
VSS
VSS
213
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
161
162
CB5
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
A10_AP
A16/BA2
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
VSS
VSS
VSS
228
231
234
167
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
237
CB6
WE#
CAS#
RAS#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
VREF
VSS
168
CB7
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
28
MEM_MB_DQS_L2
27
MEM_MB_DQS_H3
37
MEM_MB_DQS_L3
36
MEM_MB_DQS_H4
84
MEM_MB_DQS_L4
83
MEM_MB_DQS_H5
93
MEM_MB_DQS_L5
92
MEM_MB_DQS_H6
105
MEM_MB_DQS_L6
104
MEM_MB_DQS_H7
114
MEM_MB_DQS_L7
113
46
45
MEM_MB_ADD0
188
A0
MEM_MB_ADD1
183
A1
MEM_MB_ADD2
63
A2
MEM_MB_ADD3
182
A3
MEM_MB_ADD4
61
A4
MEM_MB_ADD5
60
A5
MEM_MB_ADD6
180
A6
MEM_MB_ADD7
58
A7
MEM_MB_ADD8
179
A8
MEM_MB_ADD9
177
A9
MEM_MB_ADD10
70
MEM_MB_ADD11
57
A11
MEM_MB_ADD12
176
A12
MEM_MB_ADD13
196
A13
MEM_MB_ADD14
174
A14
MEM_MB_ADD15
173
A15
MEM_MB_BANK2
54
MEM_MB_BANK1
190
BA1
MEM_MB_BANK0
71
BA0
MEM_MB_WE_L
73
MEM_MB_CAS_L
74
MEM_MB_RAS_L
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
MEM_MB0_ODT0
195
77
52
171
MEM_MB0_CS_L0
193
MEM_MB0_CS_L1
76
MEM_MB0_CLK_H0
185
MEM_MB0_CLK_L0
186
MEM_MB0_CLK_H1
137
MEM_MB0_CLK_L1
138
MEM_MB0_CLK_H2
220
MEM_MB0_CLK_L2
221
SMB_MEM_CLK
120
SCL
SMB_MEM_DATA
119
SDA
1
X1
X1
239
SA0
240
SA1
101
SA2
X2
X2
X3
X3
DDRII-240_GREEN-RH
DDRII-240_GREEN-RH
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_CKE0
MEM_MB_CKE0
VDDR_VREF
VCC3
MEM_MB_BANK2 7,10,11
MEM_MB_BANK1 7,10,11
MEM_MB_BANK0 7,10,11
MEM_MB_WE_L 7,10,11
MEM_MB_CAS_L 7,10,11
MEM_MB_RAS_L 7,10,11
MEM_MB0_ODT0 7,11
MEM_MB_CKE0 7,11
MEM_MB0_CS_L0 7,11
MEM_MB0_CS_L1 7,11
MEM_MB0_CLK_H0 7,11
MEM_MB0_CLK_L0 7,11
MEM_MB0_CLK_H1 7,11
MEM_MB0_CLK_L1 7,11
MEM_MB0_CLK_H2 7,11
MEM_MB0_CLK_L2 7,11
VDDR_VREF
C55
C55
C1000p50X0402
C1000p50X0402
PLACE CLOSE TO DIMM PIN
ADDRESS A0
A A
5
VCC_DDR
R96
R96
15R1%0805
15R1%0805
R81
R81
15R1%0805
15R1%0805
4
C58
C58
X_C0.1u16Y0402
X_C0.1u16Y0402
VDDR_VREF
C46
C46
C0.1u16Y0402
C0.1u16Y0402
VDDR_VREF
SMB_MEM_CLK10
SMB_MEM_DATA10
3
SMB_MEM_CLK
SMB_MEM_DATA
3VDUAL
Z
Y
D24
D24
X
1PS226_SOT23
1PS226_SOT23
Z
Y
D22
D22
X
1PS226_SOT23
1PS226_SOT23
R228R228
R224R224
MEM_SMB_CLK0 17
MEM_SMB_DATA0 17
2
ADDRESS A2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
FIRST LOGICAL DIMM
FIRST LOGICAL DIMM
FIRST LOGICAL DIMM
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
of
940Thursday, April 24, 2008
940Thursday, April 24, 2008
940Thursday, April 24, 2008
5
4
3
2
1
197
172
VDDQ
VDDQ69VDDQ
VSS
VSS
VSS
160
163
166
VCC3
MEM_MB_DM[7..0]7,9
C246
C246
X_C0.1u16Y0402
X_C0.1u16Y0402
187
184
189
67
178
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
169
198
201
204
207
VDDQ
VSS
210
238
VSS
213
VDDSPD
VSS
VSS
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
228
161
162
167
168
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
SCL
SDA
VREF
X1
SA0
SA1
SA2
X2
X3
VSS
VSS
VSS
VSS
DDRII-240_ORANGE-RH
DDRII-240_ORANGE-RH
231
234
237
MEM_MA_DQS_H0
7
MEM_MA_DQS_L0
6
MEM_MA_DQS_H1
16
MEM_MA_DQS_L1
15
MEM_MA_DQS_H2
28
MEM_MA_DQS_L2
27
MEM_MA_DQS_H3
37
MEM_MA_DQS_L3
36
MEM_MA_DQS_H4
84
MEM_MA_DQS_L4
83
MEM_MA_DQS_H5
93
MEM_MA_DQS_L5
92
MEM_MA_DQS_H6
105
MEM_MA_DQS_L6
104
MEM_MA_DQS_H7
114
MEM_MA_DQS_L7
113
46
45
MEM_MA_ADD0
188
MEM_MA_ADD1
183
MEM_MA_ADD2
63
MEM_MA_ADD3
182
MEM_MA_ADD4
61
MEM_MA_ADD5
60
MEM_MA_ADD6
180
MEM_MA_ADD7
58
MEM_MA_ADD8
179
MEM_MA_ADD9
177
MEM_MA_ADD10
70
MEM_MA_ADD11
57
MEM_MA_ADD12
176
MEM_MA_ADD13
196
MEM_MA_ADD14
174
MEM_MA_ADD15
173
MEM_MA_BANK2
54
190
71
73
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
119
1
X1
239
240
101
X2
X3
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_RAS_L
MEM_MA1_ODT0
MEM_MA_BANK2 7,9,11
MEM_MA_BANK1 7,9,11
MEM_MA_BANK0 7,9,11
MEM_MA_WE_L 7,9,11
MEM_MA_CAS_L 7,9,11
MEM_MA_RAS_L 7,9,11
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_CKE1
MEM_MA1_CS_L0
MEM_MA1_CS_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
SMB_MEM_CLK
SMB_MEM_DATA SMB_MEM_CLK
MEM_MA1_ODT0 7,11
MEM_MA_CKE1 7,11
MEM_MA1_CS_L0 7,11
MEM_MA1_CS_L1 7,11
MEM_MA1_CLK_H0 7,11
MEM_MA1_CLK_L0 7,11
MEM_MA1_CLK_H1 7,11
MEM_MA1_CLK_L1 7,11
MEM_MA1_CLK_H2 7,11
MEM_MA1_CLK_L2 7,11
SMB_MEM_CLK 9
SMB_MEM_DATA 9
VDDR_VREF
VCC3 VCC3
MEM_MB_ADD[15..0]7,9,11
MEM_MB_DATA[63..0]7,9
MEM_MB_DQS_H[7..0]7,9
MEM_MB_DQS_L[7..0]7,9
DIMM4
DIMM4
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
VCC_DDR
102
68
19
55
3
4
9
2
5
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC2
NC1
RC118RC0
VDD51VDD56VDD62VDD72VDD78VDD
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
170
191
194
181
175
75
VDD
VDD
VDD
VDD
VDDQ
VDDQ53VDDQ59VDDQ64VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
139
142
145
148
151
154
157
197
172
187
VDDQ
VDDQ69VDDQ
VSS
VSS
VSS
160
163
166
169
VDDQ
VSS
184
198
VDDQ
VSS
VCC3
189
67
178
VDDQ
VSS
VSS
201
204
207
VDDQ
VSS
210
238
VSS
213
VDDSPD
VSS
VSS
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
225
228
161
162
167
168
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
SCL
SDA
VREF
X1
SA0
SA1
SA2
X2
X3
VSS
VSS
VSS
VSS
DDRII-240_ORANGE-RH
DDRII-240_ORANGE-RH
231
234
237
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
MEM_MB_BANK2
54
MEM_MB_BANK1
190
MEM_MB_BANK0
71
MEM_MB_WE_L
73
MEM_MB_CAS_L
74
MEM_MB_RAS_L
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
119
1
X1
239
240
101
X2
X3
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB1_ODT0
MEM_MB_CKE1
MEM_MB1_CS_L0
MEM_MB1_CS_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
SMB_MEM_DATA
MEM_MB_BANK2 7,9,11
MEM_MB_BANK1 7,9,11
MEM_MB_BANK0 7,9,11
MEM_MB_WE_L 7,9,11
MEM_MB_CAS_L 7,9,11
MEM_MB_RAS_L 7,9,11
MEM_MB1_ODT0 7,11
MEM_MB_CKE1 7,11
MEM_MB1_CS_L0 7,11
MEM_MB1_CS_L1 7,11
MEM_MB1_CLK_H0 7,11
MEM_MB1_CLK_L0 7,11
MEM_MB1_CLK_H1 7,11
MEM_MB1_CLK_L1 7,11
MEM_MB1_CLK_H2 7,11
MEM_MB1_CLK_L2 7,11
C49
C49
X_C0.1u16Y0402
X_C0.1u16Y0402
VDDR_VREF
MEM_MA_DM[7..0]7,9
MEM_MA_ADD[15..0]7,9,11
MEM_MA_DQS_H[7..0]7,9
MEM_MA_DQS_L[7..0]7,9
MEM_MA_DATA[63..0]7,9
D D
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
C C
B B
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
DIMM3
DIMM3
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
VCC_DDR
102
68
19
55
3
4
9
2
5
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC2
NC1
RC118RC0
VDD51VDD56VDD62VDD72VDD78VDD
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
124
170
191
194
181
175
75
VDD
VDD
VDD
VDD
VDDQ
VDDQ53VDDQ59VDDQ64VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
127
130
133
136
139
142
145
148
151
154
157
ADDRESS A4
A A
5
4
3
ADDRESS A6
2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
SECOND LOGICAL DIMM
SECOND LOGICAL DIMM
SECOND LOGICAL DIMM
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
of
10 40Thursday, April 24, 2008
10 40Thursday, April 24, 2008
10 40Thursday, April 24, 2008
5
4
3
2
1
MEM_MA0_CLK_H27,9
D D
C C
MEM_MB_ADD157,9,10
MEM_MB_ADD147,9,10
MEM_MA_ADD157,9,10
MEM_MA_ADD147,9,10
MEM_MB_ADD117,9,10
MEM_MB_ADD77,9,10
MEM_MB_ADD87,9,10
MEM_MB_ADD67,9,10
MEM_MA_ADD57,9,10
MEM_MB_ADD37,9,10
MEM_MB_ADD17,9,10
MEM_MB_ADD27,9,10
B B
A A
MEM_MB_BANK17,9,10
MEM_MA_BANK07,9,10
MEM_MA_RAS_L7,9,10
MEM_MA0_CS_L07,9
MEM_MA_WE_L7,9,10
MEM_MA_CAS_L7,9,10
MEM_MA0_ODT07,9
MEM_MB_BANK27,9,10
MEM_MB_ADD127,9,10
MEM_MA_BANK27,9,10
MEM_MA_ADD127,9,10
MEM_MA1_ODT07,10
MEM_MB_ADD137,9,10
MEM_MB0_CS_L17,9
RTT:Place Behind DIMMs
MEM_MA_ADD97,9,10
MEM_MA_ADD117,9,10
MEM_MB_ADD97,9,10
MEM_MA_ADD77,9,10
MEM_MA_ADD07,9,10
MEM_MA_BANK17,9,10
MEM_MB_ADD07,9,10
MEM_MA_ADD107,9,10
MEM_MA_ADD87,9,10
MEM_MB_ADD57,9,10
MEM_MA_ADD67,9,10
MEM_MB_ADD47,9,10
MEM_MA_ADD47,9,10
MEM_MA_ADD37,9,10
MEM_MA_ADD17,9,10
MEM_MA_ADD27,9,10
MEM_MB1_CS_L07,10
MEM_MB0_CS_L07,9
MEM_MB_WE_L7,9,10
MEM_MB_CAS_L7,9,10
MEM_MA_CKE17,10
MEM_MA_CKE07,9
MEM_MB_CKE17,10
MEM_MB_CKE07,9
MEM_MB1_CS_L17,10
MEM_MA_ADD137,9,10
MEM_MA1_CS_L17,10
MEM_MA0_CS_L17,9
MEM_MB_ADD107,9,10
MEM_MB_BANK07,9,10
MEM_MB_RAS_L7,9,10
MEM_MA1_CS_L07,10
MEM_MB1_ODT07,10
MEM_MB0_ODT07,9
MEM_MA_ADD9
MEM_MA_ADD11
MEM_MB_ADD9
MEM_MA_ADD7
MEM_MA_ADD0
MEM_MA_BANK1
MEM_MB_ADD0
MEM_MA_ADD10
MEM_MA_ADD8
MEM_MB_ADD5
MEM_MA_ADD6
MEM_MB_ADD4
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MB1_CS_L0
MEM_MB0_CS_L0
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB1_CS_L1
MEM_MA_ADD13
MEM_MA1_CS_L1
MEM_MA0_CS_L1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_RAS_L
MEM_MA1_CS_L0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD6
MEM_MA_ADD5
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_BANK1
MEM_MA_BANK0
MEM_MA_RAS_L
MEM_MA0_CS_L0
MEM_MA_WE_L
MEM_MB1_ODT0
MEM_MA_CAS_L
MEM_MA0_ODT0
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MA_BANK2
MEM_MA_ADD12
MEM_MA1_ODT0
MEM_MB0_ODT0
MEM_MB_ADD13
MEM_MB0_CS_L1
5
RN11 8P4R-47R0402RN11 8P4R-47R0402
1
3
5
7
RN16 8P4R-47R0402RN16 8P4R-47R0402
1
3
5
7
RN13 8P4R-47R0402RN13 8P4R-47R0402
1
3
5
7
RN15 8P4R-47R0402RN15 8P4R-47R0402
1
3
5
7
RN19 8P4R-47R0402RN19 8P4R-47R0402
1
3
5
7
RN8 8P4R-47R0402RN8 8P4R-47R0402
1
3
5
7
RN23 8P4R-47R0402RN23 8P4R-47R0402
1
3
5
7
RN18 8P4R-47R0402RN18 8P4R-47R0402
1
3
5
7
RN9 8P4R-47R0402RN9 8P4R-47R0402
1
3
5
7
RN12 8P4R-47R0402RN12 8P4R-47R0402
1
3
5
7
RN14 8P4R-47R0402RN14 8P4R-47R0402
1
3
5
7
RN17 8P4R-47R0402RN17 8P4R-47R0402
1
3
5
7
RN20 8P4R-47R0402RN20 8P4R-47R0402
1
3
5
7
RN10 8P4R-47R0402RN10 8P4R-47R0402
1
3
5
7
RN22 8P4R-47R0402RN22 8P4R-47R0402
1
3
5
7
VTT_DDR
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
VTT_DDR
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
MEM_MA0_CLK_L27,9
MEM_MA0_CLK_H17,9
MEM_MA0_CLK_L17,9
MEM_MA0_CLK_H07,9
MEM_MA0_CLK_L07,9
MEM_MB0_CLK_H27,9
MEM_MB0_CLK_L27,9
MEM_MB0_CLK_H17,9
MEM_MB0_CLK_L17,9
MEM_MB0_CLK_H07,9
MEM_MB0_CLK_L07,9
MEM_MA1_CLK_H27,10
MEM_MA1_CLK_L27,10
MEM_MA1_CLK_H17,10
MEM_MA1_CLK_L17,10
MEM_MA1_CLK_H07,10
MEM_MA1_CLK_L07,10
MEM_MB1_CLK_H27,10
MEM_MB1_CLK_L27,10
MEM_MB1_CLK_H17,10
MEM_MB1_CLK_L17,10
MEM_MB1_CLK_H07,10
MEM_MB1_CLK_L07,10
4
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
C223
C223
C1.5p50N0402
C1.5p50N0402
C92
C92
C1.5p50N0402
C1.5p50N0402
C181
C181
C1.5p50N0402
C1.5p50N0402
C217
C217
C1.5p50N0402
C1.5p50N0402
C80
C80
C1.5p50N0402
C1.5p50N0402
C178
C178
C1.5p50N0402
C1.5p50N0402
C213
C213
C1.5p50N0402
C1.5p50N0402
C84
C84
C1.5p50N0402
C1.5p50N0402
C186
C186
C1.5p50N0402
C1.5p50N0402
C222
C222
C1.5p50N0402
C1.5p50N0402
C78
C78
C1.5p50N0402
C1.5p50N0402
C182
C182
C1.5p50N0402
C1.5p50N0402
Place Between Processor and DIMMs
VCC_DDRVCC_DDR
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C571 C22p50N0402C571 C22p50N0402
C570 C22p50N0402C570 C22p50N0402
C610 C22p50N0402C610 C22p50N0402
C573 C22p50N0402C573 C22p50N0402
C577 C22p50N0402C577 C22p50N0402
C604 C22p50N0402C604 C22p50N0402 C189 C22p50N0402C189 C22p50N0402
C578 C22p50N0402C578 C22p50N0402
C583 C22p50N0402C583 C22p50N0402
C582 C22p50N0402C582 C22p50N0402
C586 C22p50N0402C586 C22p50N0402
C585 C22p50N0402C585 C22p50N0402
C590 C22p50N0402C590 C22p50N0402
C589 C22p50N0402C589 C22p50N0402
C594 C22p50N0402C594 C22p50N0402
C595 C22p50N0402C595 C22p50N0402
C602 C22p50N0402C602 C22p50N0402
C608 C22p50N0402C608 C22p50N0402
C609 C22p50N0402C609 C22p50N0402
C605 C22p50N0402C605 C22p50N0402
C574 C22p50N0402C574 C22p50N0402
C603 C22p50N0402C603 C22p50N0402
C606 C22p50N0402C606 C22p50N0402
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
C144 C22p50N0402C144 C22p50N0402
C145 C22p50N0402C145 C22p50N0402
C203 C22p50N0402C203 C22p50N0402
C149 C22p50N0402C149 C22p50N0402
C155 C22p50N0402C155 C22p50N0402
C154 C22p50N0402C154 C22p50N0402
C158 C22p50N0402C158 C22p50N0402
C157 C22p50N0402C157 C22p50N0402
C163 C22p50N0402C163 C22p50N0402
C164 C22p50N0402C164 C22p50N0402
C167 C22p50N0402C167 C22p50N0402
C168 C22p50N0402C168 C22p50N0402
C173 C22p50N0402C173 C22p50N0402
C174 C22p50N0402C174 C22p50N0402
C188 C22p50N0402C188 C22p50N0402
C198 C22p50N0402C198 C22p50N0402
C199 C22p50N0402C199 C22p50N0402
C194 C22p50N0402C194 C22p50N0402
C150 C22p50N0402C150 C22p50N0402
C190 C22p50N0402C190 C22p50N0402
C195 C22p50N0402C195 C22p50N0402
Layout: Spread out on VTT pour
VTT_DDR
C179
C239
C239
VTT_DDR
VCC_DDR
C124
C124
C241
C241
C0.1u16Y0402
C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C128
C128
C148
C148
C0.1u16Y0402
C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C207
C207
C0.1u16Y0402
C0.1u16Y0402
C1000p50X0402
C1000p50X0402
C228
C228
C235
C235
X_C0.1u16Y0402
X_C0.1u16Y0402
C105
C105
X_C0.1u16Y0402
X_C0.1u16Y0402
C206
C206
C204
C204
X_C0.1u16Y0402
X_C0.1u16Y0402
C141
C141
C0.1u16Y0402
C0.1u16Y0402
C0.1u16Y0402
C0.1u16Y0402
C193
C193
C151
C151
C0.1u16Y0402
C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C197
C197
C0.1u16Y0402
C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C202
C202
C104
C104
C0.1u16Y0402
C0.1u16Y0402
C183
C183
C187
C187
X_C0.1u16Y0402
X_C0.1u16Y0402
C205
C205
C129
C129
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C179
C0.1u16Y0402
C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C108
C108
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C126
C126
C1000p50X0402
C1000p50X0402
C143
C143
X_C0.1u16Y0402
X_C0.1u16Y0402
VCC_DDR
C130
C130
X_C0.1u16Y0402
X_C0.1u16Y0402
C153
C153
X_C0.1u16Y0402
X_C0.1u16Y0402
C180
C180
C127
C127
X_C0.1u16Y0402
X_C0.1u16Y0402
C152
C152
C211
C211
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
VCC_DDR
C101
C101
X_C0.1u16Y0402
X_C0.1u16Y0402
C159
C159
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C208
C208
X_C0.1u16Y0402
X_C0.1u16Y0402
C135
C135
C0.1u16Y0402
C0.1u16Y0402
C323
C323
C191
C191
X_C0.1u16Y0402
X_C0.1u16Y0402
C201
C201
C106
C106
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C185
C185
X_C0.1u16Y0402
X_C0.1u16Y0402
C177
C177
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
X_C0.1u16Y0402
C224
C224
X_C0.1u16Y0402
X_C0.1u16Y0402
C147
C147
X_C0.1u16Y0402
X_C0.1u16Y0402
for EMI
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
3
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
DDR TERMINATOR
DDR TERMINATOR
DDR TERMINATOR
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
of
11 40Monday, April 28, 2008
11 40Monday, April 28, 2008
11 40Monday, April 28, 2008
5
4
3
2
1
R153
R153
300R0402
300R0402
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
R152
R152
300R0402
300R0402
NB_CORE_1.1V
NB_CORE_1.1V
1.1V_PLL_CPU_HT
L17
L17
10n300mA_0402-RH
10n300mA_0402-RH
L18
L18
10n300mA_0402-RH
10n300mA_0402-RH
HT_CLKOUT_H06
HT_CLKOUT_L06
HT_CLKOUT_H16
HT_CLKOUT_L16
HT_CTLOUT_H06
HT_CTLOUT_L06
HT_CTLOUT_H16
HT_CTLOUT_L16
R446 150R1%0402R446 150R1%0402
R174 150R1%0402R174 150R1%0402
C620
C620
C4.7u6.3X5
C4.7u6.3X5
C624
C624
C4.7u6.3X5
C4.7u6.3X5
HT_CADOUT_H0
HT_CADOUT_H1
HT_CADOUT_H2
HT_CADOUT_H3
HT_CADOUT_H4
HT_CADOUT_H5
HT_CADOUT_H6
HT_CADOUT_H7
HT_CADOUT_H8
HT_CADOUT_H9
HT_CADOUT_H10
HT_CADOUT_H11
HT_CADOUT_H12
HT_CADOUT_H13
HT_CADOUT_H14
HT_CADOUT_H15
HT_CADOUT_L0
HT_CADOUT_L1
HT_CADOUT_L2
HT_CADOUT_L3
HT_CADOUT_L4
HT_CADOUT_L5
HT_CADOUT_L6
HT_CADOUT_L7
HT_CADOUT_L8
HT_CADOUT_L9
HT_CADOUT_L10
HT_CADOUT_L11
HT_CADOUT_L12
HT_CADOUT_L13
HT_CADOUT_L14
HT_CADOUT_L15
Layout : Within 0.6 inch
HT_MCP_COMP_VDD
HT_MCP_COMP_GND
CPU_PROCHOT#
CPU_THRIP#
1.1V_PLL_CPU_HT
150 mA
C622
C622
C2.2u6.3X0402
C2.2u6.3X0402
+1.1V_PLL_CPU
77 mA
C623
C623
C2.2u6.3X0402
C2.2u6.3X0402
AG8
HT_MCP_RXD0_P
AG9
HT_MCP_RXD1_P
AK9
HT_MCP_RXD2_P
AJ10
HT_MCP_RXD3_P
AG12
HT_MCP_RXD4_P
AG13
HT_MCP_RXD5_P
AK13
HT_MCP_RXD6_P
AJ14
HT_MCP_RXD7_P
AB10
HT_MCP_RXD8_P
AD10
HT_MCP_RXD9_P
AF10
HT_MCP_RXD10_P
AC12
HT_MCP_RXD11_P
AB11
HT_MCP_RXD12_P
AB13
HT_MCP_RXD13_P
AF14
HT_MCP_RXD14_P
AE14
HT_MCP_RXD15_P
AH8
HT_MCP_RXD0_N
AH9
HT_MCP_RXD1_N
AJ9
HT_MCP_RXD2_N
AH10
HT_MCP_RXD3_N
AH12
HT_MCP_RXD4_N
AH13
HT_MCP_RXD5_N
AJ13
HT_MCP_RXD6_N
AH14
HT_MCP_RXD7_N
AC10
HT_MCP_RXD8_N
AE10
HT_MCP_RXD9_N
AG10
HT_MCP_RXD10_N
AD12
HT_MCP_RXD11_N
AC11
HT_MCP_RXD12_N
AB12
HT_MCP_RXD13_N
AG14
HT_MCP_RXD14_N
AD14
HT_MCP_RXD15_N
AJ11
HT_MCP_RX_CLK0_P
AH11
HT_MCP_RX_CLK0_N
AE12
HT_MCP_RX_CLK1_P
AF12
HT_MCP_RX_CLK1_N
AJ15
HT_MCP_RXCTL0_P
AH15
HT_MCP_RXCTL0_N
AB14
RESERVED35
AC14
RESERVED36
AB9
HT_MCP_COMP_VDD
AB8
HT_MCP_COMP_GND
AD8
PROCHOT/GPIO20#
AE8
THERMTRIP/GPIO58#
AC15
+1.1V_PLL_CPU_HT
AB15
+1.1V_PLL_CPU
+1.1V_PLL_CPU
U21A
U21A
SEC 1 OF 8
SEC 1 OF 8
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N
RESERVED33
RESERVED34
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_RST#
HT_MCP_PWRGD
CLKOUT_200MHZ_P
CLKOUT_200MHZ_N
CPU_SBVREF
CLKOUT_25MHZ
CLK200_TERM_GND
AH23
AH22
AJ21
AH21
AH19
AH18
AJ17
AH17
AF22
AB20
AC20
AE20
AD18
AF18
AB17
AC16
AJ23
AJ22
AK21
AG21
AJ19
AJ18
AK17
AG17
AG22
AB19
AD20
AF20
AE18
AG18
AB16
AD16
AH20
AG20
AC18
AB18
AH16
AG16
AE16
AF16
HT_MCP_REQ#
AH25
AH24
AG23
AG24
AK25
AJ25
AF24
AK26
CLK200_TERM_GND
AJ26
Layout : Place R201
within 1.0 inch of MCP
HT_CADIN_H0
HT_CADIN_H1
HT_CADIN_H2
HT_CADIN_H3
HT_CADIN_H4
HT_CADIN_H5
HT_CADIN_H6
HT_CADIN_H7
HT_CADIN_H8
HT_CADIN_H9
HT_CADIN_H10
HT_CADIN_H11
HT_CADIN_H12
HT_CADIN_H13
HT_CADIN_H14
HT_CADIN_H15
HT_CADIN_L0
HT_CADIN_L1
HT_CADIN_L2
HT_CADIN_L3
HT_CADIN_L4
HT_CADIN_L5
HT_CADIN_L6
HT_CADIN_L7
HT_CADIN_L8
HT_CADIN_L9
HT_CADIN_L10
HT_CADIN_L11
HT_CADIN_L12
HT_CADIN_L13
HT_CADIN_L14
HT_CADIN_L15
Layout : Place C301
within 0.5 inch of MCP
HT_CLKIN_H0 6
HT_CLKIN_L0 6
HT_CLKIN_H1 6
HT_CLKIN_L1 6
HT_CTLIN_H0 6
HT_CTLIN_L0 6
HT_CTLIN_H1 6
HT_CTLIN_L1 6
R194 10KR0402R194 10KR0402
LDT_STOP# 6
LDT_RST# 6
LDT_PWRGD 6,31,32
CPU_CLK 6
CPU_CLK# 6
R201 2.37KR1%0402R201 2.37KR1%0402
VCC3
NB_CORE_1.1V
C301
C301
C0.1u16X0402-2
C0.1u16X0402-2
HT_CADIN_H[15..0]6
HT_CADIN_L[15..0]6
HT_CADOUT_H[15..0]6
D D
C C
B B
HT_CADOUT_L[15..0]6
VCC_DDR
CPU_PROCHOT#6
CPU_THRIP#6
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MCP HT I/F
MCP HT I/F
MCP HT I/F
MS-7511 1.2
MS-7511 1.2
MS-7511 1.2
1
of
12 40Thursday, April 24, 2008
12 40Thursday, April 24, 2008
12 40Thursday, April 24, 2008
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