MSI MS-7509 Schematic 1105A
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MS-7509
uATX(244mm X 200mm)
D D
CPU:
AMD AM2+ / AM3 Socket940
System Chipset:
North Bridge --South Bridge --- NA
OnBoard Chipset:
Clock Gen:NA
AC'97 Codec:ALC888
C C
LAN Chip: REL8211BL/8201CL
SIO:Fintek 882(with smart fan control-3/4 pin co-lay)
Flash ROM:8MB SPI (SIO)
MCP78V
VER 20
Cover Sheet 1
Block Diagram 2
Device Map
GPIO Table 4
Clock Distribution
CPU:AM2+
DDR2 DIMM(Dual Channel)
MCP78
LAN_ RTL8211BL/8201CL
PCIE x 16 , x1 Slots.
DVI
PCI Slot1 / 2
VGA connect
FAN
USB Conn.
Main Memory:
DDRII* 2 (Dual Channel)
Expansion Slots:
PCI Express (X16) Slot * 1
B B
PCI Express (X1) Slot * 1
PCI Slot * 2
Azalia Codec
SIO-F71882FG / TPM
KB/MS&COM1&LPT&Floppy Conn.
ACPI Power Controler-UPI
UPI 6103 System Regulators
VRM-ISL6566
PWM:
Controller:ISL6566
ACPI:
UPI solution
Front Panel 33
For EMI
BOM - Option Parts
Power Delivery
Other:
FDD *1
SATA(SATA2-300MB/s) * 6(included 1 ESATA)
A A
USB2.0 *12 (Rear*6 Front*6)
History
PageTitle
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5
6,7,8,9
10,11,12
13 ~ 19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37Power Sequence
38
COM PORT *1
LPT PORT *1
DVI*1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
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Date: Sheet
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Cover Sheet
Cover Sheet
Cover Sheet
MS-7059 20
MS-7059 20
MS-7059 20
1
138Wednesday, November 05, 2008
138Wednesday, November 05, 2008
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AMD
VRM-ISL6323CR
3-Phase PWM +1-NB
D D
PCIE X16
PCIE X1
JPM381
PCIE X16
PCIE X1
PCIE X1
AM2+_940 / AM3
HyperTransport LINK0
1G
nVIDIA
LINK0
16x16
DDR400/533/667/800
DDRII
DDR400/533/667/800
VGA
DVI
UNBUFFERED DDR
CHANNEL_A DIMM2
240-PIN DDRII
UNBUFFERED DDR
CHANNEL_B DIMM1
240-PIN DDRII
VGA CON.
DVI
MCP78
C C
Rear port x 6
Front port x 6
Giga LAN or10/100 LAN
USB2.0
AC LINK
SATA-II Link
Azalia CODEC
ALC888(8CH)
SATA-II Port #1~2
#3~4#5~6(included 1 ESATA)
PCI BUS
B B
A A
5
PCI SLOT x2
Fintek 882
KB &
FLOPPY
LPT
*1 *1 *1 *1
MOUSE
4
SERIAL
PORTS
FAN
CONTROL
LPC
TPM Pin
Header
3
SPI SPI
Header
SPI FLASH ROMSPI Pin
8M
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
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DDR DIMM Config.
DEVICE
DIMM 2
CH-A
D D
DIMM 1
CH-B
USB
C C
Rear
Front
B B
10100000B
10100001B
Port DATA +/-
ESATA_USB1A
I1394_USB1
LAN_USB1A
JUSB4
JUSB2
JUSB5
CLOCKADDRESS
MEM_MA0_CLK_H0/L0
MEM_MA0_CLK_H1/L1 PCI Slot 2
MEM_MA0_CLK_H2/L2
MEM_MB0_CLK_H0/L0
MEM_MB0_CLK_H1/L1
MEM_MB0_CLK_H2/L2
OC#
USB0USB0+
USB1USB1+
USB2USB2+
USB3USB3+
USB10USB10+
USB11USB11+
USB4USB4+
USB5USB5+
USB6USB6+
USB7USB7+
USB8USB8+
USB9USB9+
PCI Config.
DEVICE MCP1 INT Pin
PCI_INT#X
PCI_INT#Y
PCI_INT#Z
PCI_INT#W
PCI_INT#W
PCI Slot 1
PCI_INT#X
PCI_INT#Y
PCI_INT#Z
IEEE1394
TPM
Chipset
LPC
SIO
PCI RESET DEVICE
MCP78
Signals
PCI_RESET0*
PCI_RESET1*
PCI_RESET2* HD_RST#
PCI_RESET3*
LPC_RESET*
Target
PCIRST_SLOT1#
PCIRST_SLOT2#
JTPM_RST#
SIO_RST#
REQ#/GNT#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
IDSEL
AD25
AD24
CLOCK
PCICLK2
(PCI_CLK2)
PCICLK1
(PCI_CLK1)
PCIE2_CLK
/PCIE2_CLK#
LPCPCLK
(LPC_CLK1)
PCI_CLKIN
(PCICLK4)
LPC_PCLK
SIOPCLK
(LPC_CLK0)
CPU VID TABLE
VID
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000 1.1500V
10001
10010
10011 1.0750V
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
VOLTAGE
1.5500V
1.5250V
1.5000V
1.4750V
1.4500V
1.4250V
1.4000V
1.3750V
1.3500V
1.3250V
1.3000V
1.2750V
1.2500V
1.2250V
1.2000V
1.1750V
1.1250V
1.1000V
1.0500V
1.0250V
1.0000V
0.9750V
0.9500V
0.9250V
0.9000V
0.8750V
0.8500V
0.8250V
0.8000V
0.7750V
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Device Map
Device Map
Device Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
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Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
338Wednesday, November 05, 2008
338Wednesday, November 05, 2008
338Wednesday, November 05, 2008
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MCP78 GPIO TABLE
D D
C C
B B
PIN NAME
THERMTRIP*/GPIO58
PROCHOT*/GPIO20
MII_RXER/GPIO36
MII_COL/GPIO13/MI2C_DATA
MII_CRS/GPIO14/MI2C_CLK
RGMII/MII_INTR*/GPIO35
RGMII/MII_PWRDWN*/GPIO37
MII_RESET*/GPIO12
DDC_CLK/GPIO17
DDC_DATA/GPIO19
PCI_REQ2*/GPIO40.RS232_DSR*
PCI_REQ3*/GPIO38/RS232_CTS*
PCI_GNT2*/GPIO41/RS232_DTR*
PCI_GNT3*/GPIO39/RS232_RTS*
PCI_PERR*/GPIO43/RS232_DCD*
PCI_PME*/GPIO30
LPC_PWRDWN*/GPIO54/EXT_NMI*
LPC_DRQ0*/GPIO50
LPC_DRQ1*/GPIO15/FANRPM1
CABLE_DET_P/GPIO63
SATE_LED*/GPIO57
HDA_SDATA_OUT0/GPIO45
HDA_SDATA_IN0/GPIO22
HDA_SDATA_IN1/GPIO23/MGPIO0
HDA_SYNC/GPIO44
GPIO_1
GPIO_2/NMI*/PS2_CLK0
GPIO_3/SMI*/PS2_DATA0
GPIO_4/SCI_INTR/PS2_CLK1
GPIO_5/INIT*/PS2_DATA2
GPIO_6/FERR*/SYS_FERR*
GPIO_7/NFERR*/SYS_PERR*
GPIO_8/SPI_DI
GPIO_9/SPI_DO
GPIO_10/SPI_CS
GPIO_11/SPI_CLK
USB_OC0*/GPIO25
USB_OC1*/GPIO26
USB_OC2*/GPIO27
USB_OC3*/GPIO28/MGPIO_1
USB_OC4*/GPIO29
A20GATE/GPIO55
EXT_SMI*/GPIO32
RI*/GPIO33
SIO_PME*/GPIO31
KBRDRSTIN*/GPIO56
SUS_CLK/GPIO34
THERM*/GPIO59
FANRPM0/GPIO60
FANCTL0/GPIO61
FANCTL1/GPIO62
THERM_SIC/GPIO48
THERM_SID0/GPIO49
PE_WAKE*/GPIO21
FUNCTION
CPU_THERMTRIP*
PROCHOT*
MII_RXER
MII_COL
MII_CRS
Pull High 10K to 3VDUAL
-MII_RESET*
DDC_CLK
DDC_DATA
PCI_REQ2* Pull High to 3VDUAL
PCI_REQ3* Pull High to 3VDUAL
PCI_GNT2*
PCI_GNT3*
PCI_PERR*
PCI_PME*
OD_TCK
LPC_DRQ0*
--
CABLE_DET_P
SATE_LED*
HDA_SDATA_OUT
HDA_SDATA_IN0
-HDA_SYNC
--
--
--
-OD_CPU_RST_L
DBREQ_L
OD_TRST_L
--
--
--
-Pull High 10K to 3VDUAL(USB not USE)
Pull High 10K to 3VDUAL(USB not USE)
Pull High 10K to 3VDUAL(USB not USE)
Pull High 10K to 3VDUAL(USB not USE)
Pull High 10K to 3VDUAL(USB not USE)
A20GATE
EXT_SMI*
G3 TO S5 POEWR CONTROL
SIO_PME*
SIO_KBRST*
-DO_DBRDY#
THERM*
-OD_TDO#
Internal 10K pull-up to vcc3
-PE_WAKE*
SIO GPIO TABLE
GROUP
UART & SIR
Hardware Monitor
ACPI Function Pins
VID Controller
GPIO10/SPISLK/FININ4
GPIO11/SPI_CS0#/FAN_CTL4
FPIO12/SPI_MISO/FANCTL1_1
GPIO13/SPI_MOSI/BEEP
GPIO14/FWH_DIS/WDTRST#/SPI_CS1#
PIN NAME
IRTX/GPIO42
IRRX/GPIO43
GPIO17
FANIN3/GPIO40
FAN_CTL3/GPIO41
PME#/GPIO25
GPIO15/LED_VSB/ALERT#
GPIO16/LED_VCC/Turbo2#
PCIRST1#/GPIO20
PCIRST2#/GPIO21
PCIRST3#/GPIO22
GPIO23/RSTCON#
ATXPG_IN/GPIO24
PWROK/GPIO32
PWSIN#/GPIO26
PWSOUT#/GPIO27
S3#/GPIO30
PSON#/GPIO31
RSMRST#/GPIO33
VIDOUT0/GPIO0
VIDOUT1/GPIO1
VIDOUT2/GPIO2
VIDOUT3/GPIO3
VIDOUT4/GPIO4
VIDOUT5/GPIO5/SIC
SLOTOCC#/GPIO6
GPIO7/Turbo1#/WDTRST#
FUNCTION
-PCI_PERR*
DDC_CLK
DDC_CLK
PCI_GNT2*
PME#
SPI_SLK
SPI_CS0#
MII_RESET*
MII_COL
MII_CRS
SUS_LED
PWR_LED
PROCHOT*
PE_WAKE*
HDA_SDATA_IN0
--
ATXPG_IN
--
PWSIN#
PWSOUT#
S3#
PSON#
--
VIDOUT0
VIDOUT1
VIDOUT2
VIDOUT3
VIDOUT4
SIC
SLOTOCC#
--
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
GPIO Table
GPIO Table
GPIO Table
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
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Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
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438Wednesday, November 05, 2008
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AMD
AM2+/AM2
MEMORY_A0_CLK[2:0]
MEMORY_A0_CLK[2:0]#
3 PAIR MEM CLK
DIMM1-CHADIMM2-CHB
HT_CPU_RXCLK[1:0]#
D D
HT_CPU_RXCLK[1:0]
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
CPUCLK_IN
CPUCLK_IN#
MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]#
3 PAIR MEM CLK
Dual Chanel
NVIDIA
CLKOUT_200MHZ
CLKOUT_200MHZ#
C C
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
HT_CPU_RXCLK[1:0]
HT_CPU_RXCLK[1:0]#
MCP78
PE0_REFCLK
PE0_REFCLK#
PE1_REFCLK
PE1_REFCLK#
BUF_SIO
LPC_CLK0
24MHZ
SIO_PCLK
PEX_X16
PEX_X1
SIO
SPI_CLK
PCICLK
SPI_CLK
SPI ROM
#1
PCI_CLK0
PCI_CLK1
B B
32.768 KHZ
A A
25 MHZ
5
RTC_XTAL
XTAL_IN
XTAL_OUT
4
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN
LPC_CLK1
HDA_BITCLK
MII_TXCLK
MII_RXCLK
BUF_25MHZ
PCICLK_SLOT1
PCICLK_SLOT2
PCICLK_TPM
LPC_PCLK
HDA_BITCLK
MII_TXCLK
BUF_25MHZ
3
MII_RXCLK
PCI_SLOT1
PCI_SLOT2
LPC
HEADER
HDA
CODEC
HDA_BITCLK
LAN
PHY
MII_TXCLK
MII_RXCLK
BUF_25MHZ
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
538Wednesday, November 05, 2008
538Wednesday, November 05, 2008
538Wednesday, November 05, 2008
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VCC_DDR
D D
CLKIP1[13]
CLKIN1[13]
CLKIP0[13]
CLKIN0[13]
CTLIP1[13]
CTLIN1[13]
CTLIP0[13]
CTLIN0[13]
HT_D_4/6/13
C C
CADIP[0..15][13]
CADIN[0..15][13]
CADOP[0..15][13]
CADON[0..15][13]
CTLIP1
CTLIN1
CADIP15
CADIN15
CADIP14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CADIP[0..15]
CADIN[0..15]
CADOP[0..15]
CADON[0..15]
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
CPU1A
CPU1A
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_H(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
L0_CLKOUT_L(1)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
Designer need to ensure this project support
which model processer .
If support AM2r2/AM3 and Please change resistor
value to 1KΩ (±5%).
AD5
AD4
AD1
AC1
CTLOP1
Y6
CTLON1
W6
W2
W3
CADOP15
Y5
CADON15
Y4
CADOP14
AB6
CADON14CADIN14
AA6
CADOP13
AB5
CADON13
AB4
CADOP12
AD6
CADON12
AC6
CADOP11
AF6
CADON11
AE6
CADOP10
AF5
CADON10
AF4
CADOP9
AH6
CADON9
AG6
CADOP8
AH5
CADON8
AH4
CADOP7
Y1
CADON7
W1
CADOP6
AA2
CADON6
AA3
CADOP5
AB1
CADON5
AA1
CADOP4
AC2
CADON4
AC3
CADOP3
AE2
CADON3
AE3
CADOP2
AF1
CADON2
AE1
CADOP1
AG2
CADON1
AG3
CADOP0
AH1
CADON0
AG1
N12-9400050-F02
NV VCC Function
VCC3
B B
A A
OD_CPU_RST_L[18]
OD_DBREQ_L
OD_DBREQ_L[18]
OD_DBRDY[18]
OD_TCK
OD_TCK[16]
OD_TMS CPU_TMS
OD_TMS[16]
OD_TDI[16]
OD_TRST_L
OD_TRST_L[18]
OD_TDO
OD_TDO[18]
OD_CPU_RST_L
R465 1KR0402R465 1KR0402
R468 1KR0402R468 1KR0402
R471 1KR0402R471 1KR0402
R474 1KR0402R474 1KR0402
R477 1KR0402R477 1KR0402
R480 1KR0402R480 1KR0402
R483 1KR0402R483 1KR0402
R486 1KR0402R486 1KR0402
5
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
Q59
Q59
Q61
Q61
Q62
Q62
Q63
Q63
Q64
Q64
Q66
Q66
C E
C E
B
CE
B
Q60
Q60
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
B
CE
B
CE
B
CE
B
CE
B
Q65
Q65
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
B
CE
RN4
RN4
1
3
5
7
8P4R-300R-RH
8P4R-300R-RH
R464 1KR0402R464 1KR0402
R466 220RR466 220R
R467 1KR0402R467 1KR0402
R469 220RR469 220R
R470 1KR0402R470 1KR0402
R472 220RR472 220R
R473 1KR0402R473 1KR0402
R475 220RR475 220R
R476 1KR0402R476 1KR0402
R478 220RR478 220R
R479 1KR0402R479 1KR0402
R481 220RR481 220R
R482 1KR0402R482 1KR0402
R484 220RR484 220R
R485 1KR0402R485 1KR0402
R487 220RR487 220R
4
2
4
6
8
CLKOP1 [13]
CLKON1 [13]
CLKOP0 [13]
CLKON0 [13]
CTLOP1 [13]
CTLON1 [13]
CTLOP0 [13]
CTLON0 [13]
4
CPU_THRIP#
LDT_RST#
CPU_GD
LDTSTOP#
HT_D_4/6/12
VCC_DDR
CPU_DBREQ_L
CPU_DBRDYOD_DBRDY
CPU_TCK
CPU_TDIOD_TDI
CPU_TRST_L
CPU_TDO
LDT_RST#
CPUCLKO_H[13]
Layout : Place R63
within 0.5 inch of CPU
CPUCLKO_L[13]
If SI is not used,the SID
pin can be left unconnector
and SIC should have a 300
ohm pulldown to VSS
C71 C3900p50XC71 C3900p50X
C73 C3900p50XC73 C3900p50X
VCC_DDR
HT_MEM_REF_N_4/12/12
VCC_DDR
R49
R49
15R1%0805
15R1%0805
15 mils
CPU_M_VREF
C66
C66
R62
R62
C0.1u16Y0402
C0.1u16Y0402
15R1%0805
15R1%0805
LDT_RST# [13]
R123
R123
1KR0402
1KR0402
R126
R126
39.2R1%0402
39.2R1%0402
R129
R129
39.2R1%0402
39.2R1%0402
C64
C64
C0.1U25Y
C0.1U25Y
VCC_DDR
C62
C62
C1000p50X0402
C1000p50X0402
VCC5
3
C10u10X50805-RH
C10u10X50805-RH
R63
R63
169R1%0402
169R1%0402
CLK-HOST_D_4/6/20
R124
R124
VCC_DDR
1KR0402
1KR0402
R128
R128
X_300R0402
X_300R0402
VCC_DDR
CPU-POWER_D_4/4/12
MEMZN
MEMZP
VCC_DDR
U4
U4
LT1087S_SOT89
LT1087S_SOT89
VIN3VOUT
3
CPU_GD[13,32]
LDTSTOP#[13]
LDT_RST#[13]
COREFB_H[32]
COREFB_L[32]
R66 510R0402R66 510R0402
R65 510R0402R65 510R0402
THERMDC_CPU[28]
THERMDA_CPU[28]
ADJ
1
C52
C52
C51
C51
X_C1u16X
X_C1u16X
R127 1KR0402R127 1KR0402
TP22TP22
TP17TP17
TP14TP14
TP21TP21
R354 300R0402R354 300R0402
TP10TP10
R53 300R0402R53 300R0402
R54 300R0402R54 300R0402
TP8TP8
TP9TP9
TP12TP12
TP7TP7
TP15TP15
2
R48
R48
200R1%0402
200R1%0402
C49
C49
X_C3300p50X0402
X_C3300p50X0402
CPUCLKIN_H
CPUCLKIN_L
CPU_GD
LDTSTOP#
LDT_RST#
CPU_PRESENT_L
THERMAL_SIC
THERMAL_SID
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB_H
COREFB_L
CPU_VTT_SENSE
CPU_M_VREF
CPU_TEST25_H
CPU_TEST25_L
C0.1U16Y0402
C0.1U16Y0402
R47
R47
200R1%0402
200R1%0402
2
CP2
VDDA25
VDDA_25
C10
VDDA1
D10
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
E12
VTT_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AG9
TEST5
AG8
TEST4
AH7
TEST3
AJ6
TEST2
N12-9400050-F02
CP2
VDDA25
X_CP003
X_CP003
L1
L1
X_80L2A-100_0805-RH
X_80L2A-100_0805-RH
CPU1D
CPU1D
MISC
MISC
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
THERMTRIP_L
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
D2
D1
C1
E3
E2
E1
CPU_THRIP#
AK7
PROCHOT#
AL7
CPU_TDOCPU_TDI
AK10
CPU_DBRDY
B6
CPU_VDDIOFB_H
AK11
CPU_VDDIOFB_L
AL11
CPU_PSI_L
F1
HTREF1
V8
HTREF0
V7
R64 80.6R1%0402R64 80.6R1%0402
C11
D11
FBCLKOUT_D_5/4/15
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
R122 300R0402R122 300R0402
AK5
G7
D4
CPUVID5
CPUVID4
CPUVID3
CPUVID2
CPUVID1
CPUVID0
1KR0402
1KR0402
R55
R55
VCC_DDR
VCC_DDR
R83 X_300R0402R83 X_300R0402
R56
R56
1KR0402
1KR0402
CPUVID5 [32]
CPUVID4 [32]
CPUVID3 [32]
CPUVID2 [32]
CPUVID1 [32]
CPUVID0 [32]
CPU_THRIP# [13]
TP20TP20
TP6TP6
CP20CP20
CPU_VDDIOFB_H [31]
TP2TP2
VID_N_4/5/8
16 mil
Layout :
1. Place R64
within 0.5 inch
TP19TP19
TP13TP13
TP18TP18
R191
R191
R125
R125
300R0402
300R0402
300R0402
300R0402
As the SIC and SID are not
recommended to use for the rev. F processors.
for NV Stuff R557 , R559
for SIO Stuff R558 , R560
5/10/10
VDDA_25
C59
C59
C53
C53
C10U10Y0805
C10U10Y0805
Title
Title
Title
CPU-HT & Straps
CPU-HT & Straps
CPU-HT & Straps
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
Date: Sheet
Date: Sheet
2
Date: Sheet
1
THERMAL_SIC[28]
THERMAL_SID[28]
C171
C171
1
PROCHOT# [13]
R130 44.2R1%R130 44.2R1%
R132 44.2R1%R132 44.2R1%
C176
C176
C1000p50X0402
C1000p50X0402
THERMAL_SIC
THERMAL_SID
638Wednesday, November 05, 2008
638Wednesday, November 05, 2008
638Wednesday, November 05, 2008
VCC1_2HT
of
of
of
NEAR CPU
Layout : Place
with in 1 inch
C1000p50X0402
C1000p50X0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
5
MEMORY INTERFACE A
D D
C C
B B
MEM_MA0_CLK_H2[10,12]
MEM_MA0_CLK_L2[10,12]
MEM_MA0_CLK_H1[10,12]
MEM_MA0_CLK_L1[10,12]
MEM_MA0_CLK_H0[10,12]
MEM_MA0_CLK_L0[10,12]
MEM_MA0_CS_L1[10,12]
MEM_MA0_CS_L0[10,12]
MEM_MA0_ODT0[10,12]
MEM_MA_CAS_L[10,12]
MEM_MA_WE_L[10,12]
MEM_MA_RAS_L[10,12]
MEM_MA_BANK2[10,12]
MEM_MA_BANK1[10,12]
MEM_MA_BANK0[10,12]
MEM_MA_CKE0[10,12]
MEM_MA_ADD[15..0][10,12]
MEM_MA_DQS_H7[10]
MEM_MA_DQS_L7[10]
MEM_MA_DQS_H6[10]
MEM_MA_DQS_L6[10]
MEM_MA_DQS_H5[10]
MEM_MA_DQS_L5[10]
MEM_MA_DQS_H4[10]
MEM_MA_DQS_L4[10]
MEM_MA_DQS_H3[10]
MEM_MA_DQS_L3[10]
MEM_MA_DQS_H2[10]
MEM_MA_DQS_L2[10]
MEM_MA_DQS_H1[10]
MEM_MA_DQS_L1[10]
MEM_MA_DQS_H0[10]
MEM_MA_DQS_L0[10]
MEM_MA_DM7[10]
MEM_MA_DM6[10]
MEM_MA_DM5[10]
MEM_MA_DM4[10]
MEM_MA_DM3[10]
MEM_MA_DM2[10]
MEM_MA_DM1[10]
MEM_MA_DM0[10]
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
W27
AD27
AA25
AC27
AB25
AB27
AA26
AA27
M25
M27
AC26
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
G15
AF15
AF19
AJ25
AH29
G19
H19
U27
U26
G20
G21
V27
N25
Y27
L27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
D29
C29
C25
D25
E19
F19
F15
B29
E24
E18
H15
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
CPU1B
CPU1B
4
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
3
MEM_MA_DATA[63..0] [10]
2
CPU1C
CPU1C
MEMORY INTERFACE B
MEM_MB0_CLK_H2[10,12]
MEM_MB0_CLK_L2[10,12]
MEM_MB0_CLK_H1[10,12]
MEM_MB0_CLK_L1[10,12]
MEM_MB0_CLK_H0[10,12]
MEM_MB0_CLK_L0[10,12]
MEM_MB0_CS_L1[10,12]
MEM_MB0_CS_L0[10,12]
MEM_MB0_ODT0[10,12]
MEM_MB_CAS_L[10,12]
MEM_MB_WE_L[10,12]
MEM_MB_RAS_L[10,12]
MEM_MB_BANK2[10,12]
MEM_MB_BANK1[10,12]
MEM_MB_BANK0[10,12]
MEM_MB_CKE0[10,12]
MEM_MB_ADD[15..0][10,12]
MEM_MB_DQS_H7[10]
MEM_MB_DQS_L7[10]
MEM_MB_DQS_H6[10]
MEM_MB_DQS_L6[10]
MEM_MB_DQS_H5[10]
MEM_MB_DQS_L5[10]
MEM_MB_DQS_H4[10]
MEM_MB_DQS_L4[10]
MEM_MB_DQS_H3[10]
MEM_MB_DQS_L3[10]
MEM_MB_DQS_H2[10]
MEM_MB_DQS_L2[10]
MEM_MB_DQS_H1[10]
MEM_MB_DQS_L1[10]
MEM_MB_DQS_H0[10]
MEM_MB_DQS_L0[10]
MEM_MB_DM7[10]
MEM_MB_DM6[10]
MEM_MB_DM5[10]
MEM_MB_DM4[10]
MEM_MB_DM3[10]
MEM_MB_DM2[10]
MEM_MB_DM1[10]
MEM_MB_DM0[10]
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
AE30
AC31
AD29
AL19
AL18
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
AA31
AA28
M31
M29
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
A18
A19
U31
U30
C19
D19
N31
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
1
MEM_MB_DATA[63..0] [10]
N12-9400050-F02 N12-9400050-F02
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CPU-Memory
CPU-Memory
CPU-Memory
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
1
of
of
of
738Wednesday, November 05, 2008
738Wednesday, November 05, 2008
738Wednesday, November 05, 2008
5
4
3
2
1
VCCP
VDD_NB
A4
A6
AA8
AA10
D D
C C
B B
AA12
AA14
AA16
AA18
AB7
AB9
AB11
AC4
AC5
AC8
AC10
AD2
AD3
AD7
AD9
AE10
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
F11
G10
G12
H11
H23
J12
J14
J16
J18
J20
J22
J24
K11
K13
K15
K17
K19
K21
K23
L10
L12
Y17
Y19
B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8
F5
F7
F9
G6
G8
H7
J8
K7
K9
L4
L5
L8
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151
CPU1F
CPU1F
VDD1
VDD1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
N12-9400050-F02
VCCP
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
W10
VDD62
W12
VDD63
W14
VDD64
W16
VDD65
W18
VDD66
W20
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
N12-9400050-F02
CPU1G
CPU1G
VDD2
VDD2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCCP VCC1_2HT
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
5
6
7
8
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
GND
GND
GND
GND
CPU1H
CPU1H
VDD3
VDD3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
VTT_DDR
VCC_DDR
N12-9400050-F02
VDD_NB
VCC1_2HT
CPU1I
CPU1I
VDDIO
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
N12-9400050-F02
CPU1E
CPU1E
INTERNAL MISC E
INTERNAL MISC E
L25
RSVD1
L26
RSVD2
L31
RSVD3
L30
RSVD4
W26
RSVD5
W25
RSVD6
AE27
RSVD7
U24
RSVD8
V24
RSVD9
AE28
RSVD10
Y31
RSVD11
Y30
RSVD12
AG31
RSVD13
V31
RSVD14
W31
RSVD15
AF31
RSVD16
AD18
KEY1
AD19
KEY2
AE7
KEY3
AE8
KEY4
H3
KEY5
H4
KEY6
H20
KEY7
H21
KEY8
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
VLDT_RUN_B
VTT_DDR
C10u10Y0805
C10u10Y0805
E20
B19
CPU_THERM_ALERT
AL4
AK4
AK3
F2
F3
CPU_VDDNB_FB_H
G4
CPU_VDDNB_FB_L
G3
CORE_SEL
G5
AD25
AE24
AE25
AJ18
AJ20
C18
C20
G24
G25
H25
V29
W30
TP11TP11
C87
C87
R78
R78
1KR0402
1KR0402
R455
R455
0R0402
0R0402
C94
C94
X_C0.01u25Y
X_C0.01u25Y
VCC_DDR
R121
R121
1KR0402
1KR0402
CPU_VDDNB_FB_H [32]
CPU_VDDNB_FB_L [32]
C92
C92
X_C0.01u25Y
X_C0.01u25Y
CPU_THERM_ALERT [18]
CORE_SEL [32]
C91
C91
X_C0.01u25Y
X_C0.01u25Y
C181
C272
C272
2.2uf/6.3V/X5R/6
A A
5
4
2.2uf/6.3V/X5R/6
VCCP
3
C181
C10u10Y0805
C10u10Y0805
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CPU-Power & GND
CPU-Power & GND
CPU-Power & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
1
of
of
of
838Wednesday, November 05, 2008
838Wednesday, November 05, 2008
838Wednesday, November 05, 2008
5
4
3
VCC_DDR
2
1
VTT_DDR
C215
C67
C61
C21
D D
C21
C10u10Y0805
C10u10Y0805
VTT_DDR
C61
C10u10Y0805
C10u10Y0805
C46
C46
X_C0.22u16X
X_C0.22u16X
C67
X_C0.22u16X
X_C0.22u16X
C215
X_C1000p50X0402
X_C1000p50X0402
C54
C54
X_C1000p50X0402
X_C1000p50X0402
C221
C221
X_C180p50N0402
X_C180p50N0402
C208
C208
X_C180p50N0402
X_C180p50N0402
VCC_DDR
C156
C156
X_C10u10Y0805
X_C10u10Y0805
C161
C161
X_C10u10Y0805
X_C10u10Y0805
C157
C157
C10u10Y0805
C10u10Y0805
C102
C102
X_C1u16X
X_C1u16X
C129
C129
X_C4.7u10Y0805
X_C4.7u10Y0805
C538
C538
C0.1u16Y0402
C0.1u16Y0402
C218
C218
X_C4.7u10Y0805
X_C4.7u10Y0805
C545
C545
X_C0.1u16Y0402
X_C0.1u16Y0402
C150
C150
C47p50N0402
C47p50N0402
C570
C570
C0.22u16X
C0.22u16X
C571
C571
C180p50N0402
C180p50N0402
C95
C95
C47p50N0402
C47p50N0402
Bottom side
C70
C108
C108
X_C10u10Y0805
X_C10u10Y0805
C C
B B
VCCP
VCCP
VCCP
C201
C201
X_C4.7u10Y0805
X_C4.7u10Y0805
C558
C558
C22u6.3X1206
C22u6.3X1206
C565
C565
C22u6.3X1206
C22u6.3X1206
C197
C197
X_C0.22u16X
X_C0.22u16X
Bottom side
C568
C568
C22u6.3X1206
C22u6.3X1206
C544
C544
C22u6.3X1206
C22u6.3X1206
C36
C36
X_C0.22u16X
X_C0.22u16X
C542
C542
C22u6.3X1206
C22u6.3X1206
C540
C540
C22u6.3X1206
C22u6.3X1206
C70
X_C1000p50X0402
X_C1000p50X0402
C553
C553
C22u6.3X1206
C22u6.3X1206
C543
C543
C22u6.3X1206
C22u6.3X1206
C74
C74
C0.1u16Y0402
C0.1u16Y0402
C564
C564
C22u6.3X1206
C22u6.3X1206
C559
C559
C22u6.3X1206
C22u6.3X1206
C569
C569
C22u6.3X1206
C22u6.3X1206
C541
C541
C22u6.3X1206
C22u6.3X1206
C174
C174
X_C180p50N0402
X_C180p50N0402
C548
C548
C22u6.3X1206
C22u6.3X1206
C106
C106
X_C180p50N0402
X_C180p50N0402
VCC_DDR
C554
C554
C10u10Y0805
C10u10Y0805
VCC1_2HT
C539
C539
C10u10Y0805
C10u10Y0805
C198
C198
X_C0.22u16X
X_C0.22u16X
VDD_NB
VDD_NB
C177
C177
C0.1u16Y0402
C0.1u16Y0402
C589
C589
X_C10u16Y1206
X_C10u16Y1206
C574
C574
1u16X
1u16X
C549
C549
1u16X
1u16X
C189
C189
C10u10Y0805
C10u10Y0805
C664
C664
C10u16Y1206
C10u16Y1206
C575
C575
1u16X
1u16X
C196
C196
X_1u16X
X_1u16X
Top side
C151
C151
X_1u16X
X_1u16X
C195
C191
C191
X_C10u10Y0805
C562
C562
X_C0.22u16X
X_C0.22u16X
VCCP
C547
C547
C22u6.3X1206
A A
C22u6.3X1206
C537
C537
X_C0.22u16X
X_C0.22u16X
5
C536
C536
X_C0.22u16X
X_C0.22u16X
C534
C534
X_C1000p50X0402
X_C1000p50X0402
C535
C535
X_C180p50N0402
X_C180p50N0402
4
VDD_NB
C693
C693
X_C0.22u16X
X_C0.22u16X
3
X_C10u10Y0805
C665
C665
C0.22u16X
C0.22u16X
C194
C194
X_C10u10Y0805
X_C10u10Y0805
C75
C75
C0.1u16Y0402
C0.1u16Y0402
C195
C10u10Y0805
C10u10Y0805
C79
C79
C0.1u16Y0402
C0.1u16Y0402
2
C82
C82
X_C0.1u16Y0402
X_C0.1u16Y0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CPU-Decoupling
CPU-Decoupling
CPU-Decoupling
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
938Wednesday, November 05, 2008
938Wednesday, November 05, 2008
938Wednesday, November 05, 2008
of
of
1
of
5
D D
MEM_MA_DATA[63..0][7]
C C
B B
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
DIMM1
DIMM1
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
170
197
55
102
19
NC
3
RC118RC0
DQ0
4
DQ1
9
NC/TEST
DQ2
10
DQ3
DQ4
DQ5
DQ6
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
DQ12
DQ13
DQ14
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
DQ20
DQ21
DQ22
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
DQ28
DQ29
DQ30
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
DQ36
DQ37
DQ38
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
DQ44
DQ45
DQ46
DQ47
98
DQ48
99
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VSS
VSS
VSS
VSS
100
103
106
109
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
VSS
112
115
118
121
124
191
194
75
VDD6
VDD3
VSS
VSS
VSS
VSS
VSS
VSS
127
130
133
136
139
181
VDD7
VSS
142
175
VDD8
VDDQ0
VSS
VSS
145
148
151
VDDQ153VDDQ259VDDQ364VDDQ4
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
154
157
160
163
172
166
N13-2400301-K06 N13-2400351-K06
187
VDDQ5
VSS
169
184
VDDQ6
VDDQ7
VSS
VSS
198
4
238
189
67
178
VDDQ8
VSS
VSS
201
204
VDDQ9
VSS
207
210
VSS
213
VDDSPD
VSS
VSS
216
219
CB042CB143CB248CB349CB4
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
VSS
VSS
222
225
228
161
162
167
CB5
CB6
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
VREF
VSS
VSS
VSS
231
234
237
168
CB7
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
190
BA1
71
BA0
73
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
SCL
119
SDA
1
239
SA0
240
SA1
101
SA2
DDRII-240_GREEN
DDRII-240_GREEN
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4 MEM_MB_DATA10
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_RAS_L
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA0_ODT0
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
SMB_MEM_CLK
SMB_MEM_DATA
VDDR_VREF
MEM_MA_DQS_H0 [7]
MEM_MA_DQS_L0 [7]
MEM_MA_DQS_H1 [7]
MEM_MA_DQS_L1 [7]
MEM_MA_DQS_H2 [7]
MEM_MA_DQS_L2 [7]
MEM_MA_DQS_H3 [7]
MEM_MA_DQS_L3 [7]
MEM_MA_DQS_H4 [7]
MEM_MA_DQS_L4 [7]
MEM_MA_DQS_H5 [7]
MEM_MA_DQS_L5 [7]
MEM_MA_DQS_H6 [7]
MEM_MA_DQS_L6 [7]
MEM_MA_DQS_H7 [7]
MEM_MA_DQS_L7 [7]
MEM_MA_ADD[15..0] [7,12]
MEM_MA_BANK2 [7,12]
MEM_MA_BANK1 [7,12]
MEM_MA_BANK0 [7,12]
MEM_MA_WE_L [7,12]
MEM_MA_CAS_L [7,12]
MEM_MA_RAS_L [7,12]
MEM_MA_DM[7..0] MEM_MB_DM[7..0]
MEM_MA0_ODT0 [7,12]
MEM_MA_CKE0 [7,12]
MEM_MA0_CS_L0 [7,12]
MEM_MA0_CS_L1 [7,12]
MEM_MA0_CLK_H0 [7,12]
MEM_MA0_CLK_L0 [7,12]
MEM_MA0_CLK_H1 [7,12]
MEM_MA0_CLK_L1 [7,12]
MEM_MA0_CLK_H2 [7,12]
MEM_MA0_CLK_L2 [7,12]
SMB_MEM_CLK [18]
SMB_MEM_DATA [18]
C38
C38
X_C0.1u16Y0402
X_C0.1u16Y0402
MEM_MA_DM[7..0] [7]
ADDRESS: 1010 000
3
DIMM2
DIMM2
55
102
MEM_MB_DATA[63..0][7]
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
19
NC
3
RC118RC0
DQ0
4
DQ1
9
NC/TEST
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VSS
VSS
VSS
VSS
100
103
106
109
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
VSS
112
115
118
121
191
75
VDD3
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
2
VCC3VCC_DDRVCC3VCC_DDR
172
187
184
178
VDDQ5
VDDQ6
VDDQ7
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
163
166
169
198
201
189
204
67
VDDQ8
VSS
207
VDDQ9
VSS
210
VSS
238
VDDSPD
VSS
213
216
CB042CB143CB248CB349CB4
VSS
VSS
VSS
219
222
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
225
228
161
162
167
168
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
SCL
SDA
VREF
SA0
SA1
SA2
VSS
VSS
VSS
DDRII-240_ORANGE
DDRII-240_ORANGE
231
234
237
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
28
MEM_MB_DQS_L2
27
MEM_MB_DQS_H3
37
MEM_MB_DQS_L3
36
MEM_MB_DQS_H4
84
MEM_MB_DQS_L4
83
MEM_MB_DQS_H5
93
MEM_MB_DQS_L5
92
MEM_MB_DQS_H6
105
MEM_MB_DQS_L6
104
MEM_MB_DQS_H7
114
MEM_MB_DQS_L7
113
46
45
MEM_MB_ADD0
188
MEM_MB_ADD1
183
MEM_MB_ADD2
63
MEM_MB_ADD3
182
MEM_MB_ADD4
61
MEM_MB_ADD5
60
MEM_MB_ADD6
180
MEM_MB_ADD7
58
MEM_MB_ADD8
179
MEM_MB_ADD9
177
MEM_MB_ADD10
70
MEM_MB_ADD11
57
MEM_MB_ADD12
176
MEM_MB_ADD13
196
MEM_MB_ADD14
174
MEM_MB_ADD15
173
MEM_MB_BANK2
54
MEM_MB_BANK1
190
MEM_MB_BANK0
71
MEM_MB_WE_L
73
MEM_MB_CAS_L
74
MEM_MB_RAS_L
192
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
146
147
MEM_MB_DM3
155
156
MEM_MB_DM4
202
203
MEM_MB_DM5
211
212
MEM_MB_DM6
223
224
MEM_MB_DM7
232
233
164
165
MEM_MB0_ODT0
195
77
52
171
MEM_MB0_CS_L0
193
MEM_MB0_CS_L1
76
MEM_MB0_CLK_H0
185
MEM_MB0_CLK_L0
186
MEM_MB0_CLK_H1
137
MEM_MB0_CLK_L1
138
MEM_MB0_CLK_H2
220
MEM_MB0_CLK_L2
221
SMB_MEM_CLK
120
SMB_MEM_DATA
119
VDDR_VREF
1
VCC3
239
240
101
C39
C39
C0.1u16Y0402
C0.1u16Y0402
PLACE CLOSE TO DIMM PINPLACE CLOSE TO DIMM PIN
MEM_MB_DQS_H0 [7]
MEM_MB_DQS_L0 [7]
MEM_MB_DQS_H1 [7]
MEM_MB_DQS_L1 [7]
MEM_MB_DQS_H2 [7]
MEM_MB_DQS_L2 [7]
MEM_MB_DQS_H3 [7]
MEM_MB_DQS_L3 [7]
MEM_MB_DQS_H4 [7]
MEM_MB_DQS_L4 [7]
MEM_MB_DQS_H5 [7]
MEM_MB_DQS_L5 [7]
MEM_MB_DQS_H6 [7]
MEM_MB_DQS_L6 [7]
MEM_MB_DQS_H7 [7]
MEM_MB_DQS_L7 [7]
MEM_MB_BANK2 [7,12]
MEM_MB_BANK1 [7,12]
MEM_MB_BANK0 [7,12]
MEM_MB_WE_L [7,12]
MEM_MB_CAS_L [7,12]
MEM_MB_RAS_L [7,12]
MEM_MB0_ODT0 [7,12]
MEM_MB_CKE0 [7,12]
MEM_MB0_CS_L0 [7,12]
MEM_MB0_CS_L1 [7,12]
MEM_MB0_CLK_H0 [7,12]
MEM_MB0_CLK_L0 [7,12]
MEM_MB0_CLK_H1 [7,12]
MEM_MB0_CLK_L1 [7,12]
MEM_MB0_CLK_H2 [7,12]
MEM_MB0_CLK_L2 [7,12]
SMB_MEM_CLK [18]
SMB_MEM_DATA [18]
170
197
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
139
142
145
148
151
154
157
160
1
MEM_MB_ADD[15..0] [7,12]
MEM_MB_DM[7..0] [7]
ADDRESS: 1010 001
VCC_DDR
VCC_DDR
C99
C99
X_C10u10Y0805
X_C10u10Y0805
A A
5
15R1%
15R1%
15R1%
15R1%
R27
R27
C33
C33
X_C0.1u16Y0402
X_C0.1u16Y0402
R29
R29
C37
C37
X_C0.1u16Y0402
X_C0.1u16Y0402
VDDR_VREF
VDDR_VREF
4
VCC3 VCC3
R199
R199
2.7KR0402
2.7KR0402
SMB_MEM_CLK SMB_MEM_DATA
3
2
D20
D20
1PS226_SOT23
1PS226_SOT23
1
R198
R198
2.7KR0402
2.7KR0402
3VDUAL3VDUAL
2
D21
D21
1PS226_SOT23
1PS226_SOT23
3
1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
FIRST LOGICAL DDRII DIMM
FIRST LOGICAL DDRII DIMM
FIRST LOGICAL DDRII DIMM
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
1
10 38Wednesday, November 05, 2008
10 38Wednesday, November 05, 2008
10 38Wednesday, November 05, 2008
of
of
of
5
D D
4
3
2
1
close VGA connector
R[15]
R120
R120
150R1%0402
150R1%0402
G[15]
B[15]
C C
DDC_CLK VGA_14
DDC_CLK[15]
DDC_DATA[15]
R108 X_10KR0402R108 X_10KR0402
HSYNC#
HSYNC#[15]
B B
VSYNC#
VSYNC#[15]
5V_HSYNC
5V_VSYNC
U40_1
HSYNC#
VSYNC#
R110 33RR110 33R
R109 33RR109 33R
R102 X_33RR102 X_33R
R94 X_33RR94 X_33R
R104 60L500mA-100-RHR104 60L500mA-100-RH
R95 60L500mA-100-RHR95 60L500mA-100-RH
VCC5
C135 X_C0.1U16Y0402C135 X_C0.1U16Y0402
1 2
53
1
4
2
U9
U9
X_NC7SZ08M5X_SOT23-5
X_NC7SZ08M5X_SOT23-5
VCC5
C107 X_C0.1U16Y0402C107 X_C0.1U16Y0402
1 2
53
1
4
2
U8
U8
X_NC7SZ08M5X_SOT23-5
X_NC7SZ08M5X_SOT23-5
5V_HSYNC
5V_VSYNC
VCC5
3
VCC5
3
R118
R118
150R1%0402
150R1%0402
R114
R114
150R1%0402
150R1%0402
2
D10
D10
1PS226_SOT23
1PS226_SOT23
1
2
D8
D8
1PS226_SOT23
1PS226_SOT23
1
2
3
1
VCC5
2
3
1
3
3
3
D9
D9
1PS226_SOT23
1PS226_SOT23
R113
R113
2.2KR0402
2.2KR0402
D7
D7
1PS226_SOT23
1PS226_SOT23
2
1
2
1
2
1
VCC5VCC5
VCC5
D14
D14
1PS226_SOT23
1PS226_SOT23
VCC5
D13
D13
1PS226_SOT23
1PS226_SOT23
VCC5
D11
D11
1PS226_SOT23
1PS226_SOT23
R112
R112
2.2KR0402
2.2KR0402
X_C22p50N0402
X_C22p50N0402
X_C22p50N0402
X_C22p50N0402
C169
C169
X_C10p50N0402
X_C10p50N0402
X_C10p50N0402
X_C10p50N0402
X_C10p50N0402
X_C10p50N0402
DVI_VCC5[22]
C103
C103
C120
C120
C153
C153
C22p50N0402
C22p50N0402
C98
C98
C0.1U16Y0402
C0.1U16Y0402
VGAGND
VGA_15
VGA_9DDC_DATA
VGA_13
VGA_12
C154
C154
C22p50N0402
C22p50N0402
1 2
C165
C165
1 2
C159
C159
1 2
2 1
68n300mAL468n300mA
2 1
68n300mAL368n300mA
C10P50N0402
C10P50N0402
2 1
68n300mAL268n300mA
C10P50N0402
C10P50N0402
L4
C168
C168
C10P50N0402
C10P50N0402
L3
C164
C164
L2
C158
C158
Width = 4.5 milsWidth = 4.5 mils
1 2
VGAGND
1 2
VGAGND
1 2
VGAGND
VGA_DVI-RH-4
VGA_DVI-RH-4
VGA_15
VGA_14
VGA_13
VGA_12
VGA_B
15
14
13
12
11
VGA_G
VGA_R
16 17
5
10
4
9
3
8
2
7
1
6
JVGA_DVI1A
JVGA_DVI1A
VGA_9
VGA_B
VGA_G
VGA_R
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
SECOND LOGICAL DDRII DIMM
SECOND LOGICAL DDRII DIMM
SECOND LOGICAL DDRII DIMM
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
1
11 38Wednesday, November 05, 2008
11 38Wednesday, November 05, 2008
11 38Wednesday, November 05, 2008
of
of
of
5
4
3
2
1
Place Between Processor and DIMMs
RTT:Place Behind DIMMs
VTT_DDR
RN13
RN13
8P4R-47R0402
MEM_MB_CKE0[7,10]
MEM_MB_ADD15[7,10]
D D
C C
VTT_DDR
MEM_MB_ADD14[7,10]
MEM_MB_BANK2[7,10]
MEM_MB_ADD12[7,10]
MEM_MA_BANK2[7,10]
MEM_MA_CKE0[7,10]
MEM_MA_ADD14[7,10]
MEM_MA_ADD15[7,10]
MEM_MB_ADD9[7,10]
MEM_MB_ADD11[7,10]
MEM_MA_ADD12[7,10]
MEM_MB_ADD7[7,10]
MEM_MA_ADD11[7,10]
MEM_MA_ADD9[7,10]
MEM_MA_ADD7[7,10]
MEM_MB_ADD8[7,10]
MEM_MB_ADD6[7,10]
MEM_MA_ADD8[7,10]
MEM_MA_ADD6[7,10]
MEM_MA_ADD5[7,10]
MEM_MB_ADD5[7,10]
MEM_MA_ADD4[7,10]
MEM_MA_ADD1[7,10]
MEM_MA_ADD3[7,10]
MEM_MB_ADD4[7,10]
MEM_MB_ADD3[7,10]
MEM_MA_ADD2[7,10]
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MA_BANK2
MEM_MA_CKE0
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MB_ADD9
MEM_MB_ADD11
MEM_MA_ADD12
MEM_MB_ADD7
MEM_MA_ADD11
MEM_MA_ADD9
MEM_MA_ADD7
MEM_MB_ADD8
MEM_MB_ADD6
MEM_MA_ADD8
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MA_ADD4
MEM_MA_ADD1
MEM_MA_ADD3
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MA_ADD2
8P4R-47R0402
1
2
3
4
5
6
7
8
RN14
RN14
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
RN15
RN15
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
RN16
RN16
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
RN17
RN17
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
RN18
RN18
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
RN19
RN19
8P4R-47R0402
8P4R-47R0402
1
2
3
4
5
6
7
8
MEM_MB_ADD1[7,10]
MEM_MB_ADD2[7,10]
MEM_MB_ADD0[7,10]
MEM_MB_BANK1[7,10]
MEM_MB_ADD10[7,10]
MEM_MB_BANK0[7,10]
MEM_MB_RAS_L[7,10]
MEM_MA_ADD0[7,10]
MEM_MA_ADD10[7,10]
MEM_MA_BANK1[7,10]
MEM_MA_BANK0[7,10]
MEM_MA_RAS_L[7,10]
MEM_MA0_CS_L0[7,10]
MEM_MB0_CS_L0[7,10]
MEM_MB_WE_L[7,10]
MEM_MA_WE_L[7,10]
MEM_MA0_ODT0[7,10]
MEM_MA_CAS_L[7,10]
MEM_MA_ADD13[7,10]
MEM_MB_CAS_L[7,10]
MEM_MB0_ODT0[7,10]
MEM_MA0_CS_L1[7,10]
MEM_MB_ADD13[7,10]
MEM_MB0_CS_L1[7,10]
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_RAS_L
MEM_MA_ADD0
MEM_MA_ADD10
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_RAS_L
MEM_MA0_CS_L0
MEM_MB0_CS_L0
MEM_MB_WE_L
MEM_MA_WE_L
MEM_MA0_ODT0
MEM_MA_CAS_L
MEM_MA_ADD13
MEM_MB_CAS_L
MEM_MB0_ODT0
MEM_MA0_CS_L1
MEM_MB_ADD13
MEM_MB0_CS_L1
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
RN20
RN20
8P4R-47R0402
8P4R-47R0402
2
4
6
8
RN21
RN21
8P4R-47R0402
8P4R-47R0402
2
4
6
8
RN22
RN22
8P4R-47R0402
8P4R-47R0402
2
4
6
8
RN23
RN23
8P4R-47R0402
8P4R-47R0402
2
4
6
8
RN24
RN24
8P4R-47R0402
8P4R-47R0402
2
4
6
8
RN26
RN26
8P4R-47R0402
8P4R-47R0402
2
4
6
8
VTT_DDR
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3 MEM_MB_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C551 C22p50N0402C551 C22p50N0402
C546 C22p50N0402C546 C22p50N0402
C584 C22p50N0402C584 C22p50N0402
C550 C22p50N0402C550 C22p50N0402
C556 C22p50N0402C556 C22p50N0402
C581 C22p50N0402C581 C22p50N0402
C563 C22p50N0402C563 C22p50N0402
C555 C22p50N0402C555 C22p50N0402
C561 C22p50N0402C561 C22p50N0402
C567 C22p50N0402C567 C22p50N0402
C560 C22p50N0402C560 C22p50N0402
C572 C22p50N0402C572 C22p50N0402
C566 C22p50N0402C566 C22p50N0402
C573 C22p50N0402C573 C22p50N0402
C576 C22p50N0402C576 C22p50N0402
C579 C22p50N0402C579 C22p50N0402
C583 C22p50N0402C583 C22p50N0402
C580 C22p50N0402C580 C22p50N0402
C582 C22p50N0402C582 C22p50N0402
C557 C22p50N0402C557 C22p50N0402
C577 C22p50N0402C577 C22p50N0402
C578 C22p50N0402C578 C22p50N0402
VCC_DDR
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MA0_CLK_H2[7,10]
MEM_MA0_CLK_L2[7,10]
MEM_MA0_CLK_H1[7,10]
MEM_MA0_CLK_L1[7,10]
MEM_MA0_CLK_H0[7,10]
MEM_MA0_CLK_L0[7,10]
C105 C22p50N0402C105 C22p50N0402
C100 C22p50N0402C100 C22p50N0402
C173 C22p50N0402C173 C22p50N0402
C104 C22p50N0402C104 C22p50N0402
C110 C22p50N0402C110 C22p50N0402
C155 C22p50N0402C155 C22p50N0402
C119 C22p50N0402C119 C22p50N0402
C109 C22p50N0402C109 C22p50N0402
C114 C22p50N0402C114 C22p50N0402
C125 C22p50N0402C125 C22p50N0402
C113 C22p50N0402C113 C22p50N0402
C134 C22p50N0402C134 C22p50N0402
C124 C22p50N0402C124 C22p50N0402
C136 C22p50N0402C136 C22p50N0402
C138 C22p50N0402C138 C22p50N0402
C144 C22p50N0402C144 C22p50N0402
C148 C22p50N0402C148 C22p50N0402
C163 C22p50N0402C163 C22p50N0402
C160 C22p50N0402C160 C22p50N0402
C111 C22p50N0402C111 C22p50N0402
C140 C22p50N0402C140 C22p50N0402
C143 C22p50N0402C143 C22p50N0402
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
VCC_DDR
C185
C185
C1.5p50N0402
C1.5p50N0402
C69
C69
C1.5p50N0402
C1.5p50N0402
C122
C122
C1.5p50N0402
C1.5p50N0402
C187
C12
C220
C220
C0.1u16Y0402
C0.1u16Y0402
B B
VTT_DDR
C115
C115
C0.1u16Y0402
C0.1u16Y0402
A A
C152
C152
C0.1u16Y0402
C0.1u16Y0402
C204
C204
C0.1u16Y0402
C0.1u16Y0402
VTT_DDR VCC_DDR
C192 X_C0.1u16Y0402C192 X_C0.1u16Y0402
C182 X_C0.1u16Y0402C182 X_C0.1u16Y0402
C145 X_C0.1u16Y0402C145 X_C0.1u16Y0402
C216 X_C0.1u16Y0402C216 X_C0.1u16Y0402
C188 X_C0.1u16Y0402C188 X_C0.1u16Y0402
C183 X_C0.1u16Y0402C183 X_C0.1u16Y0402
5
C240
C240
X_C0.1u16Y0402
X_C0.1u16Y0402
C121
C121
C0.1u16Y0402
C0.1u16Y0402
C12
X_C0.1u16Y0402
X_C0.1u16Y0402
C132
C132
C0.1u16Y0402
C0.1u16Y0402
C175
C175
C0.1u16Y0402
C0.1u16Y0402
C44
C44
C0.1u16Y0402
C0.1u16Y0402
C241 X_C0.1u16Y0402C241 X_C0.1u16Y0402
C123 X_C0.1u16Y0402C123 X_C0.1u16Y0402
C203 X_C0.1u16Y0402C203 X_C0.1u16Y0402
C190 X_C0.1u16Y0402C190 X_C0.1u16Y0402
C170 X_C0.1u16Y0402C170 X_C0.1u16Y0402
C193 X_C0.1u16Y0402C193 X_C0.1u16Y0402
C11
C11
X_C0.1u16Y0402
X_C0.1u16Y0402
4
C187
C0.1u16Y0402
C0.1u16Y0402
VCC_DDRVTT_DDR
C260
C260
X_C0.1u16Y0402
X_C0.1u16Y0402
C142
C142
C0.1u16Y0402
C0.1u16Y0402
MEM_MB0_CLK_H2[7,10]
MEM_MB0_CLK_L2[7,10]
MEM_MB0_CLK_H1[7,10]
MEM_MB0_CLK_L1[7,10]
MEM_MB0_CLK_H0[7,10]
MEM_MB0_CLK_L0[7,10]
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
DDRII Termination
DDRII Termination
DDRII Termination
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MS-7509 2008/09/01 20
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
1
12 38Wednesday, November 05, 2008
12 38Wednesday, November 05, 2008
12 38Wednesday, November 05, 2008
C180
C180
C1.5p50N0402
C1.5p50N0402
C72
C72
C1.5p50N0402
C1.5p50N0402
C130
C130
C1.5p50N0402
C1.5p50N0402
of
of
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