MSI MS-7062 Schematics
1
Cover Sheet
Block Diagram
Clock Map
Power Map
Intel LGA775 CPU
Intel Grantsdale - MCH
Intel ICH6 - PCI & DMI & CPU & IRQ
Intel ICH6 - LPC & ATA & USB & GPIO 13
Intel ICH6 - POWER
Clock - ICS954130 and BUFFER
LPC I/O - W83627EHF
Azalia ALC880
DDR II System Memory 1 & 2
DDR II System Memory 3 & 4
DDR II VTT Decoupling
A A
PCI EXPRESS X16 Slot 1
PCI Slot 1 & 2 & 3
ATA33/66/100 IDE & SATA Connectors
VGA Connector
USB Connectors
BTX Connetcor & Front Panel
FWH 27
ACPI Controller MS7
VRM 10.1 - Intersil HIP 6556 + HIP 6602B x1
RTL8110S/8100C 30
VT6307 1394-2 PORTS
History
AutoBOM parts
1
2
3
4
5-7
8-11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
31
32
33
MS-7062
Version 20A
12/28/2005
Intel (R) Grantsdale (GMCH) + ICH6 Chipset
Intel Tejas & Pre sc ot t/Cedar Mill LGA775 Processor
CPU:
Intel Tejas/Prescott/Cedar Mill - 3.0G & Above
System Chipset:
Intel Grantsdale - GMCH (North Bridge)
Intel ICH6 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
Aliza Codec -- ALC880
LPC Super I/O -- W83627EHF
LAN--RTL8110S/8100C
CLOCK -- ICS954130 and BUFFER 9FG130
1394 Controller -- VT6307 2pots
Main Memory:
DDR II * 4 (Max 4GB)
Expansion Slots:
PCI2.2 SLOT * 3
PCI EXPRESS X16 SLOT *1
Intersil PWM:
Controller: HIP6556 3 Phase
Driver: HIP6602B * 1
Driver: HIP6601B * 1
1
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
COVER SHEET
MS-7062
133Thursday, March 02, 2006
20A
Block Diagram
1
VRM 10.1
Intersil 6556
3-Phase PWM
PCI EXPRESS
X16
Connector
Analog
Video
Out
UltraDMA
IDE Primary
A A
SATA 0~3
33/66/100
SATA
USB
Intel LGA775 Processor
FSB
200MHz
Grantsdale
DMI
ICH6
64bit DDR
200/266MHz
PCI CNTRL
PCI ADDR/DATA
4 DDR II
DIMM
Modules
J1394_1
VT6307
J1394_2
1394
PCI Slot 1
PCI Slot 2
PCI Slot 3
USB Port 0~7
LPC Bus
ALC880
33MHz@16.5MB/s
Azalia Codec
Realtek
RTL8110S
RTL8100C
PCI LAN
Flash
LPC SIO
Winbond
83627EHF
Keyboard
Floopy Parallel Serial
Mouse
MSI
Title
Size Document Number Rev
1
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
MS-7028
233Thursday, March 02, 2006
20A
5
4
3
2
1
HCLK
LGA775
CLOCK MAP
D D
MCHCLK
Grantsdale
MCH
ICS 954130
DOTCLK
96MHz
ICHCLK
Clock
Generator
SATACLK
USB48MHz
ICH6
ICH14.318MHz
C C
SIO48MHz
FWH_PCLK
33MHz
LAN_CLK66
33MHz
B B
1394_PCLK
33MHz
Winbon
LPC IO
FWH
RTL8110S
&
8100C
VT6307
1394
MCH_PE
100MHz
PCI_EXPRESS_SEED
ICH_PE
100MHz
ICS 9FG130
PCI-Express
Clock Buffer
PCI_E1_100MHz
PCI_E1
PCI-Express X 16
PCI1
A A
5
PCICLK[0..2]
33MHz
PCI2
MSI
PCI3
4
3
2
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
CLOCK MAP
MS-7062
333Thursday, March 02, 2006
1
20A
5
4
3
2
1
POWER MAP
D D
BTX POWER
+12V +5V +3.3V +5VSB
1.875A
6.5A
3.75A
8.5A
PCI_E1
PCI1
PCI2
PCI3
C C
MSI
ACPI
Controller
MS - 7
B B
5VDIMM
MSI
MS6 +
V_1P5_CORE
VCC_DDR
14.0A
Grantsdale
4.6A
MCH
11.1A
9.4A
DDR2 X 4
1.2A
1.2A
LANV1_8
RTL8110S
LGA775VRM 10.1
2.57A
ICH6
0.33A
V_FSB_VTT
A A
VCC3_SB VTT_DDR
W83310DS
5VDUAL
5
4
5.0A
1.2A
4.0A
USB
3
2
/8100C
MSI
Title
Size Document Number Rev
Date: Sheet of
LANV2_5
MICRO-STAR INt'L CO., LTD.
POWER MAP
MS-7062
1
20A
433Thursday, March 02, 2006
8
7
6
5
4
3
2
1
CPU SIGNAL BLOCK
D D
H_DBI#[0..3]8
H_EDRDY#8
H_IERR#6
H_FERR#6,12
H_STPCLK#12
H_INIT#12
H_DBSY#8
H_DRDY#8
H_TRDY#8
C C
B B
A A
H_LOCK#8
H_DEFER#8
CPU_TMPA16
VTIN_GND16
TRMTRIP#6,12
H_PROCHOT#6
H_IGNNE#12
ICH_H_SMI#12
C372 X_C0.1U50Y
R315 X_1KR
H_FSBSEL06,10,15
H_FSBSEL16,10,15
H_FSBSEL26,10,15
H_PWRGD6,12
H_CPURST#6,8
H_D#[0..63]8
H_ADS#8
H_BNR#8
H_HIT#8
H_HITM#8
H_BPRI#8
H_A20M#12
H_SLP#12
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
CPU_BOOTVTT_OUT_RIGHT
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_A#[3..31]8
A8
G11
D19
C20
F2
AB2
AB3
R3
M3
AD3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
AD1
AF1
AC1
AG1
AE1
AL1
AK1
M2
AE8
AL2
N2
P2
K3
L2
AH2
N5
AE6
C9
G10
D16
A20
Y1
V2
AA2
G29
H30
G30
N1
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
U14A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
H_A#10
H_A#8
H_A#7
H_A#5
H_A#3
H_A#6
H_A#22
H_A#18
H_A#27
H_A#30
H_A#26
H_A#31
H_A#29
H_A#25
H_A#28
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
F21
F20
B15
A14
C14
C15
D17
D20
H_D#51
H_D#49
H_D#53
H_D#52
H_D#50
H_D#48
F18
E22
E21
E19
E18
D22
G22
G21
H_D#39
H_D#44
H_D#38
H_D#41
H_D#47
H_D#42
H_D#40
H_D#46
H_D#43
H_D#45
H_A#16
H_A#24
H_A#23
AB5
AA5
A25#
A24#
D38#
D37#
F17
G17
H_D#37
H_D#36
H_A#14
H_A#20
H_A#15
H_A#19
H_A#17
H_A#21
AD6
AA4
AB6
A23#
A22#
A21#
A20#Y4A19#Y6A18#W6A17#
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
F15
F14
E16
E15
G18
G16
G15
G14
G13
H_D#30
H_D#32
H_D#29
H_D#35
H_D#33
H_D#28
H_D#34
H_D#31
H_D#27
H_A#12
H_A#13
D26#
E13
D13
H_D#25
H_D#26
H_A#11
U6
D25#
D24#
D23#
F12
F11
H_D#24
H_D#23
H_A#9
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#19
H_D#18
H_D#22
H_D#21
H_D#20
H_A#4
L5
H_D#17
H_D#16
R300 X_1KR
TP16
1
VSS_SENSE
VCC_SENSE
AJ3
AK3
AC2
AN5
AN4
AM5
AN6
AM7
AN3
DBR#
ITP_CLK1
ITP_CLK0
RSVD#AM7
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D14#
D13#
D12#D8D11#
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
B12
B10
A11
A10
D11
C12
C11
H_D#7
H_D#5
H_D#4
H_D#3
H_D#9
H_D#6
H_D#8
H_D#14
H_D#12
H_D#13
H_D#11
H_D#10
H_D#15
VID5
VID4
AL4
AK4
VID6#
VID5#
VID_SELECT
GTLREF_SEL
H_D#2
H_D#1
VID3
AL6
VID4#
FORCEPH
LINT1/NMI
LINT0/INTR
B4
H_D#0
FP_RST# 13,26
VID[0..5] 29
VID2
VID0
VID1
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
GTLREF0
H2
GTLREF1
H29
E24
GTLREF2
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
G6
RSVD#G6
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
K1
ZIF-SOCK775-15u-in
R445 62R
CPU_GTLREF0
CPU_GTLREF1
GTLREF_SEL
CPU_MCH_GTLREF
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_PCREQ#
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
TP14
1
TP13
1
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
1
1
1
1
VCC_SENSE
VSS_SENSE
CPU_GTLREF0 6
CPU_GTLREF1 6
1
CPU_MCH_GTLREF 8
H_PCREQ# 8
H_REQ#[0..4] 8
RN36 8P4R-62R
1
2
3
4
5
6
7
8
R274 62R
R177 62R
R316 62R
R174 62R
R288 X_62R
R325 X_62R
CK_H_CPU# 15
CK_H_CPU 15
H_RS#[0..2] 8
R293,R314 located 0-1.2 inches from the processor pin and connected
with a 10 mil trace width and 7 mil spacing to other traces.
R314 60.4R1%
R293 60.4R1%
R298 100R1%
R272 100R1%
R308 60.4R1%
R201 60.4R1%
TP7
TP6
TP9
TP8
H_ADSTB#1 8
H_ADSTB#0 8
H_DSTBP#3 8
H_DSTBP#2 8
H_DSTBP#1 8
H_DSTBP#0 8
H_DSTBN#3 8
H_DSTBN#2 8
H_DSTBN#1 8
H_DSTBN#0 8
H_NMI 12
H_INTR 12
R289 0R
C521
C10U16Y1206
R290 0R
TP1
V_FSB_VTT 6,8,10,1 4,15,28
VTT_OUT_RIGHT 6,7
VTT_OUT_LEFT 6
C382
X_C0.1U50Y
H_BR#0 6,8
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
VCC_VRM_SENSE 29
VCC_VRM_SENSE and VSS_VRM_SENSE
layout as Differential pair
VSS_VRM_SENSE 29
VCCP
+12V
R223
619R1%
R222
10KR
GTLREF_SEL
VTT_OUT_RIGHT
C356 C0 . 1U50Y
C357 C0 . 1U50Y
DS
G
VCC3
DS
G
VID3
VID1
VID4
VID2
VID0
R303 680R
VID5
R302 680R
RN33 8P4R-51R
1
3
5
7
1
3
5
7
RN34 8P4R-51R
R304 X_49.9R1%
R287 X_49.9R1%
R286 49.9R1%
PLACE BPM TERMINATION NEAR CPU
Q35
N-2N7002_SOT23
MCH_GTLREF 8
R209
249R1%
Q33
N-2N7002_SOT23
H_TESTHI0
RN35
8P4R-680R
1
2
3
4
5
6
7
8
2
4
6
8
2
4
6
8
VCC3
R210
110R1%
R211
61.9R1%
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TDI
H_BPM#2
H_BPM#4
H_TDO
H_TMS
H_TCK
H_TRST#
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet of
2
Intel LGA775 CPU - Signals
MS-7062
533Thursday, March 02, 2006
1
20A
MICRO-STAR INt'L CO., LTD.
MSI
8
VCCP
AF22
AF21
AG18
AG15
AG14
AG12
AG11
AF9
AF8
U14B
VCCP
AF19
VCC#AF19
VCC#AF9
D D
C C
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
VCC#AF8
VCC#AF22
VCC#AF21
VCC#AG18
VCC#AG15
VCC#AG14
VCC#AG12
VCC#AG11
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
AE9
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
AD8
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
AC8
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
AB8
VCC#AB8
AA8
VCC#AA8
VCC#Y24
VCC#Y25
VCC#Y26
VCC#Y27
VCC#Y28
VCC#Y29
VCC#Y30
VCC#Y8
Y8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
VCCP
7
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
VCC#AG22
VCC#AG21
VCC#AG19
VCC#W29
VCC#W30
VCC#W8W8VCC#Y23
W28
W29
W30
AH12
AH11
VCC#AG9
VCC#AG8
VCC#AH11
VCC#AG30
VCC#AG29
VCC#AG28
VCC#AG27
VCC#AG26
VCC#AG25
VCC#U30
VCC#U8U8VCC#V8V8VCC#W23
VCC#W24
VCC#W25
VCC#W26
VCC#W27
VCC#W28
U29
U30
W23
W24
W25
W26
W27
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
VCC#AH27
VCC#AH26
VCC#AH25
VCC#AH22
VCC#AH21
VCC#AH19
VCC#AH18
VCC#AH15
VCC#AH14
VCC#AH12
VCC#T29
VCC#T30
VCC#T8T8VCC#U23
VCC#U24
VCC#U25
VCC#U26
VCC#U27
VCC#U28
VCC#U29
T29
T30
U23
U24
U25
U26
U27
U28
6
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AH28
AH29
AH30
VCC#AH8
VCC#AH9
VCC#AJ11
VCC#AJ12
VCC#AJ14
VCC#AH28
VCC#AH29
VCC#AH30
VCC#T24
VCC#T25
VCC#T26
VCC#T27
VCC#T28
T23
T24
T25
T26
T27
T28
AK11
AK12
AK14
AK15
AJ18
AJ19
AJ21
AJ22
VCC#AJ15
VCC#AJ18
VCC#AJ19
VCC#AJ21
VCC#N28
VCC#N29
VCC#N30
VCC#N8N8VCC#P8P8VCC#R8R8VCC#T23
N27
N28
N29
N30
AK18
AJ25
AJ26
AJ8
AJ9
VCC#AJ8
VCC#AJ9
VCC#AJ22
VCC#AJ25
VCC#AJ26
VCC#AK11
VCC#AK12
VCC#AK14
VCC#AK15
VCC#AK18
VCC#M27
VCC#M28
VCC#M29
VCC#M30
VCC#M8M8VCC#N23
VCC#N24
VCC#N25
VCC#N26
VCC#N27
N23
N24
N25
N26
M27
M28
M29
M30
AK19
AK21
VCC#AK19
VCC#AK21
VCC#M25
VCC#M26
M25
M26
AK22
AK25
VCC#AK22
VCC#AK25
VCC#M24
M23
M24
AK8
AK26
VCC#AK8
VCC#AK26
VCC#K8K8VCC#L8L8VCC#M23
AK9
AL11
VCC#AK9
VCC#K30
K29
K30
5
AM11
AL12
AL14
AL15
AL18
AL19
VCC#AL11
VCC#AL12
VCC#AL14
VCC#AL15
VCC#AL18
VCC#AL19
VCC#K24
VCC#K25
VCC#K26
VCC#K27
VCC#K28
VCC#K29
K24
K25
K26
K27
K28
AM12
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
VCC#AL8
VCC#AL9
VCC#AL21
VCC#AL22
VCC#AL25
VCC#AL26
VCC#AL29
VCC#AL30
VCC#AM11
VCC#J25
VCC#J26
VCC#J27
VCC#J28
VCC#J29
VCC#J30
VCC#J8J8VCC#J9J9VCC#K23
J24
J25
J26
J27
J28
J29
J30
K23
4
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCCA
VCC#AN11
VCC#AN12
VCC#AN8
VCC#AN9
AN8
VCC#AN14
VCC#AN15
VCC#AN18
VTT_OUT_RIGHT
VTT_OUT_LEFT
VCC#AN26
VCC#AN29
VCC#AN30
AN25
AN26
AN29
AN30
VCC#AN19
VCC#AN21
VCC-IOPLL
VTTPWRGD
RSVD#F29
VCC#AN25
VSSA
VCC#AN22
VCCPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTT_SEL
1122334
VCC#AM8
VCC#AM12
VCC#AM14
VCC#AM15
VCC#AM18
VCC#J21
VCC#J22
VCC#J23
VCC#J24
J21
J22
J23
VCC#AM9
VCC#AM19
VCC#AM21
VCC#AM22
VCC#AM25
VCC#AM26
VCC#AM29
VCC#AM30
VCC#J10
VCC#J11
VCC#J12
VCC#J13
VCC#J14
VCC#J15
VCC#J18
VCC#J19
VCC#J20
J10
J11
J12
J13
J14
J15
J18
J19
J20
AN9
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
4
3
H_VCCA
H_VSSA
H_VCCA
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
R172 X_1KR
VTT_SEL
VCC3
2
V_FSB_VTT
1
C222
C10U10Y0805
C220
C10U10Y0805
C214
X_C10U10Y0805
CAPS FOR FSB GENERIC
TEJ/PSC
0
1
RSVD
VTT_OUT_RIGHT
C349
VTT_OUT_RIGHT
C1U10Y
C512
C1U10Y
B B
R282
124R1%
R280
210R1%
R443
124R1%
R444
210R1%
R441 10R
R442 10R
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.75V
CPU_GTLREF0
C348
C220P50N
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.75V
CPU_GTLREF1
C511
C220P50N
CPU_GTLREF0 5
CPU_GTLREF1 5
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
L5 X_10U100m_0805
X_COPPER
VID_GD#28,29
C238
VTT_OUT_RIGHT
VCC5_SB
R121
1KR
R119 10KR
X_C1U10Y
CP6
R123 680R
B
C231
C10U10Y1206
CE
C233
X_C10U10Y1206
1.25V VTT_PWRGOOD
VTT_PWG
Q26
N-MMBT3904_NL_SOT23
H_VCCA
H_VSSA
C208
X_C1U10Y
PLACE AT CPU END OF ROUTE
TRMTRIP#
H_FERR#
H_IERR#
7
H_PROCHOT#
H_CPURST#
H_BR#0
H_PROCHOT# 5
H_CPURST# 5,8
H_PWRGD 5,12
H_BR#0 5,8
TRMTRIP# 5,12
H_FERR# 5,12
H_IERR# 5
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
6
5
RN21
1
3
5
7
8P4R-470R
H_FSBSEL1
2
4
6
8
H_FSBSEL0
H_FSBSEL2
4
H_FSBSEL1 5,10,15
H_FSBSEL0 5,10,15
H_FSBSEL2 5,10,15
Title
Size Document Number Rev
3
Date: Sheet of
2
Intel LGA775 CPU - Power
MS-7062
633Thursday, March 02, 2006
1
20A
MICRO-STAR INt'L CO., LTD.
MSI
VTT_OUT_RIGHT5,7
VTT_OUT_LEFT5
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT H_PWRGD
R301 120R
R178 62R
R318 100R
R271 62R
PLACE AT ICH END OF ROUTE
V_FSB_VTT
V_FSB_VTT5,8,10,14,15,28
8
R327 62R
R326 62R
R317 62R
8
7
6
5
4
3
2
1
H_COMP7
H_COMP6
AE3
COMP6Y3COMP7
VSS#AE29
VSS#AE30
VSS#AE5
AE5
AE30
R192
60.4R1%
AE4
D1
RSVD#D1
RSVD#AE4
VSS#AE7
VSS#AF10
AE7
AF10
TP4
1
D14
E23
RSVD#E23
RSVD#D14
VSS#AF13
VSS#AF16
AF13
AF16
R203 X_62R
RSVD#E5E5RSVD#E6E6RSVD#E7
VSS#AF17
VSS#AF20
AF17
AF20
AF23
TP10
1
1
E7
F23
RSVD#F23
VSS#AF23
VSS#AF24
VSS#AF25
AF24
AF25
TP5
TP11
1
1
F6
B13
IMPSEL#
VSS#AF26
AF26
AF27
TP12
RSVD#B13
VSS#AF27
VSS#AF28
VSS#AF29
AF28
AF29
R198
62R
J3
N4
RSVD#J3
VSS#AF3
AF3
AF30
P5
RSVD#P5
RSVD#N4
VSS#AF30
VSS#AF6
VSS#AF7
AF6
AF7
W1
MSID[1]V1MSID[0]
VSS#AG10
VSS#AG13
AG10
AG13
R200
62R
AC4
RSVD#AC4
VSS#AG16
VSS#AG17
AG16
AG17
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#AG20
VSS#AG23
AG20
AG23
Y2
VSS#AG24
VSS#AG7
AG7
AG24
W4
VSS#W7W7VSS#W4
VSS#AH1
AH1
AH10
V6
VSS#V7V7VSS#V6
VSS#AH10
VSS#AH13
VSS#AH16
AH13
AH16
V30
V3
VSS#V30
VSS#AH17
AH17
AH20
V29
V28
VSS#V3
VSS#V29
VSS#V28
VSS#AH20
VSS#AH23
VSS#AH24
AH23
AH24
V27
V26
VSS#V27
VSS#AH3
AH3
AH6
V25
V24
VSS#V26
VSS#V25
VSS#AH6
VSS#AH7
AH7
AJ10
V23
VSS#V24
VSS#V23
VSS#AJ10
VSS#AJ13
AJ13
AJ16
U1
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#AJ16
VSS#AJ17
VSS#AJ20
AJ17
AJ20
P30
P29
P28
P27
P26
P25
P24
R28
R27
VSS#R29
VSS#R28
VSS#AJ30
VSS#AJ4
AJ4
AJ7
R26
R25
VSS#R27
VSS#R26
VSS#AJ7
VSS#AK10
AK10
AK13
R24
R23
VSS#R25
VSS#R24
VSS#R23
VSS#AK13
VSS#AK16
VSS#AK17
AK16
AK17
R2
VSS#R2
VSS#AK2
AK2
AK20
P4
VSS#P7P7VSS#P4
VSS#P30
VSS#AK20
VSS#AK23
VSS#AK24
AK23
AK24
VSS#P29
VSS#P28
VSS#AK27
VSS#AK28
AK27
AK28
VSS#P27
VSS#AK29
AK29
AK30
VSS#P26
VSS#P25
VSS#AK30
VSS#AK5
AK5
AK7
T3
R30
R29
R5
VSS#R7R7VSS#R5
VSS#R30
VSS#AJ23
VSS#AJ24
VSS#AJ27
VSS#AJ28
VSS#AJ29
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
VSS#P24
VSS#P23
VSS#AK7
VSS#AL10
AL10
AL13
N3
VSS#N7N7VSS#N6N6VSS#N3
VSS#M7M7VSS#M1
VSS#AL13
VSS#AL16
VSS#AL17
VSS#AL20
AL16
AL17
AL20
M1
VSS#AL23
AL23
AL24
L30
L6
VSS#L7L7VSS#L6
VSS#L30
VSS#AL24
VSS#AL27
VSS#AL28
AL27
AL28
L3
VSS#L3
VSS#AL3
AL3
L29
AL7
P23
L28
VSS#L29
VSS#L28
VSS#AL7
VSS#AM1
AM1
L27
L26
VSS#L27
VSS#AM10
AM10
AM13
L25
VSS#L26
VSS#L25
VSS#AM13
VSS#AM16
AM16
L24
L23
VSS#L24
VSS#AM17
AM17
AM20
K5
VSS#K7K7VSS#K5
VSS#L23
VSS#AM20
VSS#AM23
AM23
AM24
VSS#AM24
K2
VSS#K2
VSS#AM27
AM27
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
J7
H9
H14
VSS#J4J4VSS#J7
VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9
VSS#H27
VSS#H28
VSS#AM28
VSS#AM4
VSS#AN1
VSS#AN10
VSS#AN13
VSS#AN16
VSS#AN17
VSS#AN2
VSS#AN20
AN1
AN2
AM4
AN10
AN13
AN16
AN17
AM28
AN20
VSS#H25
VSS#H26
VSS#AN23
VSS#AN24
AN23
AN24
VSS#H23
VSS#H24
VSS#AN27
VSS#AN28
AN27
AN28
VSS#H21
VSS#H22
VSS#B1B1VSS#B11
B11
VSS#H14
VSS#H13
VSS#H17
VSS#H18
VSS#H19
VSS#H20
VSS#H12
VSS#H11
VSS#H10
VSS#G1
VSS#F7
VSS#F4
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E8
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E2
VSS#E17
VSS#E14
VSS#E11
VSS#D9
VSS#D6
VSS#D5
VSS#D3
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C7
VSS#C4
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B8
VSS#B5
VSS#B24
VSS#B20
VSS#B17
VSS#B14
ZIF-SOCK775-15u-in
B14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
VTT_OUT_RIGHT5,6
D D
C C
B B
R183
60.4R1%
U14C
A12
VSS#A12
A15
VSS#A15
A18
VSS#A18
A2
VSS#A2
A21
VSS#A21
A24
VSS#A24
A6
VSS#A6
A9
VSS#A9
AA23
VSS#AA23
AA24
VSS#AA24
AA25
VSS#AA25
AA26
VSS#AA26
AA27
VSS#AA27
AA28
VSS#AA28
AA29
VSS#AA29
AA3
VSS#AA3
AA30
VSS#AA30
AA6
VSS#AA6
AA7
VSS#AA7
AB1
VSS#AB1
AB23
VSS#AB23
AB24
VSS#AB24
AB25
VSS#AB25
AB26
VSS#AB26
AB27
VSS#AB27
AB28
VSS#AB28
AB29
VSS#AB29
AB30
VSS#AB30
AB7
VSS#AB7
AC3
VSS#AC3
AC6
VSS#AC6
AC7
VSS#AC7
AD4
VSS#AD4
AD7
VSS#AD7
AE10
VSS#AE10
AE13
VSS#AE13
AE16
VSS#AE16
AE17
VSS#AE17
AE2
VSS#AE2
AE20
VSS#AE20
AE24
VSS#AE24
AE25
VSS#AE25
AE26
VSS#AE26
AE27
VSS#AE27
AE28
VSS#AE28
AE29
A A
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel LGA775 CPU - GND
2
MS-7062
20A
733Thursday, March 02, 2006
1
8
H_A#[3..31]5
D D
EMI
V_1P5_CORE
C252
C0.1U50Y
C251
C0.1U50Y
H_ADSTB#05
H_ADSTB#15
H_PCREQ#5
ICH_SYNC#13
PLTRST#12,28
H_BR#05,6
H_BPRI#5
H_BNR#5
H_LOCK#5
H_ADS#5
H_REQ#[0..4]5
H_RS#[0..2]5
R231 2 0 R1%
CK_H_MCH#15
H_CPURST#5,6
H_HIT#5
H_HITM#5
H_DEFER#5
H_TRDY#5
H_DBSY#5
H_DRDY#5
H_EDRDY#5
CK_H_MCH15
PWRGD_3V13,28
ICH_SYNC#
C C
B B
7
AC11
AB11
Y20
Y19
Y17
Y16
W20
W16
VCCNCTF
VCCNCTF
AJ21
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AK21
AK24
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AL21
AL20
U20
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AJ24
AK18
U15A
H_A#3 H_D#0
H29
HA3#
H_A#4
K29
HA4#
H_A#5
J29
HA5#
H_A#6
G30
HA6#
H_A#7
G32
HA7#
H_A#8
K30
HA8#
H_A#9
L29
HA9#
H_A#10
M30
HA10#
H_A#11
L31
HA11#
H_A#12
L28
HA12#
H_A#13
J28
HA13#
H_A#14
K27
HA14#
H_A#15
K33
HA15#
H_A#16
M28
HA16#
H_A#17
R29
HA17#
H_A#18
L26
HA18#
H_A#19
N26
HA19#
H_A#20
M26
HA20#
H_A#21
N31
HA21#
H_A#22
P26
HA22#
H_A#23
N29
HA23#
H_A#24
P28
HA24#
H_A#25
R28
HA25#
H_A#26
N33
HA26#
H_A#27
T27
HA27#
H_A#28
T31
HA28#
H_A#29
U28
HA29#
H_A#30
T26
HA30#
H_A#31
T29
HA31#
J31
HAD_STB0#
N27
HAD_STB1#
E31
HPCREQ#
R33
BREQ0#
E30
BPRI#
M35
BNR#
L33
HLOCK#
M31
ADS#
H_REQ#0
F33
HREQ0#
H_REQ#1
E32
HREQ1#
H_REQ#2
H31
HREQ2#
H_REQ#3
G31
HREQ3#
H_REQ#4
F31
HREQ4#
L34
HIT#
N35
HITM#
J35
DEFER#
N34
HTRDY#
L35
DBSY#
M32
DRDY#
P33
HEDRDY#
H_RS#0
K34
RS0#
H_RS#1
P34
RS1#
H_RS#2
J32
RS2#
M23
HCLKP
M22
HCLKN
AG7
PWROK
G24
CPURST#
AF7
RSTIN#
M14
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
HXRCOMP
ICH_SYNC#
B23
HDRCOMP
D24
HDSCOMP
A23
HDSWING
A24
HDVREF
U16
T20
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AJ23
AJ18
T19
T17
VCCNCTF
RSVRD
V31
AJ20
T16
AA13
VCCNCTF
VCCNCTF
RSVRD
RSVRD
V30
U30
AA14
AA16
VCCNCTF
VCCNCTF
RSVRD
RSVRD
V32
Y30
6
AA18
AA20
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
R31
AB29
AA21
AA22
VCCNCTF
RSVRD
R30
AA31
AA23
AA24
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AA30
AC12
V_1P5_CORE
AB13
AB14
AB15
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AC13
AC14
AC15
AB16
AB17
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AC16
AC17
AB18
AB19
VCCNCTF
RSVRD
AC18
AC19
AB20
AB21
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AC20
AC21
AB22
AB23
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AC22
AB24
N13
VCCNCTF
NC
N12NCN22NCN23NCN24
N14
N15
VCCNCTF
VCCNCTF
N16
N18
VCCNCTF
VCCNCTF
NC
P12NCP23NCP24
5
N20
N21
VCCNCTF
VCCNCTF
R12NCR24
P13
P14
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
T12
P15
P17
VCCNCTF
VCCNCTF
NC
NC
V12
U12
P19
P21
VCCNCTF
VCCNCTF
NC
NC
Y12
W12
P22
R13
VCCNCTF
NC
AA12NCAB12
R14
R15
VCCNCTF
VCCNCTF
NC
AC23NCAC24NCAN19
R16
R18
VCCNCTF
VCCNCTF
VCCNCTF
NC
AL28
R20
R22
VCCNCTF
NC
AJ14
AH24
R23
T13
VCCNCTF
VCCNCTF
NC
NC
AG6
AD30
T14
T15
VCCNCTF
VCCNCTF
NC
NC
L19NCL12
P30
T21
T23
VCCNCTF
VCCNCTF
NC
K12
4
T24
U13
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
NC
J12
H17NCH15NCH12
U14
U22
VCCNCTF
VCCNCTF
U24
V13
VCCNCTF
VCCNCTF
NC
NC
F24NCF12
G12
V14
V15
VCCNCTF
E16
V21
V23
VCCNCTF
VCCNCTF
NC
NC
C16
AR35NCAR34
V24
W13
VCCNCTF
VCCNCTF
NC
AR2NCAR1
W14
W22
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
AP35
W24
Y13
VCCNCTF
NC
B35
AP1
VCCNCTF
NC
Y14
Y15
Y21
Y23
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
NCB1NC
NC
INTEL-82915-G-C2-LF
A2
A34
3
Y24
VCCNCTF
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
2
J33
H_D#1
H33
H_D#2
J34
H_D#3
G35
H_D#4
H35
H_D#5
G34
H_D#6
F34
H_D#7
G33
H_D#8
D34
H_D#9
C33
H_D#10
D33
H_D#11
B34
H_D#12
C34
H_D#13
B33
H_D#14
C32
H_D#15
B32
H_D#16
E28
H_D#17
C30
H_D#18
D29
H_D#19
H28
H_D#20
G29
H_D#21
J27
H_D#22
F28
H_D#23
F27
H_D#24
E27
H_D#25
E25
H_D#26
G25
H_D#27
J25
H_D#28
K25
H_D#29
L25
H_D#30
L23
H_D#31
K23
H_D#32
J22
H_D#33
J24
H_D#34
K22
H_D#35
J21
H_D#36
M21
H_D#37
H23
H_D#38
M19
H_D#39
K21
H_D#40
H20
H_D#41
H19
H_D#42
M18
H_D#43
K18
H_D#44
K17
H_D#45
G18
H_D#46
H18
H_D#47
F17
H_D#48
A25
H_D#49
C27
H_D#50
C31
H_D#51
B30
H_D#52
B31
H_D#53
A31
H_D#54
B27
H_D#55
A29
H_D#56
C28
H_D#57
A28
H_D#58
C25
H_D#59
C26
H_D#60
D27
H_D#61
A27
H_D#62
E24
H_D#63
B25
H_DBI#0
E34
H_DBI#1
J26
H_DBI#2
K19
H_DBI#3
B26
E33
E35
H26
F26
J19
F19
B29
C29
H_DSTBP#0 5
H_DSTBN#0 5
H_DSTBP#1 5
H_DSTBN#1 5
H_DSTBP#2 5
H_DSTBN#2 5
H_DSTBP#3 5
H_DSTBN#3 5
H_D#[0..63] 5
H_DBI#[0..3] 5
U15_X1
X5
X6
X7
X8
MCH
Heatsink
1
X1
X2
X3
X4
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.75V
A A
8
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
V_FSB_VTT5,6,10,14,15,28
ICH_SYNC#
7
R234 60.4R1%
R253 8.2KR
HXSCOMP V_FSB_VTT
C297
X_C2.2P50N
V_2P5_MCH
6
V_FSB_VTT
R233
CPU_MCH_GTLREF
124R1%
R447 10R
R240
210R1%
C298
C1U10Y
CAPS SHOULD BE PLACED NEAR MCH PIN
5
CPU_MCH_GTLREF 5
MCH_GTLREF HXSWING
MCH_GTLREF 5
C299
X_C220P16X0402
4
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R228
300R1%
C296
R232
C0.01U50X
100R1%
3
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Grantsdale - C PU Signals
MS-7062
2
833Thursday, March 02, 2006
1
20A
8
D D
SCS_A#[0..3]18,20
MAA_A[0..13]18,20
ODT_A[0..3]18,20
C C
B B
PLACE 0.1UF CAP CLOSE TO MCH
A A
R266 8 0 . 6R1%
8
7
DATA_A[0..63]18
U15B
SCS_A#0
AR29
AP32
AR28
AN31
AP27
AN29
AN28
AP26
AR24
AP23
AR23
AP22
AN23
AP21
AN22
AN21
AM27
AM21
AR20
AP31
AP30
AN32
AP29
AP33
AR27
AN27
AN20
AF17
AG17
AM30
AG35
AG33
AA34
AA35
AN26
AP25
AC34
AC35
AN25
AM24
AC33
AB34
AB33
AH15
AE16
AK12
C339
C0.1U50Y
AL24
AG1
AG2
AL3
AL2
AP7
AR7
AL29
U34
U35
AM2
AM3
AN3
AN2
AJ12
AE7
AG8
AG4
AE5
AF5
DATA_B[0..63]19
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACK0
SACK0#
SACK1
SACK1#
SACK2
SACK2#
SACK3
SACK3#
SACK4
SACK4#
SACK5
SACK5#
SADDR1MA13
SARCVENOUT#
SARCVENIN#
SMSLEWIN0
SMSLEWOUT0
SMVREF0
SMRCOMP1
SMRCOMP0
SMOCDCOMP1
SMOCDCOMP0
VCC_DDR
C341
C0.1U50Y
R262 8 0 . 6R1%
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
RAS_A#18,20
CAS_A#
CAS_A#18,20
WE_A#
WE_A#18,20
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A018,20
SBS_A1
SBS_A118,20
SBS_A2
SBS_A218,20
DQS_A0
DQS_A018
DQS_A#0
DQS_A#018
DQS_A1
DQS_A118
DQS_A#1
DQS_A#118
DQS_A2
DQS_A218
DQS_A#2
DQS_A#218
DQS_A3
DQS_A318
DQS_A#3
DQS_A#318
DQS_A4
DQS_A418
DQS_A#4
DQS_A#418
DQS_A5
DQS_A518
DQS_A#5
DQS_A#518
DQS_A6
DQS_A618
DQS_A#6
DQS_A#618
DQS_A7
DQS_A718
DQS_A#7
DQS_A#718
P_DDR0_A
P_DDR0_A18
N_DDR0_A
N_DDR0_A18
P_DDR1_A
P_DDR1_A18
N_DDR1_A
N_DDR1_A18
P_DDR2_A
P_DDR2_A18
N_DDR2_A
N_DDR2_A18
P_DDR3_A
P_DDR3_A18
N_DDR3_A
N_DDR3_A18
P_DDR4_A
P_DDR4_A18
N_DDR4_A
N_DDR4_A18
P_DDR5_A
P_DDR5_A18
N_DDR5_A
N_DDR5_A18
SM_XSLEWIN
SM_XSLEWIN
MCH_VREF_A
SMPCOMP_P
SMPCOMP_N
R256 40.2R1%
R268 40.2R1%
MCH_VREF_A
SMPCOMP_P SMPCOMP_N
7
DATA_A0
AE3
DATA_A1
AF3
SADQ0
DATA_A2
AH3
SADQ1
AH4
DATA_B0
DATA_A3
AJ2
SADQ2
SBDQ0
AJ6
DATA_B1
6
DATA_A4
AE2
SADQ3
SBDQ1
AL6
DATA_B2
6
DATA_A5
AE1
SADQ4
SBDQ2
AN6
DATA_B3
DATA_A6
AG3
SADQ5
SBDQ3
AG9
DATA_B4
DATA_A7
AH2
SADQ6
SBDQ4
AH7
DATA_B5
DATA_A8
AK2
SADQ7
SBDQ5
AL5
DATA_B6
DATA_A9
AK3
SADQ8
SBDQ6
AM5
DATA_B7
DATA_A10
AN4
SADQ9
SBDQ7
AJ8
DATA_B8
DATA_A11
AP4
SADQ10
SADQ11
SBDQ8
SBDQ9
AL8
DATA_B9
DATA_A12
AJ1
SADQ12
SBDQ10
AF11
DATA_B10
DATA_A14
DATA_A13
AJ3
AP2
SADQ13
SBDQ11
AJ7
AE11
DATA_B11
DATA_B12
DATA_A15
AP3
SADQ14
SADQ15
SBDQ12
SBDQ13
AL7
DATA_B13
DATA_A16
AR5
AG10
DATA_B14
DATA_A17
AP6
SADQ16
SADQ17
SBDQ14
SBDQ15
AG11
DATA_B15
DATA_A18
AP9
SADQ18
SBDQ16
AF13
DATA_B16
DATA_A19
AN9
AH12
DATA_B17
DATA_A20
AN5
SADQ19
SADQ20
SBDQ17
SBDQ18
AD14
DATA_B18
DATA_A21
AP5
AD15
DATA_B19
DATA_A22
AN8
SADQ21
SADQ22
SBDQ19
SBDQ20
AD12
DATA_B20
DATA_A23
AR8
AE13
DATA_B21
DATA_A24
AL17
SADQ23
SADQ24
SBDQ21
SBDQ22
AG14
DATA_B22
DATA_A25
AJ17
AF14
DATA_B23
5
DATA_A26
AF19
SADQ25
SADQ26
SBDQ23
SBDQ24
AK19
DATA_B24
5
DATA_A27
DATA_A28
AH18
AK16
SADQ27
SBDQ25
AH19
AH21
DATA_B25
DATA_B26
DATA_A29
AF16
SADQ28
SADQ29
SBDQ26
SBDQ27
AD21
DATA_B27
DATA_A31
DATA_A30
AD17
AE19
SADQ30
SBDQ28
AL18
AD18
DATA_B28
DATA_B29
DATA_A32
AK27
SADQ31
SADQ32
SBDQ29
SBDQ30
AE22
DATA_B30
DATA_A34
DATA_A33
AJ28
AL31
SADQ33
SBDQ31
AF22
AF24
DATA_B32
DATA_B31
DATA_A35
AK31
SADQ34
SADQ35
SBDQ32
SBDQ33
AF25
DATA_B33
DATA_A36
AH27
AL26
DATA_B34
DATA_A37
AL27
SADQ36
SADQ37
SBDQ34
SBDQ35
AJ26
DATA_B35
DATA_A38
AN30
AF23
DATA_B36
DATA_A39
AL30
SADQ38
SADQ39
SBDQ36
SBDQ37
AD23
DATA_B37
DATA_A40
AH33
AL25
DATA_B38
DATA_A41
AH35
SADQ40
SADQ41
SBDQ38
SBDQ39
AJ25
DATA_B39
DATA_A42
AF33
AK32
DATA_B40
DATA_A43
AE33
SADQ42
SADQ43
SBDQ40
SBDQ41
AJ31
DATA_B41
DATA_A44
AJ33
AG31
DATA_B42
DATA_A45
AJ34
SADQ44
SADQ45
SBDQ42
SBDQ43
AF28
DATA_B43
DATA_A46
AG32
SADQ46
SBDQ44
AJ29
DATA_B44
DATA_A47
AF34
SADQ47
SBDQ45
AK33
DATA_B45
4
DATA_A48
AD31
AG30
DATA_B46
4
DATA_A49
AD35
SADQ48
SADQ49
SBDQ46
SBDQ47
AG27
DATA_B47
DATA_A50
Y33
AF27
DATA_B48
SCKE_A[0..3]18,20
DATA_A51
W34
SADQ50
SADQ51
SBDQ48
SBDQ49
AE27
DATA_B49
DATA_A52
AE35
SADQ52
SBDQ50
AC26
DATA_B50
DATA_A53
AE34
SADQ53
SBDQ51
AB26
DATA_B51
SCKE_B[0..3]19,20
DATA_A54
AA32
SADQ54
SBDQ52
AE31
DATA_B52
DATA_A55
Y35
SADQ55
SBDQ53
AE29
DATA_B53
DQM_A[0..7]18
DATA_A56
V34
SADQ56
SBDQ54
AC28
DATA_B54
DATA_A57
V33
AB27
DATA_B55
DATA_A58
R32
SADQ57
SADQ58
SBDQ55
SBDQ56
AA28
DATA_B56
DQM_B[7..0]19
DATA_A59
R34
W29
DATA_B57
DATA_A60
W35
SADQ59
SADQ60
SBDQ57
SBDQ58
V28
DATA_B58
DATA_A61
W33
SADQ61
SBDQ59
V29
DATA_B59
DATA_A62
T33
SADQ62
SBDQ60
Y26
DATA_B60
DATA_A63
T35
SADQ63
SBDQ61
AA29
DATA_B61
SCKE_A0
SBDQ62
W26
DATA_B63
DATA_B62
AP19
SACKE0
SBDQ63
U26
SCKE_A1
AM18
SACKE1
SCKE_A2
AN18
SACKE2
SBCKE0
AP10
SCKE_B0
SCKE_A3
AR19
SACKE3
SBCKE1
AN10
SCKE_B2
SCKE_B1
SBCKE2
AR9
3
DQM_A0
AF2
SADM0
SBCKE3
AM9
SCKE_B3
3
2
DQM_A6
DQM_A1
DQM_A4
DQM_A2
DQM_A7
DQM_A3
DQM_A5
AL1
AN7
AH16
AK29
AG34
AA33
U33
SADM1
SADM2
SADM3
SADM4
SADM5
SADM6
SADM7
SBDQS0#
SBDQS1#
SBDQS2#
SBDQS3#
SBDQS4#
SBDQS5#
SBDQS6#
SBDQS7#
SBDDR1MA13
SBRCVENOUT#
SBRCVENIN#
SMSLEWIN1
SMSLEWOUT1
SMVREF1
SBDM1
SBDM2
SBDM3
SBDM4
SBDM5
SBDM6
SBDM7
AJ5
AH9
W31
AH13
AH31
AD24
AG20
AG24
DQM_B2
DQM_B3
DQM_B1
DQM_B7
DQM_B6
DQM_B5
DQM_B0
DQM_B4
AN33
SBCS0#
AM34
SBCS1#
AP34
SBCS2#
AN34
SBCS3#
AN17
SBRAS#
AP18
SBCAS#
AP17
SBWE#
AM15
SBMA0
AR15
SBMA1
AN15
SBMA2
AL15
SBMA3
AP14
SBMA4
AM12
SBMA5
AP13
SBMA6
AL12
SBMA7
AN13
SBMA8
AR12
SBMA9
AP15
SBMA10
AP11
SBMA11
AR11
SBMA12
AL33
SBMA13
AM33
SBODT0
AL34
SBODT1
AL35
SBODT2
AK34
SBODT3
AR16
SBBA0
AN16
SBBA1
AN11
SBBA2
AK5
SBDQS0
AL4
AK10
SBDQS1
AH10
AK13
SBDQS2
AL14
AD20
SBDQS3
AF20
AH25
SBDQS4
AG26
AH28
SBDQS5
AH30
AB31
SBDQS6
AC30
W27
SBDQS7
Y28
AH22
SBCK0
AG23
SBCK0#
AK9
SBCK1
AL9
SBCK1#
AE26
SBCK2
AE25
SBCK2#
AL23
SBCK3
AK22
SBCK3#
AJ11
SBCK4
AL11
SBCK4#
AD28
SBCK5
AD29
SBCK5#
AD32
AK15
AN14
AF9
AE10
AE8
SBDM0
INTEL-82915-G-C2-LF
VCC_DDR
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
ODT_B0
ODT_B1
ODT_B2
ODT_B3
SBS_B0
SBS_B1
SBS_B2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B
SM_YSLEWIN
MCH_VREF_B
R252 1 KR1%
Title
Size Document Number Rev
Date: Sheet of
SCS_B#[0..3] 19,20
RAS_B# 19,20
CAS_B# 19,20
WE_B# 19,20
MAA_B[0..13] 19,20
ODT_B[0..3] 19,20
SBS_B0 19,20
SBS_B1 19,20
SBS_B2 19,20
DQS_B0 19
DQS_B#0 19
DQS_B1 19
DQS_B#1 19
DQS_B2 19
DQS_B#2 19
DQS_B3 19
DQS_B#3 19
DQS_B4 19
DQS_B#4 19
DQS_B5 19
DQS_B#5 19
DQS_B6 19
DQS_B#6 19
DQS_B7 19
DQS_B#7 19
P_DDR0_B 19
N_DDR0_B 19
P_DDR1_B 19
N_DDR1_B 19
P_DDR2_B 19
N_DDR2_B 19
P_DDR3_B 19
N_DDR3_B 19
P_DDR4_B 19
N_DDR4_B 19
P_DDR5_B 19
N_DDR5_B 19
PLACE 0.1UF CAP CLOSE TO MCH
C333
C0.1U50Y
CP15
X_COPPER
R257 X_0R
R267
1KR1%
MSI
MICRO-STAR INt'L CO., LTD.
Intel Grantsdale - Memory Signals
2
MCH_VREF_A
MS-7062
1
MCH_VREF_B
933Thursday, March 02, 2006
1
20A
5
4
3
2
1
V_1P5_CORE
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AC10
AC9
AC8
AC7
AC6
AC5
AC4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
E19
E20
C22
D22
D21
D20
D19
C21
CP10
12
X_COPPER
L11 X_10U100m_0805
C271
X_C10U10Y0805
CP13
12
X_COPPER
L15 X_10U100m_0805
C291
X_C10U10Y0805
4
AC3
VCC
VTT
C20
D D
EXP_A_RXP_1021
EXP_A_RXN_1021
EXP_A_RXP_1121
EXP_A_RXN_1121
EXP_A_RXP_1221
EXP_A_RXN_1221
EXP_A_RXP_1321
EXP_A_RXN_1321
EXP_A_RXP_1421
EXP_A_RXN_1421
EXP_A_RXP_1521
C C
B B
A A
EXP_A_RXN_1521
CK_PE_100M_MCH15
CK_PE_100M_MCH#15
SDVO_CTRL_DATA21
SDVO_CTRL_CLK21
V_2P5_DAC_FILTERED24
V_1P5_CORE V_1P5_CORE V_1P5_CORE
EXP_A_RXP_0
EXP_A_RXP_021
EXP_A_RXN_0
EXP_A_RXN_021
EXP_A_RXP_1
EXP_A_RXP_121
EXP_A_RXN_1
EXP_A_RXN_121
EXP_A_RXP_2
EXP_A_RXP_221
EXP_A_RXN_2
EXP_A_RXN_221
EXP_A_RXP_3
EXP_A_RXP_321
EXP_A_RXN_3
EXP_A_RXN_321
EXP_A_RXP_4
EXP_A_RXP_421
EXP_A_RXN_4
EXP_A_RXN_421
EXP_A_RXP_5
EXP_A_RXP_521
EXP_A_RXN_5
EXP_A_RXN_521
EXP_A_RXP_6
EXP_A_RXP_621
EXP_A_RXN_6
EXP_A_RXN_621
EXP_A_RXP_7
EXP_A_RXP_721
EXP_A_RXN_7
EXP_A_RXN_721
EXP_A_RXP_8
EXP_A_RXP_821
EXP_A_RXN_8
EXP_A_RXN_821
EXP_A_RXP_9
EXP_A_RXP_921
EXP_A_RXN_9
EXP_A_RXN_921
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_012
DMI_ITN_MRN_012
DMI_ITP_MRP_112
DMI_ITN_MRN_112
DMI_ITP_MRP_212
DMI_ITN_MRN_212
DMI_ITP_MRP_312
DMI_ITN_MRN_312
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
V_1P5_CORE
V_2P5_MCH
CP11
12
X_COPPER
L12 X_10U100m_0805
C294
X_C0.22U16Y
CP12
12
X_COPPER
L14 X_10U100m_0805
X_C10U10Y0805
5
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
NOA_0
NOA_1
NOA_2
NOA_5
NOA_6
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
C283
E11
F11
J11
H11
F9
E9
F7
E7
B3
B4
D5
E5
G6
G5
H8
H7
J6
J5
K8
K7
L6
L5
P10
R10
M8
M7
N6
N5
P7
P8
R6
R5
U5
U6
T9
T8
V7
V8
V10
U10
A11
B11
K13
J13
H16
E15
D17
M16
F15
C15
A16
B15
C14
K15
L10
M10
A17
B17
A12
B13
A14
A13
E13
D13
F13
INTEL-82915-G-C2-LF
V_FSB_VTT5,6,8,14,15,28
VCCA_MPLL
C280
X_C10U10Y0805
VCCA_DPLLB
C290
C0.1U50Y
U15C
EXPARXP0
EXPARXN0
EXPARXP1
EXPARXN1
EXPARXP2
EXPARXN2
EXPARXP3
EXPARXN3
EXPARXP4
EXPARXN4
EXPARXP5
EXPARXN5
EXPARXP6
EXPARXN6
EXPARXP7
EXPARXN7
EXPARXP8
EXPARXN8
EXPARXP9
EXPARXN9
EXPARXP10
EXPARXN10
EXPARXP11
EXPARXN11
EXPARXP12
EXPARXN12
EXPARXP13
EXPARXN13
EXPARXP14
EXPARXN14
EXPARXP15
EXPARXN15
DMI RXP0
DMI RXN0
DMI RXP1
DMI RXN1
DMI RXP2
DMI RXN2
DMI RXP3
DMI RXN3
GCLKINP
GCLKINN
SDVOCTRLDATA
SDVOCTRLCLK
BSEL0
BSEL1
BSEL2
RSVRD
RSVRD
MTYPE
EXP_SLR
RSVRD
RSVRD
RSVRD
DREFSSCLKINP
DREFSSCLKINN
VCCAHPLL
VCCAMPLL
VCCADPLLA
VCCADPLLB
VCCA3GPLL
VCCHV
VCCACRTDAC
VCCACRTDAC
VSSACRTDAC
C285
C0.1U50Y
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
F22
F21
F20
E22
E21
H22
G22
G21
V_1P5_COREV_1P5_CORE
AD10
AB4
AB9
AB8
AB7
AB6
AB5
VCC
VTT
AC1
VCC
VTT
B22
AB10
VCC
VCC
VTT
VTT
B21
B20
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
B19
A22
A21
A20
VCCA_DPLLA
C281
C0.1U50Y
VCCA_HPLL
C292
C0.1U50Y
AB3
VCC
VTT
A19
AC2
VCC
VTT
C19
VCC
AB2
AB1
VCC
VCC
VSSNCTF
AC25
W18
V19
VCC
VSSNCTF
AB25
AA25
U18
V17
VCC
VCC
VSSNCTF
VSSNCTF
Y25
AA11
VCC_DDR
AR33
VCC
VCCSM
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
Y18
Y11
W25
V_1P5_CORE
AR26
AR31
VCCSM
VCCSM
VSSNCTF
VSSNCTF
V25
W11
AR22
AR18
VCCSM
VSSNCTF
V20
V16
AR14
VCCSM
VSSNCTF
V11
AP28
AM28
AR10
AP24
AP20
AP16
AN35
AM32
AP12
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
T25
T18
T11
P25
P11
U25
U11
R25
R11
CP30
X_COPPER
L17 X_10U100m_0805
X_C10U10Y0805
CP14
12
X_COPPER
L16 X_10U100m_0805
3
AM26
AM25
VCCSM
VCCSM
VSSNCTF
VSSNCTF
N25
AD25
AM23
AM22
VCCSM
VCCSM
VSSNCTF
VSSNCTF
N11
M11
12
C328
AM20
VCCSM
VCCSM
VSSNCTF
VSSNCTF
AA15
AM19
AM11
AM10
AM17
AM16
AM14
AM13
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
P16
P18
P20
N17
N19
AA17
AA19
VCCA_GPLL
C317
C0.1U50Y
V_1P5_PCIEXPRESS
C313
C10U10Y0805
C316
X_C10U10Y0805
AK35
VCCSM
VSSNCTF
VSSNCTF
R17
R19
W1
VSSNCTF
T22
R21
VSSNCTF
VSSNCTF
U15
U21
V_2P5_MCH
VSSNCTF
VSSNCTF
V22
U23
VSSNCTF
VSSNCTF
VSSNCTF
W15
W21
VSSNCTF
VSSNCTF
Y22
W23
L10 X_0.1U50m
VCC3GY9VCC3GY8VCC3GY7VCC3GY6VCC3GY5VCC3GY4VCC3GY3VCC3GY2VCC3GY1VCC3GW9VCC3GW8VCC3GW7VCC3GW6VCC3GW4VCC3GW3VCC3GW2VCC3G
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
EXPATXP8
EXPATXN8
EXPATXP9
EXPATXN9
EXPATXP10
EXPATXN10
EXPATXP11
EXPATXN11
EXPATXP12
EXPATXN12
EXPATXP13
EXPATXN13
EXPATXP14
EXPATXN14
EXPATXP15
EXPATXN15
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
EXPACOMPO
EXPACOMPI
CRTHSYNC
CRTVSYNC
CRTRED
CRTGREEN
CRTBLUE
CRTREDB
CRTGREENB
CTRBLUEB
CRTDDCDATA
CRTDDCCLK
DREFCLKINP
DREFCLKINN
CRTIREF
PMEXTTS
PMBMBUSY#
TESTIN#
MCHDETECT
CP31
12
X_COPPER
V_1P5_PCIEXPRESS
C10
C9
A9
A8
C8
C7
A7
A6
C6
C5
C2
D2
E3
F3
F1
G1
G3
H3
H1
J1
J3
K3
K1
L1
L3
M3
M1
N1
N3
P3
P1
R1
R3
T3
T1
U1
U3
V3
V5
W5
Y10
W10
E12
D12
F14
D14
H14
G14
E14
J14
L14
M15
M13
M12
A15
K16
G16
R35
A35
V_2P5_DAC_FILTERED
C282
C10U10Y0805
2
EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
GRCOMP
HSYNC
VSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
MCH_DDC_DATA
MCH_DDC_CLK
CK_96M_DREF
CK_96M_DREF#
DACREFSET
EXTTS
1
1
C272
C0.01U50X
V_1P5_CORE
EXP_A_TXP_0 21
EXP_A_TXN_0 21
EXP_A_TXP_1 21
EXP_A_TXN_1 21
EXP_A_TXP_2 21
EXP_A_TXN_2 21
EXP_A_TXP_3 21
EXP_A_TXN_3 21
EXP_A_TXP_4 21
EXP_A_TXN_4 21
EXP_A_TXP_5 21
EXP_A_TXN_5 21
EXP_A_TXP_6 21
EXP_A_TXN_6 21
EXP_A_TXP_7 21
EXP_A_TXN_7 21
EXP_A_TXP_8 21
EXP_A_TXN_8 21
EXP_A_TXP_9 21
EXP_A_TXN_9 21
EXP_A_TXP_10 21
EXP_A_TXN_10 21
EXP_A_TXP_11 21
EXP_A_TXN_11 21
EXP_A_TXP_12 21
EXP_A_TXN_12 21
EXP_A_TXP_13 21
EXP_A_TXN_13 21
EXP_A_TXP_14 21
EXP_A_TXN_14 21
EXP_A_TXP_15 21
EXP_A_TXN_15 21
DMI_MTP_IRP_0 12
DMI_MTN_IRN_0 12
DMI_MTP_IRP_1 12
DMI_MTN_IRN_1 12
DMI_MTP_IRP_2 12
DMI_MTN_IRN_2 12
DMI_MTP_IRP_3 12
DMI_MTN_IRN_3 12
HSYNC 24
VSYNC 24
VGA_RED 24
VGA_GREEN 24
VGA_BLUE 24
MCH_DDC_DATA 24
MCH_DDC_CLK 24
CK_96M_DREF 15
CK_96M_DREF# 15
R237 255R1%
R227 10KR
V_2P5_MCH
TP3
TP2
H_FSBSEL05,6,15
H_FSBSEL15,6,15
H_FSBSEL25,6,15
C273
C0.01U50X
V_1P5_PCIEXPRESS
MICRO-STAR INt'L CO., LTD.
MSI
Title
Intel Grantsdale PCI-Express & RBG Signals
Size Document Number Rev
Date: Sheet of
MCH MEMORY DECOUPLING
V_FSB_VTT
C311
C0.1U50Y
FSB GENERIC DECOUPLING
H_FSBSEL0
H_FSBSEL1
BSEL
2
0
1
0
0
1
0
1
0
MS-7062
VCC_DDR
VCC_DDR
C310
C0.1U50Y
R214 10KR
R215 10KR
R220 10KR
R213 1 KR1%
R221 1 KR1%
PSB FREQUENCY
133 MHZ (533)
200 MHZ (800)
R245 24.9R1%
1
TABLE
C331
X_C10U10Y0805
C326
C10U10Y0805
C351
C10U10Y0805
C363
C10U10Y0805
C355
C68P50N
C370
C10U10Y0805
C371
C68P50N
C376
C10U10Y0805
C308
C0.1U50Y
10 33Thursday, March 02, 2006
NOA_0
NOA_1
NOA_2H_FSBSEL2
NOA_5
NOA_6
GRCOMP
20A
Loading...