MSI MS-7056 Schematics
5
4
3
2
1
MS-7056
VIA (R) K8M800(8380) / VT8237CD Chipset
Version 0A 01/02/2004 0A
Release
AMD PGA 754 Processor Schematics
D D
*AMD PGA 754 Processor
*VIA K8M800 / VT8237CD Chipset
(DDR 400 / AGP 8X / VLink 8X)
*W83697HF LPC I/O
*RT8110S/RT8100C
*VT6307 1394A Controler
*AC'97 Codec CMI9761A+ Codec
*BLUE BIRD VL+
*EQ PT2389 & SRS TA2136N
*USB 2.0 support (integrated into VT8237)
C C
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 1
*MINI PCI SLOT * 1
*DDR DIMM * 2
B B
M:K8M800 L:LANS:8237CD F:1394A
Orcad Config ERP BOM
A A
Function Description
GL:Giga-LAN
MS-7056 Ver:0A
Giga-LAN BOM (with Giga-LAN)
K8M800
8237CD
SMT5010
SMT5020
Blue Bird
10/100 LAN BOM (with 10/100 LAN)
K8M800
8237CD
SMT5010
SMT5020
Blue Bird
MCE BOM (with Giga-LAN)
K8M800
8237CD
MCE BOM (with 10/100 LAN)
K8M800
8237CD
SMT5010
SMT5020
SMT5010
SMT5020
B:Blue Bird
DIP
Total
DIP
Total
DIP
Total
DIP
Total
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Create
Date.
Title Page
Cover Sheet 1
Block Diagram
Clock Synthesizer ICS950403 7
System Memory
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8M800(HT)
VGA Connector / TV-OUT
SB VT8237CD
PCI Connectors / Mini-PCI
1394a Controller VT6307
FAN / LM90 / MDC
ATA 66/100/133
RealTek RTL8100C/8110S
Front & Rear USB Port
W83627THF / KB / MS
PowerOK Circuit / Front Panel
K8 Vcore power
ACPI Power MS6
System Voltage Regulator
IDE2 / Blue Bird VL+
AC97 Codec / Audio Connector
Audio EQ / SRS / Connector
BULK / Decoupling 33
Power Generation
Screw Hole / FMark
History
Manual Parts
DDR DIMM 1 & 2 8
2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket
9
10
11,12,13
14AGP SLOT 8X
15
16,17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
Cover Sheet
MS-7056
1
1 37Tuesday, February 17, 2004
0A
5
Block
4
3
2
1
Diagram
D D
AMD K8
Socket 754
DDR
Audio Signal
Control Signal
HyperTransfer
AGP 8X /Fast Write
AGP
1394a * 2
C C
PCI 1
MINI PCI
PCI Bus
VIA
K8T400M
K8M400
VLINK
R,G,B,HSYNC,VSYNC
R,G,B,HSYNC,VSYNC
MII Interface
Primary ATA 100/133
IDE1
B B
Video In
VIA
VT8237
VT8237 S-ATA
SATA Connector
DDR * 2
VGA Connector
S-Video Out
10/100 BaseT
Lan
Keyboard
Mouse
FM Tuner
NS952M
Secondry
ATA 100/133
Phone In
4
IDE2
AC'97 Link
MDC Modem
Blue Bird VL+
T-Board
AUX In
Cent / LFT MIC IN SPDIF INLine IN SPDIF OUTFNT MIC
A A
SurrondLine Out
EQ PT2389SRS TA2136
5
AC'97 Codec
AC'97 Link
Secondry ATA 100/133
AC'97 Link
3
USB
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *2 ,
Back-Port *4,
Card Reader, Dual
OS
LPC BUS
LPC BUS
2
ROM
SUPER I/O
47LM292
Hardware
Monitor
FAN
Control
Serial
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
Block Diagram
MS-7056
1
2 37Tuesday, February 17, 2004
0A
5
4
3
2
1
VT8237 GPIO Function Define
PIN NAME Function define
GPO0 (VSUS33)
GPO1 (VSUS33)
GPO2/SUSA#(VSUS33)
D D
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/GNT5
GPO8/GPI8/VGATE
GPO9/UDPWREN#
GPO10/GPI10/APICD0
GPO11/GPI11/APICD1
GPO12/GPI12/INTE#
C C
GPO13/GPI13/INTF#
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
Default
GPO0
GPO1
SUSA#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPI8
UDPWREN#
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
SUSLED ( Power LED )
5V_STR Control on S5
SUSA#
SUSST#
NA
NA
NA
NA
NA
JBAT1
NA
NA
INTE#
INTF#
MP_SB_INT
MD_SB_VMODE
Pull up / downFunction
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
PIN NAME
GPI1 (VSUS33)
GPI2/EXTSMI#
(VSUS33)
GPI3/RING#
(VSUS33)
GPI4/LID#
(VSUS33)
GPI5/BATLOW#
(VSUS33)
GPI6/AGPBZ#
GPI7/REQ5#
GPI9/UDPWR UDPWR
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPO20/GPI20/ACSDIN2
/PCS0#
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/GHI#
B B
ACSDIN2
ACSDIN3
GPO23/GPI23/DPSLP#
GPO24/GPI24
/PCREQA/STRAP
GPO25/GPI25/GPIOB
/PCREQB/STRAP
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
VIDSEL/SATALED#
GPO29/GPI29/
VRDSLP
GPO30/GPI30/GPIOC
/PCGNTA/STRAP
GPO31/GPI31/GPIOD
/PCGNTB/STRAP
A A
GPI24
GPI25
SMBDT2
SMBCK2
GPI30
GPI31
5
NA
NA
NA
BB_INTR#
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
SIO_SMI#
NA
NA
J1B2/GP11/P17
J2B1/GP12/WDT
J2B2/GP13/DS1#
MIDI_OUT/GP26 BIOS_DIS
Pull up to 3VDUAL
Pull up to 3VDUAL
DEVICES
PCI SLOT
Mini PCI
SLOT
1394 INT#C
GLAN
4
3
Default
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
NA Pull up to VBATGPI0 (VBAT)
ATADET0=>Detect IDE1 ATA100/66
CD_SMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
NA
SIO_PME# Pull up to VCC3
GPI7
INTRUDER#
CPUMISS
AOLGP1
IORDY
NA
INTRUDER#
NA
THERM_ALERT#
NAGPI19/APICCLK
SIO GPIO Function Define
Default
Function Pull up / downFunction definePIN NAME
BIOS_VER1
BIOS_VER2
BIOS_VER3
PCI Routing
2
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3 1394_PCLKAD18
PREQ#4
PGNT#4INT#D
Title
Size Document Number Rev
Date: Sheet of
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
IDSEL
AD16
AD17
AD19
Pull up / downFunction defineFunction
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VBAT
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
CLOCK
PCICLK1
PCICLK2
GLAN_PCLK
MICRO-STAR INt'L CO., LTD.
MSI
GPIO Spec
MS-7056
0A
37Tuesday, February 17, 2004
3
1
5
4
3
2
1
C469
X_102P
VREF routed as 40~50 mils trace wide ,
Space>25 mils
D D
DDR_VREF8
VDD_25_SUS
Place near CPU in 1" , Routed => 5:10/Trace:Space
, Same Length
MD[63..0]10
C C
B B
DDR_VREF
R178 15RST
R177 15RST
AMD Suggest change to 34.8Ohm
MEMDM[7..0]10
-MDQS[7..0]10
A A
5
C132
X_102P
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
AE13
AG12
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
AH13
AJ13
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
A13
AA1
AG1
AH7
A14
AB1
AJ2
AJ8
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
U21B
RSVD_MEMADDA15
RSVD_MEMADDA14
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
-MCS3 8,9
-MCS2 8,9
-MCS1 8,9
-MCS0 8,9
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBANKB1 8,9
MEMBANKB0 8,9
LAYOUT: Locate close to Clawhammer socket.
VTT_DDR_SUS
C460
MCKE0 8,9
MCKE1 8,9
MEMCLK_H[7..0] 8,9
MEMCLK_L[7..0] 8,9
C458
GND
CADIP[0..15]11
CADIN[0..15]11
0.22U16Y
X_10U10Y1206
MAA[13..0] 8,9
CLKIP111
CLKIN111
CLKIP011
CLKIN011
VLDT0
R445 49.9RST
CTLIP011
CTLIN011
R447 49.9RST
MAB[13..0] 8,9
VTT_DDR_SUSVDD_25_SUS
C271
0.1U25Y
C283
X_0.1U25Y
C309
0.1U25Y
3
C497
VDD_12_A
0.22U16Y
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP1
CADIP0
CTLIP1
CTLIN1
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
T27
T28
V29
U29
V27
V28
Y29
Y25
Y27
Y28
R27
R26
T29
R29
VDD_12_A
C493
X_0.22U16Y
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
2
C494
X_0.22U16Y
U21A
HYPER TRANSPORT - LINK0
VCORE
C495
0.22U16Y
C496
1U10Y
C492
X_0.1U25Y_B
C189
X_0.1U25Y
VDD_12_A
VLDT0
AH29
VLDT0_B6
AH27
VLDT0_B5
AG28
VLDT0_B4
AG26
VLDT0_B3
AF29
VLDT0_B2
AE28
VLDT0_B1
AF25
VLDT0_B0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
MSI
Title
Size Document Number Rev
Date: Sheet of
CADOP15
N26
CADON15
N27
CADOP14
L25
CADON14
M25
CADOP13
L26
CADON13
L27
CADOP12
J25
CADON12
K25
CADOP11
G25
CADON11
H25
CADOP10
G26
CADON10
G27
CADOP9
E25
CADON9
F25
CADOP8
E26
CADON8
E27
CADOP7
N29
CADON7
P29
CADOP6
M28
CADON6
M27
CADOP5
L29
CADON5
M29
CADOP4
K28
CADON4
K27
CADOP3
H28
CADON3
H27
CADOP2CADIP2
G29
CADON2
H29
CADOP1
F28
CADON1
F27
CADOP0
E29
CADON0
F29
CLKOP1
J26
CLKON1
J27
CLKOP0
J29
CLKON0
K29
N25
P25
CTLOP0
P28
CTLON0
P27
MICRO-STAR INt'L CO., LTD.
K8 DDR & HT
MS-7056
C463
4.7U10Y0805
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
1
VLDT0 5
CADOP[0..15] 11
CADON[0..15] 11
4 37Tuesday, February 17, 2004
0A
5
4
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
D D
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
VDDA_25
C153
CPU_VDDA_25
C158
4.7U10Y0805
C159
392P
C462
0.22U16Y
FB22 180nH-1210-450mA
10U6.3X0805
VCCA_PLL regulator circuit.
VCC2_5
R205
X_1KR
C501
X_10U10Y1206
Near MS6,
Remove this two
components in 0B
THRMTRIP# 21,26,28
AH25
C166
X_102P
CPU_GD28
C C
-LDTSTOP
PS_ON#A26
B B
HDT Connectors
DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI
NC_AJ18
NC_AH18
NC_AG18
NC_AG17
NC_C19
A A
NC_D18
NC_D20
NC_B19
NC_C21
PS_ON#A
R149
Q21
2N7002
R147 1KR
R148 1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R174 1KR
5
1KR
VCC2_5
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
02/06 ADD close to CPUCLK0_H/L
into CPU side.
RN44
8P4R-1KR
VCC2_5
RN14
8P4R-1KR
8P4R-1KR
RN43
VLDT04
VCORE
VLDT0
R444 44.2RST
R443 44.2RST
C555
X_0.1U25Y
8/28 AMD CHANGE THE PULL-UP POWER
4
C465
102P
VDD_25_SUS
C468
X_102P
102P
C464
-CPURST26
-LDTSTOP11,18
COREFB_H27
COREFB_L27
Differential , "10:10:5:10:10" .
CPUCLK0_H7
Near CPU in 0.5" .
CPUCLK0_L7
VDDIO_SENSE
C164 392P
C165 392P
VTT_DDR_SUS
VCC2_5
3
CPU_GD
L0_REF1
L0_REF0
VDDIO_SENSE
169RST
R150
R143 820RST
R141 820RST
R176 1KR
R175 1KR
1 2
3 4
5 6
7 8
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN16
8P4R-1KR
CLKIN_H
CLKIN_L
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AE21
AA2
AG2
B18
AH1
C20
AG4
AG6
AE9
AG9
A23
A24
B23
C16
C15
E20
E17
B21
A21
C18
A19
A28
C1
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
J3
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U21C
G_FBCLKOUT_H
G_FBCLKOUT_L
2
THERMTRIP_L
THERMDA
THERMDC
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
THRMTRIP_K8#
A20
THERMDA_CPU
A26
A27
VID4
AG13
VID4
VID3
AF14
VID3
VID2
AG14
VID2
VID1
AF15
VID1
VID0
AE15
VID0
TDO
NC_AG18
AG18
NC_AH18
AH18
NC_AG17
AG17
NC_AJ18
AJ18
FBCLKOUT_H
AH19
AJ19
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
AE19
NC_D20
D20
NC_C21
C21
NC_D18
D18
NC_C19
C19
NC_B19
B19
TDO
A22
AF18
D22
C22
VID0
VID2
VID1
VID3
B13
B7
C3
VID4
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
MSI
Title
Size Document Number Rev
Date: Sheet of
TP16
1
.
THERMDA_CPU 21
VID[4..0] 27
LAYOUT: Route
FBCLKOUT_H/L differentially
R151
with 20/8/5/8/20 spacing and
80.6RST
trace width. ( In CPU
breakout => routed 5:5:5 )
8/28 AMD CHANGE THE PULL-UP POWER
VDD_25_SUS
R173 1KR
VCC2_5
RN18
7 8
5 6
3 4
1 2
X_8P4R-4.7K
R146 X_4.7KR
MICRO-STAR INt'L CO., LTD.
K8 HDT & MISC
MS-7056
1
R448 0R
C155
0.1U25Y
THERMDC_CPU 21
5
0A
37Tuesday, February 17, 2004
5
4
3
2
1
U21E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
D D
C C
B B
A A
VSS9
D2
VSS10
AF2
VSS11
W6
VSS12
Y7
VSS13
AA8
VSS14
AB9
VSS15
AA10
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
AE16
VSS20
J18
VSS21
G20
VSS22
R20
VSS23
U20
VSS24
W20
VSS25
AA20
VSS26
AC20
VSS27
AE20
VSS28
AG20
VSS29
AJ20
VSS30
D21
VSS31
F21
VSS32
H21
VSS33
K21
VSS34
M21
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
AD21
VSS40
AG21
VSS41
B22
VSS42
E22
VSS43
G22
VSS44
J22
VSS45
L22
VSS46
N22
VSS47
R22
VSS48
U22
VSS49
AG29
VSS50
AA22
VSS51
AC22
VSS52
AG22
VSS53
AH22
VSS54
AJ22
VSS55
D23
VSS56
F23
VSS57
H23
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
AB23
VSS64
AD23
VSS65
AG23
VSS66
E24
VSS67
G24
VSS68
J24
VSS69
N24
VSS70
R24
VSS71
U24
VSS72
W24
VSS73
AA24
VSS74
AC24
VSS75
AG24
VSS76
AJ24
VSS77
B25
VSS78
C25
VSS79
B26
VSS80
D26
VSS81
H26
VSS82
M26
VSS83
T26
VSS84
Y26
VSS85
AD26
VSS86
AF26
VSS87
AH26
VSS88
C27
VSS89
B28
VSS90
D28
VSS91
G28
VSS92
F15
VSS187
H15
VSS188
AB17
VSS206
AD17
VSS207
B16
VSS208
G18
VSS209
AA18
VSS210
AC18
VSS211
D19
VSS212
F19
VSS213
H19
VSS214
K19
VSS215
Y19
VSS216
AB19
VSS217
AD19
VSS218
AF19
VSS219
J20
VSS220
L20
VSS221
N20
VSS222
GND GND
5
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
GROUND
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
W21
AA21
AC21
AB22
AD22
W23
AA23
AC23
AB24
AD24
AH24
AE25
VCORE
C491
0.22U16Y
VCORE
C204
C188
10U10Y1206
10U10Y1206
C187
VCORE
C136
C193
0.22U16Y
X_22U10Y1206
LAYOUT: Place beside processor.
VDD_25_SUS
C470
0.22U16Y
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
U21D
L7
VDD1
VDD2
H18
VDD3
B20
VDD4
E21
VDD5
H22
VDD6
J23
VDD7
H24
VDD8
F26
VDD9
N7
VDD10
L9
VDD11
V10
VDD12
G13
VDD13
K14
VDD14
Y14
VDD15
VDD16
G15
VDD17
J15
VDD18
VDD19
H16
VDD20
K16
VDD21
Y16
VDD22
VDD23
G17
VDD24
J17
VDD25
VDD26
VDD27
VDD28
F18
VDD29
K18
VDD30
Y18
VDD31
VDD32
VDD33
VDD34
E19
VDD35
G19
VDD36
VDD39
VDD38
J19
VDD37
F20
VDD40
H20
VDD41
K20
VDD42
M20
VDD43
P20
VDD44
T20
VDD45
V20
VDD46
Y20
VDD47
VDD48
VDD49
G21
VDD50
J21
VDD51
L21
VDD52
N21
VDD53
R21
VDD54
U21
VDD55
VDD56
VDD57
VDD58
F22
VDD59
K22
VDD60
M22
VDD61
P22
VDD62
T22
VDD63
V22
VDD64
Y22
VDD65
VDD66
VDD67
E23
VDD68
G23
VDD69
L23
VDD70
N23
VDD71
R23
VDD72
U23
VDD73
VDD74
VDD75
VDD76
B24
VDD77
D24
VDD78
F24
VDD79
K24
VDD80
M24
VDD81
P24
VDD82
T24
VDD83
V24
VDD84
Y24
VDD85
VDD86
VDD87
VDD88
VDD89
K26
VDD90
P26
VDD91
V26
VDD92
POWER
EMI
C195
0.22U16Y
In CPU Cavity
C141
X_22U10Y1206
between VRM & CPU.
C471
C472
X_0.22U16Y
C474
0.22U16Y
C139
along VDD_CORE perimiter.
LAYOUT: Place 1 capacitor every 1-1.5"
VCORE
Place on CPU Solder side
C475
X_0.22U16Y
C476
C196
0.22U16Y
-
X_103P
X_10U10Y1206
C477
C197
0.22U16Y
C140
0.22U16Y
3
0.22U16Y
X_10U10Y1206
C483
0.22U16Y
X_0.22U16Y
C199
0.22U16Y
C147
10U10Y1206
VDD_25_SUS
C489
X_0.22U16Y
Place on inside of CPU Cavity ( 5 *
0.22uF/0603 X7R high-freq decoupling
Cap. )
C478
X_1U10Y
X_0.22U16Y
C479
C480
C481
X_0.22U16Y
X_0.22U16Y
C484
C482
X_0.22U16Y
CPU Solder Side Components.
LAYOUT: Place 6 EMI capsalong bottom right side of Clawhammer, 2 in middle
of HT link, and 12 along
C200
0.22U16Y
C148
C205
C202
0.22U16Y
GND
C149
10U10Y1206
10U10Y1206
GND
LAYOUT: Place 1000pF capacitors
0.22U16Y
LAYOUT: Place beside DDR slots.
1U10Y
1U10Y
C169
C490
GND
C182
0.1U25Y
0.22U16Y
C201
C210
bottom left side of Claw-
VCORE
X_1U10Y
C219
C213
X_1U10Y
VDD_25_SUS
C178
C176
4.7U10Y0805
2
C564
X_0.1U25Y
0.1U25Y
C222
Between DIMM and Socket
0.22U16Y
X_6.8P
C486
X_0.22U16Y
X_0.22U16Y
C485
hammer.
C565
X_0.1U25Y
C117
X_0.22U16Y
LAYOUT: Place beside DDR slots.
1U10Y
X_0.1U25Y
C226
C186
1U10Y
1U10Y
C247
C191
X_4.7U10Y0805
X_0.22U16Y
MSI
Title
Size Document Number Rev
Date: Sheet of
C274
C259
0.1U25Y
GND
4.7U10Y0805
C214
C216
0.22U16Y
MICRO-STAR INt'L CO., LTD.
K8 Power & GND
MS-7056
1
6 37Tuesday, February 17, 2004
0A
5
Clock Synthesizer
D D
CLKVCC3
C237 0.1U25Y
CLKVCC3
C262 0.1U25Y
CLKVCC3
R193 10KR
C231 0.1U25Y
CLKVCC3
C261 0.1U25Y
CLKVCC3
C260 0.1U25Y
C C
CLKVCC3
C241 0.1U25Y
CLKVCC3
C240 0.1U25Y
CLKVCC3
CLKVCC3
C239 0.1U25Y
B B
ModeA ModeB Pin6 Pin7
0
0 1
1
1 1
Input Configuration
FS2
0 0 01
0
1
1 0
0
0
1
0
0
0
0
A A
0
0
0
0
0
0 0
0
U22
46
47
2
5
32
33
9
10
16
15
19
20
29
30
27
38
39
35
34
43
42
0
0
VDD_46
VSS_47
VDD_2
VSS_5
PD
VSSF
VDD_9
VSS_10
VDD_16
VSS_15
VDD_19
VSS_20
VDD_29
VSS_30
VSS_27
VDD_38
VSS_39
VDD_35
VSS_34
VDDA
VSSA
ICS950403
HTTCLK0
HTTCLK0
HTTCLK0
HTTCLK0
ModeA/PCI33_HT66SEL
FS0/REF0
FS1/REF1
FS2/REF2
FS3/48MHZ
ModeB/PCI33_HT66_1
PCI33_HT66_2
PCI33_HT66_3
PCI33_10
24_48MHZ/SEL
HTTCLK1
HTTCLK1
PCICLK7 PCICLK8
HTTCLK1
Clock Generator Output
FS0
FS1FS2
CPU (MHz)
150
11 1
1
0111
200.40
166.70
133.50
0 0
1
10 168.00
0
1
0
0 0
5
202
133.90
100.90
XIN
XOUT
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_F
PCI33_4
PCI33_5
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
PCICLK6
RESET
VCC3
FS0
1
FS1
48
FS2
45
CLKX1
3
CLKX2
4
FS3
31
HT_66_0
7
HT_66_1
8
HT_66_2
11
12
13
14
17
18
23
21
22
SEL_24
28
SMBDATA1
26
SMBCLK1
25
41
40
37
36
-SEL_66
6
24
SPREAD
44
Pin8 Pin11
HTTCLK2
HTTCLK2
PCICLK8
C254
0.1U25Y
R201 10KR
R187 10KR
PCI33 (MHz)
33.33
33.33
33.33
33.33
36.56100.20
30.00
X1/6
X1/6
33.63
4
FB23 X_120L-0805-800mA
CP3
X_COPPER
R207 22R
R189 22R
R190 22R
X1 14.318MHZ
R194 33R
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
R195 33R
R191 15RST
R192 15RST
PCICLK9
HTTCLK3
PCICLK9
PCICLK9
PCI33_HT66 (MHz)
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
73.12
60.00
X1/6
X1/3
67.27
4
CLKVCC3
C255
0.1U25Y
SB_OSC14
GUICLK
APICCLK
56PC263
56PC264
VCLK
RN60
8P4R-22R
RN61
8P4R-22R
RN57
8P4R-22R
SER_24 Pin28
GCLK_SLOT
GCLK_NB
GLAN_PCLK
PCICLK1
PCICLK2
SIO_PCLK
BIOS_PCLK
1394_PCLK
SB_PCLK
SIO48M
SMBDATA1 8,17,21,23,28,30
SMBCLK1 8,17,21,23,28,30
CPUCLK0_H
CPUCLK0_L
FP_RST# 26,28,30
24MHz
1
48MHz
0
3
CPUCLK0_H
CPUCLK0_L
C245
4.7U10Y0805 R186 10KR
SB_OSC14 17
GUICLK 12
APICCLK 18
USBCLK_SB 16
VCLK 18
GCLK_SLOT 14
GCLK_NB 12
GLAN_PCLK 23
PCICLK1 19
PCICLK2 19
SIO_PCLK 25
BIOS_PCLK 25
1394_PCLK 20
SB_PCLK 18
SIO48M 25
CPUCLK0_H 5
CPUCLK0_L 5
SEL_24
FS3
FS2
FS1
FS0
FS3
FS2
FS1
FS0
HT_66_0
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
SB_OSC14
APICCLK
SB_PCLK
1394_PCLK
SIO_PCLK
PCICLK2
BIOS_PCLK
GLAN_PCLK
PCICLK1
C229 X_5P
C230 X_5P
R185 10KR
R182 X_10KR
R180 X_10KR
R200 X_10KR
R184 X_10KR
R183 10KR
R181 10KR
R206 10KR
R202 10KR
CN17
7 8
5 6
3 4
1 2
X_8P4C-10P
C232 10P
C242 10P
C270 X_10P
C238 X_10P
1 2
3 4
5 6
7 8
C272 X_10P
C279 X_10P
C280 X_10P
Comment
Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
ICS OverClock
ICS UnderClock
Bypass mode
Bypass mode
Tri-state mode
3
CLKVCC3
CN18
X_8P4C-10P
2
Signal
CPUCLK# / CPUCLK 20:5:5:5:20
GCLK_SLOT
GCLK_NB
VCLK
SB_PCLK
PCICLK[1:2]
SIO_PCLK
BIOS_PCLK
1394_PCLK
GLAN_PCLK
USBCLK_SB
SIO_14
SB_OSC14
APICCLK
GUICLK
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
Clock Trace
Clock
Synthesizer
Clock
Segment
Clock
Synthesizer
CPUT_1
CPUC_1
PCI33_HT66_2
PCI33_HT66_3
PCI33_HT66_1
PCI33_F
PCI33_1
PCI33_2
PCI33_3
PCI33_4
PCI33_5
2
LT
<0.5"
<1"
<1"
Title
Size Document Number Rev
Date: Sheet of
PCB LAYOUT GIUDE
Mismatch
10mil
<0.1"
<1"
<1"
R
Lcpu
Lcpu
L_slot
R C
L_slot+4"(L_NB)
RRC
L_slot+4"(L_SB)
C
L1+3"
R C
R
R C
R
R
R C
L6(GLAN)
C
L1(PCI)
L2(MiniPCI)
C
L3(SIO)
C
L4(BIOS)
L5(1394)
R C
MSI
MICRO-STAR INt'L CO., LTD.
Length RangeW : S
1" - 9"
1" - 8"
5" - 12"
5" - 12"
4" - 15"
1" - 12"
4" - 15"
4" - 15"
4" - 15"
Minimum
50mils
C
CPUCLK0_H
CPUCLK0_L
The longest PCI CLK
Clock Synthesizer
MS-7056
1
Notes
Base on GCLK_SLOT + 4"
The longest PCICLK + 3"
Minimum
20mils
Socket
754
LT
<0.5"
CLKIN_H
CLKIN_L
AGP Slot
7 37Tuesday, February 17, 2004
CLK
K8M800 NB
CLK
VT8237 SB
VCLK
VT8237 SB
PCICLK
RTL8100CGLAN_PCLK
PCI-SLOT
Mini-PCI
47LM292
FWH BIOS
VT6307
GCLK_SLOT
GCLK_NB
VCLK
SB_PCLK
PCICLK1
PCICLK2
SIO_PCLK
BIOS_PCLK
1394_PCLK
1
0A
5
VDD_25_SUS
DDR_VREF
C137
0.1U25Y
DR_MD[63..0]
R239 4.7KR
-MSWEA4,9
C131
X_102P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
1
9
101
102
DR_MD[63..0]9,10
D D
C C
B B
Place 104p Cap. near the DIMM
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VDDQ1
VSS7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
SLAVE ADDRESS = 1010000B
NC4
VSS0
3111826344250586674818993
4
SYSTEM MEMORY
104
112
128
136
143
156
164
172
1801582
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
184
PIN
DDR DIMM
SOCKET
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
116
124
132
139
145
152
160
176
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
NC(RESET#)
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR1
DDR400-CH
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAA13
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
SMBCLK1
SMBDATA1
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
3
-MCS0 4,9
-MCS1 4,9
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
-DR_MDQS7 9,10
MAA[13..0]
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17,21,23,28,30
SMBDATA1 7,17,21,23,28,30
MEMCLK_H5 4,9
MEMCLK_L5 4,9
MEMCLK_H0 4,9
MEMCLK_L0 4,9
MEMCLK_H7 4,9
MEMCLK_L7 4,9
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
DR_MEMDM[7..0]
MAA[13..0] 4,9
Place 104p and 1000p
Cap. near the DIMM
VDD_25_SUS
R238 4.7KR
-MSWEB4,9
C127
0.1U25Y
DR_MEMDM[7..0] 9,10
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
DDR_VREF
C133
X_102P
2
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VDDQ2
VSS8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
VSS0
VSS1
3111826344250586674818993
104
112
128
136
143
156
164
172
1801582
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
184
PIN
DDR DIMM
SOCKET
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
100
116
124
132
139
145
152
160
176
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
SDA
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
BA0
BA1
BA2
SCL
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
157
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H4
16
MEMCLK_L4
17
MEMCLK_H1
137
MEMCLK_L1
138
MEMCLK_H6
76
MEMCLK_L6
75
173
10
21
111
65
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR2
DDR400-CH
-MCS2
-MCS3
MAB13
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
SMBCLK1
SMBDATA1
MCKE0
MCKE1
-MSCASB
-MSRASB
1
VDD_25_SUS
-MCS2 4,9
-MCS3 4,9
MAB[13..0] 4,9
MEMBANKB0 4,9
MEMBANKB1 4,9
MEMCLK_H4 4,9
MEMCLK_L4 4,9
MEMCLK_H1 4,9
MEMCLK_L1 4,9
MEMCLK_H6 4,9
MEMCLK_L6 4,9
-MSCASB 4,9
-MSRASB 4,9
VDD_25_SUS
A A
R136
1KRST
R135
1KRST
C142
0.1U25Y
DDR_VREF
C130
0.1U25Y
5
DDR_VREF 4
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
4
3
2
Date: Sheet of
DDR DIMM1 & 2
MS-7056
1
8 37Tuesday, February 17, 2004
0A
5
4
3
2
1
DDR Terminations
Ver:0B
VTT_DDR_SUS VTT_DDR_SUS
D D
DR_MD59
DR_MD63
DR_MD58
DR_MD62
-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61
DR_MD56
DR_MD60
DR_MD51
DR_MD55
DR_MD50
C C
B B
DR_MD54
-DR_MDQS6
DR_MEMDM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD49
DR_MD48
DR_MD47
DR_MD46
DR_MD43
DR_MD42
-DR_MDQS5
DR_MEMDM5
-MCS1
-MCS14,8
-MCS3
-MCS34,8
-MCS0
-MCS04,8
-MCS2
-MCS24,8
-MSCASB
-MSCASB4,8
-MSCASA
-MSCASA4,8
DR_MD41
DR_MD45
-MSWEB
-MSWEB4,8
-MSWEA
-MSWEA4,8
-MSRASB
-MSRASB4,8
-MSRASA
-MSRASA4,8
DR_MD44
R237 47R
RN68 8P4R-27R0402
7 8
5 6
3 4
1 2
RN66 8P4R-27R0402
7 8
5 6
3 4
1 2
RN64 8P4R-27R0402
7 8
5 6
3 4
1 2
RN62 8P4R-27R0402
7 8
5 6
3 4
1 2
RN59 8P4R-27R0402
7 8
5 6
3 4
1 2
RN56 8P4R-27R0402
7 8
5 6
3 4
1 2
RN54 8P4R-27R0402
7 8
5 6
3 4
1 2
RN52 8P4R-27R0402
7 8
5 6
3 4
1 2
RN50 8P4R-27R0402
7 8
5 6
3 4
1 2
RN49 8P4R-27R0402
7 8
5 6
3 4
1 2
MEMBANKB04,8
MEMBANKA04,8
MEMBANKB14,8
MEMBANKA14,8
DR_MD40
DR_MD35
DR_MD39
DR_MD38
DR_MD34
DR_MEMDM4
-DR_MDQS4
DR_MD37
DR_MD33
DR_MD36
DR_MD32
MAA10
MAB10
MAA0
MAB0
MAA1
MAB1
MAA2
MAB2
DR_MD31
DR_MD27
DR_MD26
DR_MD30
MAB3
MAA3
MAA4
MAB4
DR_MEMDM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
DR_MD24
MAB6
MAA6
MAA5
MAB5
DR_MD23
DR_MD19
VTT_DDR_SUS
RN47 8P4R-27R0402
7 8
5 6
3 4
1 2
RN45 8P4R-27R0402
7 8
5 6
3 4
1 2
RN42 8P4R-27R0402
7 8
5 6
3 4
1 2
RN40 8P4R-27R0402
7 8
5 6
3 4
1 2
RN39 8P4R-27R0402
7 8
5 6
3 4
1 2
RN38 8P4R-27R0402
7 8
5 6
3 4
1 2
RN37 8P4R-27R0402
7 8
5 6
3 4
1 2
RN35 8P4R-27R0402
7 8
5 6
3 4
1 2
RN34 8P4R-27R0402
7 8
5 6
3 4
1 2
RN31 8P4R-27R0402
7 8
5 6
3 4
1 2
RN29 8P4R-27R0402
7 8
5 6
3 4
1 2
-MCS2
-MCS24,8
MAA8
MAB8
DR_MD22
MAA7
MAB7
DR_MD18
DR_MEMDM2
MAB9
MAA9
MAB11
MAA11
DR_MD21
-DR_MDQS2
DR_MD17
MAB12
MAA12
DR_MD16
DR_MD20
MCKE04,8
MCKE14,8
DR_MD11
DR_MD10
DR_MD15
DR_MD14
DR_MEMDM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD7
DR_MD6
DR_MD2
-DR_MDQS0
DR_MEMDM0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
RN28 8P4R-27R0402
7 8
5 6
3 4
1 2
RN27 8P4R-27R0402
7 8
5 6
3 4
1 2
RN25 8P4R-27R0402
7 8
5 6
3 4
1 2
RN23 8P4R-27R0402
7 8
5 6
3 4
1 2
RN21 8P4R-27R0402
7 8
5 6
3 4
1 2
RN20 8P4R-27R0402
7 8
5 6
3 4
1 2
RN17 8P4R-27R0402
7 8
5 6
3 4
1 2
RN13 8P4R-27R0402
7 8
5 6
3 4
1 2
RN11 8P4R-27R0402
7 8
5 6
3 4
1 2
RN9 8P4R-27R0402
7 8
5 6
3 4
1 2
-MSCASB4,8
-MSCASA4,8
-MSRASB4,8
-MSRASA4,8
MEMBANKB14,8
MEMBANKA14,8
MEMBANKB04,8
MEMBANKA04,8
-MCS3
-MCS34,8
MAB13
MAA13
MAB12
MAA12
MAB11
MAA11
MAB1
MAA1
MAB3
MAA3
MAB2
MAA2
MAB6
MAA6
MAB4
MAA4
MAB8
MAA8
MAB5
MAA5
MAA0
MAA10
MAB0
MAB10
-MSCASB
-MCS0
-MCS04,8
-MSCASA
-MCS1
-MCS14,8
MAA9
MAB9
MAB7
MAA7
-MSRASB
-MSRASA
-MSWEB
-MSWEB4,8
-MSWEA
-MSWEA4,8
MCKE14,8
MCKE04,8
CN16
8P4C-10P
CN5
8P4C-10P
CN10
8P4C-10P
CN9
8P4C-10P
CN8
8P4C-10P
CN7
8P4C-10P
CN11
8P4C-10P
CN15
8P4C-10P
CN6
8P4C-10P
CN13
8P4C-10P
CN12
8P4C-10P
CN4
8P4C-10P
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
A A
MEMCLK_H5
MEMCLK_H4
MEMCLK_H7
MEMCLK_H6
MEMCLK_H1
MEMCLK_H0
120RST
C466 10P
C461 10P
C498 10P
C499 10P
C487 10P
C488 10P
5
MEMCLK_L5
MEMCLK_L4
MEMCLK_L7
MEMCLK_L6
MEMCLK_L1
MEMCLK_L0
MEMCLK_L[7..0]4,8
MEMCLK_H[7..0]4,8
-DR_MDQS[7..0]8,10
4
MEMCLK_L[7..0]
MEMCLK_H[7..0]
-DR_MDQS[7..0]
3
DR_MD19
DR_MD[63..0]8,10
MAB[13..0]4,8
MAA[13..0]4,8
DR_MEMDM[7..0]8,10
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]
2
Title
Size Document Number Rev
Date: Sheet of
DDR Terminations Part1
MS-7056
1
9 37Tuesday, February 17, 2004
0A
MICRO-STAR INt'L CO., LTD.
MSI
5
DDR Terminations
4
3
2
1
LAYOUT: Place on backside,
evenly spaced around VTT fill.
C180
C190
C206
C218
C223
C227
C236
C168
X_1U6Y0402
C235
X_1U6Y0402
VTT_DDR_SUS
C173
0.1U16Y0402
C243
0.1U16Y0402
12
EC28
+
CD470U10EL11.5
C175
1U6Y0402
X_0.1U16Y0402
C249
1U6Y0402
X_0.1U16Y0402
C256
0.1U25Y0402
C266
X_0.1U25Y0402
C275
X_0.1U25Y0402
C284
0.1U25Y0402
C293
X_0.1U25Y0402
C296
X_0.1U25Y0402
C305
X_0.1U25Y0402
C177
C253
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C134
X_0.1U25Y0402
C183
X_1U6Y0402
C265
X_1U6Y0402
C185
0.1U16Y0402
C276
0.1U16Y0402
C198
1U6Y0402
X_0.1U16Y0402
C288
1U6Y0402
X_0.1U16Y0402
C207
C292
C212
0.1U16Y0402
C302
0.1U16Y0402
C215
X_0.1U16Y0402
C304
1U6Y0402
X_0.1U16Y0402
1U6Y0402
C209
X_1U6Y0402
C295
X_1U6Y0402
VTT_DDR_SUS
D D
C C
B B
RN10 8P4R-10R
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN12 8P4R-10R
MEMDM0 DR_MEMDM0
1 2
-MDQS0
3 4
MD2
5 6
MD6
7 8
RN15 8P4R-10R
MD7
1 2
MD3
3 4
MD8
5 6
MD9
7 8
RN19 8P4R-10R
MD12
1 2
-MDQS1 -DR_MDQS1
3 4
MEMDM1 DR_MEMDM1
5 6
MD13 DR_MD13
7 8
RN22 8P4R-10R
MD14
1 2
MD15
3 4
MD10
5 6
MD11
7 8
RN26 8P4R-10R
MD21 DR_MD21
1 2
MEMDM2 DR_MEMDM2
3 4
MD18 DR_MD18
5 6
MD22 DR_MD22
7 8
RN24 8P4R-10R
MD20
1 2
MD16
3 4
-MDQS2
5 6
MD17
7 8
RN30 8P4R-10R
MD23
1 2
MD19 DR_MD19
3 4
MD24
5 6
MD28 DR_MD28
7 8
RN32 8P4R-10R
MD29
1 2
MD25
3 4
-MDQS3
5 6
MEMDM3 DR_MEMDM3
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
-DR_MDQS0
DR_MD2
DR_MD6
DR_MD7
DR_MD3
DR_MD8
DR_MD9
DR_MD12
DR_MD14
DR_MD15
DR_MD10
DR_MD11
DR_MD20
DR_MD16
-DR_MDQS2
DR_MD17
DR_MD23
DR_MD24
DR_MD29
DR_MD25
-DR_MDQS3
RN36 8P4R-10R
MD26
1 2
MD30
3 4
MD27
5 6
MD31
7 8
RN41 8P4R-10R
MD32
1 2
MD36
3 4
MD33
5 6
MD37
7 8
RN46 8P4R-10R
-MDQS4 -DR_MDQS4
1 2
MEMDM4 DR_MEMDM4
3 4
MD34 DR_MD34
5 6
MD38 DR_MD38
7 8
RN48 8P4R-10R
MD35 DR_MD35
1 2
MD39
3 4
MD40
5 6
MD44
7 8
RN51 8P4R-10R
MD45 DR_MD45
1 2
MD41
3 4
-MDQS5 -DR_MDQS5
5 6
MEMDM5 DR_MEMDM5
7 8
RN55 8P4R-10R
MD42 DR_MD42
1 2
MD43
3 4
MD46 DR_MD46
5 6
MD47
7 8
RN58 8P4R-10R
MD48 DR_MD48
1 2
MD49
3 4
MD52 DR_MD52
5 6
MD53 DR_MD53
7 8
RN63 8P4R-10R
MEMDM6
1 2
-MDQS6
3 4
MD54
5 6
MD50 DR_MD50
7 8
RN65 8P4R-10R
MD55
1 2
MD51
3 4
MD60
5 6
MD56 DR_MD56
7 8
RN67 8P4R-10R
MD61
1 2
MD57
3 4
MEMDM7 DR_MEMDM7
5 6
-MDQS7 -DR_MDQS7
7 8
RN69 8P4R-10R
MD62 DR_MD62
1 2
MD58
3 4
MD63
5 6
MD59
7 8
DR_MD26
DR_MD30
DR_MD27
DR_MD31
DR_MD32
DR_MD36
DR_MD33
DR_MD37
DR_MD39
DR_MD40
DR_MD44
DR_MD41
DR_MD43
DR_MD47
DR_MD49
DR_MEMDM6
-DR_MDQS6
DR_MD54
DR_MD55
DR_MD51
DR_MD60
DR_MD61
DR_MD57
DR_MD58
DR_MD63
DR_MD59
VTT_DDR_SUS
C125
X_1U6Y0402
GND
VTT_DDR_SUS
VTT_DDR_SUS
C217
X_1U6Y0402
C138
X_0.1U25Y0402
C146
0.1U25Y0402
C151
X_0.1U25Y0402
C156
0.1U25Y0402
C167
X_0.1U25Y0402
C172
0.1U25Y0402
C174
X_0.1U25Y0402
C145
C220
C152
0.1U16Y0402
C221
0.1U16Y0402
+
C310
X_CD100U16EL5
0.1U25Y0402
X_0.1U25Y0402
0.1U25Y0402
X_0.1U25Y0402
0.1U25Y0402
X_0.1U25Y0402
0.1U25Y0402
C161
C154
1U6Y0402
X_0.1U16Y0402
All 104pF just for Cost-Down Consideration.
C228
C225
1U6Y0402
X_0.1U16Y0402
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS
in a single line along VTT island.
LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).
C281
X_4.7U10Y0805
C135
X_4.7U10Y0805
C307
X_4.7U10Y0805
GND
2
C234
4.7U10Y0805
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
DDR Terminations Part2
MS-7056
1
10 37Tuesday, February 17, 2004
0A
5
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]
VTT_DDR_SUS
C459
4.7U10Y0805
4
3
-MDQS[7..0]4
-DR_MDQS[7..0]8,9
DR_MD[63..0]8,9
A A
MD[63..0]4
MEMDM[7..0]4
DR_MEMDM[7..0]8,9
A
AVDD2
A10
A24
A25
A26A9B10
T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
G24
M26
L24
F24
R26
P25
N26
M25
K25
H25
G26
R23
P22
N23
M22
K22
H22
G23
L26
L23
F25
B11
A12
D25
D26
C26
U24
U25
U26
V21
V22
V23
V24
V25
V26
C22
AVDD2
RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
J24
RCADP13
J22
RCADP14
RCADP15
RCLKP0
RCLKP1
RCTLP
RCADN0
RCADN1
RCADN2
RCADN3
RCADN4
J26
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
J23
RCADN13
RCADN14
RCADN15
RCLKN0
RCLKN1
RCTLN
LDTRST
LDTSTP
RPCOMP
RNCOMP
RTCOMP
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
AGND2
VSS
C21
A23
From Claw Hammer
4 4
CADOP[0..15]4
CLKOP04
CLKOP14
CADON[0..15]4
3 3
CTLOP04
CLKON04
CLKON14
CTLON04
-LDTRST26
-LDTSTOP5,18
2 2
CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15
CLKOP0
CLKOP1
CTLOP0
CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15
CLKON0
CLKON1
CTLON0
-LDTRST
-LDTSTOP
RPCOMP
PNCOMP
RTCOMP
VDD_12_A
A8
VLDT
VSS
B8
VLDT
VSS
B13
VLDT
VSS
B15
U14A
VLDT
VSS
B17
VLDT
VSS
B19
B23
VLDT
VSS
B21
B24
B25
VLDT
VLDT
VSS
VSS
B22C8D8
B26B9C10
VLDT
VLDT
VSS
VSS
D6
VLDT
VSS
D12
C11
VLDT
VSS
D14
C23
VLDT
VSS
D16
C24
VLDT
VSS
D18
B
C25C9D10
VLDT
VLDT
VSS
VSS
D20
E5E6E8F7F8
VLDT
VSS
D11
VLDT
VSS
D22
VLDT
VSS
D23
VLDT
VSS
D24D9E10
VLDT
VLDT
VSS
VSS
F13
F12
VLDT
VSS
F14
VLDT
VSS
E11
F17
E21
VLDT
VSS
F18
E22
VLDT
VSS
F26
VLDT
VSS
E23
VLDT
VSS
VDD_12_A
E24E9F10
VLDT
VLDT
VLDT
VSS
VSS
VSS
G25H1H23
F11
F15
VLDT
VSS
J18
F16
VLDT
VSS
J2
VLDT
VSS
F19
J3
F20
VLDT
VSS
J21
F21
VLDT
VSS
J25
F22
VLDT
VSS
K4G1K10
F23
VLDT
VSS
C
K8T400M HT Interface
G21
G22
H21
J11
J12
J13
J14
J15
J16
J17
K18
K21
VLDT
VSS
K11
VLDT
VSS
K12
VLDT
VSS
K13
J10
VLDT
VSS
K14
VLDT
VSS
K15
VLDT
VSS
K16
VLDT
VSS
K17
VLDT
VSS
VLDT
VSS
K23H2L10
VLDT
VLDT
TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8
TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCLKP0
TCLKP1
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
TCLKN0
TCLKN1
VSS
VSS
L11
L12
VLDT
VLDT
TCTLP
TCTLN
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
L13
L14
L18
VLDT
VSS
L15
VLDT
VSS
B12
A13
B14
A15
A17
B18
A19
B20
E12
D13
E14
D15
D17
E18
D19
E20
B16
E16
A21
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
C16
E17
A22
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
K8M800
CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15
CLKIP0
CLKIP1
CTLIP0
CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15
CLKIN0
CLKIN1
CTLIN0
VDD_12_A
D
To Claw Hammer
CLKIP0 4
CLKIP1 4
CTLIP0 4
CLKIN0 4
CLKIN1 4
CTLIN0 4
CADIN[0..15] 4
U14_1
8X
MSI
AGP
E31-0400482-A58
E31-0400482-A58
CADIP[0..15] 4
For K8M800 Only
FB32 0R
CP16
1 2
PNCOMP
RTCOMP
RPCOMP
21
AGND2
R122 49.9RST
R120 100RST
R119 49.9RST
VCC3
AVDD2
C447
E
C449
1U10Y102P
VDD_12_A
AGND2
VDD_12_A
VCORE
1 1
A
C93
4.7U16Y1206
C427
X_0.22U16Y
C433
0.22U16Y
B
C434
0.22U16Y
C437
X_0.22U16Y
C439
0.22U16Y
C440
0.22U16Y
C
C442
0.22U16Y
C444
0.1U25Y
C453
X_0.1U25Y
C443
X_0.1U25Y
VDD_12_A
D
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
North Bridge K8M800 1/3
MS-7056
11 37Tuesday, February 17, 2004
E
0A
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