5
4
3
2
1
MS-7056
VIA (R) K8M800(8380) / VT8237CD Chipset
AMD PGA 754 Processor Schematics
D D
*AMD PGA 754 Processor
*VIA K8M800 / VT8237CD Chipset
(DDR 400 / AGP 8X / VLink 8X)
*W83697HF LPC I/O
*RT8110S/RT8100C
*VT6307 1394A Controler
*AC'97 Codec ALC658 Codec
*EQ PT2389 & SRS TA2136N
*USB 2.0 support (integrated into VT8237)
*AGP SLOT * 1 ( 8X )
C C
*PCI SLOT * 1
*MINI PCI SLOT * 1
*DDR DIMM * 2
B B
Orcad Config ERP BOM
A A
Version 0B 04/29/2004 0B Release
M:K8M800 L:LAN S:8237CD F:1394A
GL:Giga-LAN
Function Description
MS-7056 Ver:0A
Giga-LAN BOM (with Giga-LAN)
K8M800
8237CD
SMT5010
SMT5020
Blue Bird
10/100 LAN BOM (with 10/100 LAN)
K8M800
8237CD
SMT5010
SMT5020
Blue Bird
MCE BOM (with Giga-LAN)
K8M800
8237CD
MCE BOM (with 10/100 LAN)
K8M800
8237CD
SMT5010
SMT5020
SMT5010
SMT5020
B:Blue Bird
DIP
Total
DIP
Total
DIP
Total
DIP
Total
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
Create
Date.
Title Page
Cover Sheet 1
Block Diagram
Clock Synthesizer ICS950403 7
System Memory
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8M800(HT)
VGA Connector / TV-OUT
SB VT8237CD
PCI Connectors / Mini-PCI
1394a Controller VT6307
FAN / LM90 / MDC
IDE 66/100/133
RealTek RTL8100C/8110S
Front & Rear USB Port
W83627THF / KB / MS
PowerOK Circuit / Front Panel
K8 Vcore power
ACPI Power MS6
System Voltage Regulator
Front T-Board Connector
AC97 Codec / Audio Connector
Audio EQ / SRS / Connector
BULK / Decoupling 33
Power Generation
Screw Hole / FMark
History
Manual Parts
DDR DIMM 1 & 2 8
2
3 GPIO SPEC
4,5,6 AMD K8 -> 754 PGA Socket
9
10
11,12,13
14 AGP SLOT 8X
15
16,17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
Cover Sheet
MS-7056
1
1 36 Wednesday, July 21, 2004
0A
5
Block Diagram
4
3
2
1
AMD K8
D D
Socket 754
DDR
Audio Signal
Control Signal
HyperTransfer
AGP 8X /Fast Write
AGP
1394a * 2
C C
PCI 1
MINI PCI
PCI Bus
VIA
K8T400M
K8M400
VLINK
R,G,B,HSYNC,VSYNC
R,G,B,HSYNC,VSYNC
MII Interface
Primary ATA 100/133
IDE1
B B
Video In
VIA
VT8237
VT8237 S-ATA
SATA Connector
DDR * 2
VGA Connector
S-Video Out
10/100 BaseT
Lan
Keyboard
Mouse
FM Tuner
NS952M
Secondry
ATA 100/133
Phone In
4
IDE2
AC'97 Link
MDC Modem
Blue Bird VL+
T-Board
AUX In
Cent / LFT MIC IN SPDIF IN Line IN SPDIF OUT FNT MIC
A A
Surrond Line Out
EQ PT2389 SRS TA2136
5
AC'97 Codec
AC'97 Link
Secondry ATA 100/133
AC'97 Link
3
USB
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *2 ,
Back-Port *4,
Card Reader, Dual
OS
LPC BUS
LPC BUS
2
ROM
SUPER I/O
47LM292
Hardware
Monitor
FAN
Control
Serial
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
Block Diagram
MS-7056
1
2 36 Wednesday, July 21, 2004
0A
5
4
3
2
1
VT8237 GPIO Function Define
PIN NAME Function define
GPO0 (VSUS33)
GPO1 (VSUS33)
GPO2/SUSA#(VSUS33)
D D
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/GNT5
GPO8/GPI8/VGATE
GPO9/UDPWREN#
GPO10/GPI10/APICD0
GPO11/GPI11/APICD1
GPO12/GPI12/INTE#
C C
GPO13/GPI13/INTF#
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
Default
GPO0
GPO1
SUSA#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPI8
UDPWREN#
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
SUSLED ( Power LED )
5V_STR Control on S5
SUSA#
SUSST#
NA
NA
NA
NA
NA
JBAT1
NA
NA
INTE#
INTF#
MP_SB_INT
MD_SB_VMODE
Pull up / down Function
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
PIN NAME
GPI1 (VSUS33)
GPI2/EXTSMI#
(VSUS33)
GPI3/RING#
(VSUS33)
GPI4/LID#
(VSUS33)
GPI5/BATLOW#
(VSUS33)
GPI6/AGPBZ#
GPI7/REQ5#
GPI9/UDPWR UDPWR
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPO20/GPI20/ACSDIN2
/PCS0#
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/GHI#
B B
ACSDIN2
ACSDIN3
GPO23/GPI23/DPSLP#
GPO24/GPI24
/PCREQA/STRAP
GPO25/GPI25/GPIOB
/PCREQB/STRAP
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
VIDSEL/SATALED#
GPO29/GPI29/
VRDSLP
GPO30/GPI30/GPIOC
/PCGNTA/STRAP
GPO31/GPI31/GPIOD
/PCGNTB/STRAP
A A
GPI24
GPI25
SMBDT2
SMBCK2
GPI30
GPI31
5
NA
NA
NA
BB_INTR#
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
SIO_SMI#
NA
NA
J1B2/GP11/P17
J2B1/GP12/WDT
J2B2/GP13/DS1#
MIDI_OUT/GP26 BIOS_DIS
Pull up to 3VDUAL
Pull up to 3VDUAL
DEVICES
PCI SLOT
Mini PCI
SLOT
1394 INT#C
GLAN
4
3
Default
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
NA Pull up to VBAT GPI0 (VBAT)
ATADET0=>Detect IDE1 ATA100/66
CD_SMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
NA
SIO_PME# Pull up to VCC3
GPI7
INTRUDER#
CPUMISS
AOLGP1
IORDY
NA
INTRUDER#
NA
THERM_ALERT#
NA GPI19/APICCLK
SIO GPIO Function Define
Default
Function Pull up / down Function define PIN NAME
BIOS_VER1
BIOS_VER2
BIOS_VER3
PCI Routing
2
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3 1394_PCLK AD18
PREQ#4
PGNT#4 INT#D
Title
Size Document Number Rev
Date: Sheet of
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
IDSEL
AD16
AD17
AD19
Pull up / down Function define Function
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VBAT
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
CLOCK
PCICLK1
PCICLK2
GLAN_PCLK
MICRO-STAR INt'L CO., LTD.
MSI
GPIO Spec
MS-7056
0A
36 Wednesday, July 21, 2004
3
1
5
4
3
2
1
C469
X_102P_B
VREF routed as 40~50 mils trace wide ,
Space>25 mils
D D
C C
B B
A A
DDR_VREF 8
VDD_25_SUS
Place near CPU in 1" , Routed => 5:10/Trace:Space
, Same Length
MD[63..0] 10
MEMDM[7..0] 10
-MDQS[7..0] 10
DDR_VREF
R178 15RST
R177 15RST
AMD Suggest change to 34.8Ohm
5
C132
X_102P C496
AE13
VTT_SENSE
AG12
D14
C14
MEMVREF1
MEMZN
MEMZP
MEMZN
MEMZP
U21B
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
MEMORY INTERFACE
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
RSVD_MEMADDA15
RSVD_MEMADDA14
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
-MCS3 8,9
-MCS2 8,9
-MCS1 8,9
-MCS0 8,9
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBANKB1 8,9
MEMBANKB0 8,9
LAYOUT: Locate close to Clawhammer socket.
VTT_DDR_SUS
C460
MCKE0 8,9
MCKE1 8,9
MEMCLK_H[7..0] 8
MEMCLK_L[7..0] 8
MAA[13..0] 8,9
MAB[13..0] 8,9
C458
GND
CADIP[0..15] 11
CADIN[0..15] 11
3
X_10U10Y1206_B
CLKIP1 11
CLKIN1 11
CLKIP0 11
CLKIN0 11
CTLIP0 11
CTLIN0 11
C271
0.1U25Y_B
C283
X_0.1U25Y
C309
47P50N_B
0.22U16Y_B
VLDT0
VTT_DDR_SUS VDD_25_SUS
R445 49.9RST_B
R447 49.9RST_B
C497
VDD_12_A
0.22U16Y_B
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP1
CADIP0
CTLIP1
CTLIN1
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
T27
T28
V29
U29
V27
V28
Y29
Y25
Y27
Y28
R27
R26
T29
R29
VDD_12_A
C493
X_0.22U16Y_B
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
2
C494
X_0.22U16Y_B
U21A
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
HYPER TRANSPORT - LINK0
Title
Size Document Number Rev
Date: Sheet of
C495
0.22U16Y_B
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
MSI
VCORE
C189
X_0.1U25Y_B
VLDT0 5
CADOP[0..15] 11
CADON[0..15] 11
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
1U10Y_B
CADOP15
CADON15
CADOP14
CADON14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8
CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3
CADOP2 CADIP2
CADON2
CADOP1
CADON1
CADOP0
CADON0
CLKOP1
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
C492
X_0.1U25Y_B
VDD_12_A
VLDT0
C463
4.7U10Y0805_B
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
MICRO-STAR INt'L CO., LTD.
K8 DDR & HT
MS-7056
4 36 Wednesday, July 21, 2004
1
0A
5
4
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
VCCA_PLL regulator circuit.
D D
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
VDDA_25
FB22 180nH-1210-450mA
C153
10U6.3X0805
CPU_VDDA_25
C158
4.7U10Y0805
C159
392P
C462
0.22U16Y_B
VCC2_5
R205
C501
X_10U10Y1206_B
X_1KR
Near MS6,
Remove this two
components in 0B
THRMTRIP# 21,28
AH25
C166
X_102P
CPU_GD 28
VLDT0
C C
-LDTSTOP
Remove items in
0B BOM
PS_ON#A 26
B B
HDT Connectors
DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI
NC_AJ18
NC_AH18
NC_AG18
NC_AG17
NC_C19
NC_D18
A A
NC_D20
NC_B19
NC_C21
PS_ON#A
R149
Q21
X_2N7002
R147 1KR
R148 1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R174 1KR
5
1KR
VCC2_5
02/06 ADD close to CPUCLK0_H/L
into CPU side.
RN44
8P4R-1KR
VCC2_5
RN14
8P4R-1KR
8P4R-1KR
RN43
VLDT0 4
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
VCORE
R444 44.2RST_B
R443 44.2RST_B
C555
X_0.1U25Y
8/28 AMD CHANGE THE PULL-UP POWER
4
C465
102P_B
VDD_25_SUS
C464
102P_B
Near CPU in 0.5" .
X_102P_B C468
-CPURST 26
-LDTSTOP 11,18
COREFB_H 27
COREFB_L 27
Differential , "10:10:5:10:10" .
CPUCLK0_H 7
CPUCLK0_L 7
VTT_DDR_SUS
VDDIO_SENSE
C164 392P
C165 392P
VCC2_5
3
CPU_GD
L0_REF1
L0_REF0
VDDIO_SENSE
R150 169RST
R143 820RST
R141 820RST
R176 1KR
R175 1KR
1 2
3 4
5 6
7 8
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN16
8P4R-1KR
CLKIN_H
CLKIN_L
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AG2
AH1
AE21
AG4
AG6
AE9
AG9
A23
A24
B23
C16
C15
E20
E17
B21
A21
C18
A19
A28
AA2
B18
C20
C1
J3
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U21C
G_FBCLKOUT_H
G_FBCLKOUT_L
2
THERMTRIP_L
THERMDA
THERMDC
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
THRMTRIP_K8#
A20
THERMDA_CPU
A26
A27
VID4
AG13
VID4
VID3
VID2
VID1
VID0
TDO
VID3
AF14
VID2
AG14
VID1
AF15
VID0
AE15
NC_AG18
AG18
NC_AH18
AH18
NC_AG17
AG17
NC_AJ18
AJ18
FBCLKOUT_H
AH19
AJ19
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
AE19
NC_D20
D20
NC_C21
C21
NC_D18
D18
NC_C19
C19
NC_B19
B19
TDO
A22
AF18
D22
C22
VID0
VID2
VID1
VID3
B13
B7
C3
VID4
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
MSI
Title
Size Document Number Rev
Date: Sheet of
TP16
1
.
THERMDA_CPU 21
THERMDC_CPU 21
VID[4..0] 27
LAYOUT: Route
FBCLKOUT_H/L differentially
R151
with 20/8/5/8/20 spacing and
80.6RST
trace width. ( In CPU
breakout => routed 5:5:5 )
8/28 AMD CHANGE THE PULL-UP POWER
RN18
7 8
5 6
3 4
1 2
X_8P4R-4.7K
VDD_25_SUS
VCC2_5
R173 1KR
R522 1KR
R146 X_4.7KR
MICRO-STAR INt'L CO., LTD.
K8 HDT & MISC
MS-7056
1
C155
0.1U25Y
0A
36 Wednesday, July 21, 2004
5
5
4
3
2
1
U21E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
D D
C C
B B
A A
D2
VSS10
AF2
VSS11
W6
VSS12
Y7
VSS13
AA8
VSS14
AB9
VSS15
AA10
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
AE16
VSS20
J18
VSS21
G20
VSS22
R20
VSS23
U20
VSS24
W20
VSS25
AA20
VSS26
AC20
VSS27
AE20
VSS28
AG20
VSS29
AJ20
VSS30
D21
VSS31
F21
VSS32
H21
VSS33
K21
VSS34
M21
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
AD21
VSS40
AG21
VSS41
B22
VSS42
E22
VSS43
G22
VSS44
J22
VSS45
L22
VSS46
N22
VSS47
R22
VSS48
U22
VSS49
AG29
VSS50
AA22
VSS51
AC22
VSS52
AG22
VSS53
AH22
VSS54
AJ22
VSS55
D23
VSS56
F23
VSS57
H23
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
AB23
VSS64
AD23
VSS65
AG23
VSS66
E24
VSS67
G24
VSS68
J24
VSS69
N24
VSS70
R24
VSS71
U24
VSS72
W24
VSS73
AA24
VSS74
AC24
VSS75
AG24
VSS76
AJ24
VSS77
B25
VSS78
C25
VSS79
B26
VSS80
D26
VSS81
H26
VSS82
M26
VSS83
T26
VSS84
Y26
VSS85
AD26
VSS86
AF26
VSS87
AH26
VSS88
C27
VSS89
B28
VSS90
D28
VSS91
G28
VSS92
F15
VSS187
H15
VSS188
AB17
VSS206
AD17
VSS207
B16
VSS208
G18
VSS209
AA18
VSS210
AC18
VSS211
D19
VSS212
F19
VSS213
H19
VSS214
K19
VSS215
Y19
VSS216
AB19
VSS217
AD19
VSS218
AF19
VSS219
J20
VSS220
L20
VSS221
N20
VSS222
GND GND
5
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
GROUND
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
W21
AA21
AC21
AB22
AD22
W23
AA23
AC23
AB24
AD24
AH24
AE25
VCORE
C491
0.22U16Y_B
VCORE
C193
C187
C188
C204
10U10Y1206
10U10Y1206
VCORE
C136
VDD_25_SUS
C470
0.22U16Y
X_22U10Y1206
47P50N_B
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
U21D
L7
VDD1
VDD2
H18
VDD3
B20
VDD4
E21
VDD5
H22
VDD6
J23
VDD7
H24
VDD8
F26
VDD9
N7
VDD10
L9
VDD11
V10
VDD12
G13
VDD13
K14
VDD14
Y14
VDD15
VDD16
G15
VDD17
J15
VDD18
VDD19
H16
VDD20
K16
VDD21
Y16
VDD22
VDD23
G17
VDD24
J17
VDD25
VDD26
VDD27
VDD28
F18
VDD29
K18
VDD30
Y18
VDD31
VDD32
VDD33
VDD34
E19
VDD35
G19
VDD36
VDD39
VDD38
J19
VDD37
F20
VDD40
H20
VDD41
K20
VDD42
M20
VDD43
P20
VDD44
T20
VDD45
V20
VDD46
Y20
VDD47
VDD48
VDD49
G21
VDD50
J21
VDD51
L21
VDD52
N21
VDD53
R21
VDD54
U21
VDD55
VDD56
VDD57
VDD58
F22
VDD59
K22
VDD60
M22
VDD61
P22
VDD62
T22
VDD63
V22
VDD64
Y22
VDD65
VDD66
VDD67
E23
VDD68
G23
VDD69
L23
VDD70
N23
VDD71
R23
VDD72
U23
VDD73
VDD74
VDD75
VDD76
B24
VDD77
D24
VDD78
F24
VDD79
K24
VDD80
M24
VDD81
P24
VDD82
T24
VDD83
V24
VDD84
Y24
VDD85
VDD86
VDD87
VDD88
VDD89
K26
VDD90
P26
VDD91
V26
VDD92
POWER
EMI
C474
C195
0.22U16Y
0.22U16Y
In CPU Cavity
C141
C139
X_22U10Y1206
between VRM & CPU.
LAYOUT: Place beside processor.
47P50N_B
C471
C472
along VDD_CORE perimiter.
LAYOUT: Place 1 capacitor every 1-1.5"
VCORE
Place on CPU Solder side
C476
C475
0.22U16Y_B
X_0.22U16Y_B
0.22U16Y_B
CPU Solder Side Components.
C196
C197
C199
C200
0.22U16Y
C147
X_10U10Y1206
47P50N_B
C489
0.22U16Y
10U10Y1206
VDD_25_SUS
47P50N_B
X_10U10Y1206
C477
47P50N_B
3
0.22U16Y
C140
47P50N_B
C483
C478
C148
C169
C490
GND
Place on inside of CPU Cavity ( 5 *
0.22uF/0603 X7R high-freq decoupling
Cap. )
C479
X_0.22U16Y_B
X_1U10Y_B
C480
C481
0.22U16Y_B
X_0.22U16Y_B
C484
C485
C482
0.22U16Y_B
X_0.22U16Y_B
C486
0.22U16Y_B
LAYOUT: Place 6 EMI capsalong bottom right side of Clawhammer, 2 in middle
of HT link, and 12 along
C202
0.22U16Y
0.22U16Y
GND
C149
10U10Y1206
GND
C205
10U10Y1206
bottom left side of Claw-
0.22U16Y
LAYOUT: Place 1000pF capacitors
VCORE
C564
X_0.1U25Y_B
hammer.
C565
X_0.1U25Y
C117
X_0.22U16Y
LAYOUT: Place beside DDR slots.
LAYOUT: Place beside DDR slots.
C182
47P50N
47P50N_B
47P50N
C176
2
C219
47P50N
VDD_25_SUS
C178
4.7U10Y0805
47P50N
C222
0.22U16Y
C201
47P50N
C213
47P50N
C210
47P50N
C226
47P50N
Between DIMM and Socket
C247
X_4.7U10Y0805
C191
C186
Title
Size Document Number R ev
Date: Sheet of
47P50N
X_0.22U16Y
MSI
X_0.22U16Y_B
C259
C274
47P50N
47P50N
0.22U16Y
4.7U10Y0805
C214
C216
MICRO-STAR INt'L CO., LTD.
K8 Power & GND
MS-7056
1
6 36 Wednesday, July 21, 2004
0A
5
Clock Synthesizer
D D
CLKVCC3
CLKVCC3
C262 0.1U25Y
CLKVCC3
R193 10KR
C231 0.1U25Y
CLKVCC3
C261 0.1U25Y
CLKVCC3
C260 0.1U25Y
C C
CLKVCC3
C241 0.1U25Y
CLKVCC3
C240 0.1U25Y
CLKVCC3
CLKVCC3
C239 0.1U25Y
B B
ModeA ModeB Pin6 Pin7
0
0 1
1
1 1
Input Configuration
FS2
0 0 0 1
0
1
1 0
0
0
1
0
0
0
0
A A
0
0
0
0
0
0 0
0
U22
46
47
2
5
32
33
9
10
16
15
19
20
29
30
27
38
39
35
34
43
42
0
0
VDD_46
VSS_47
VDD_2
VSS_5
PD
VSSF
VDD_9
VSS_10
VDD_16
VSS_15
VDD_19
VSS_20
VDD_29
VSS_30
VSS_27
VDD_38
VSS_39
VDD_35
VSS_34
VDDA
VSSA
ICS950403
HTTCLK0
HTTCLK0
HTTCLK0
HTTCLK0
ModeA/PCI33_HT66SEL
FS0/REF0
FS1/REF1
FS2/REF2
FS3/48MHZ
ModeB/PCI33_HT66_1
PCI33_HT66_2
PCI33_HT66_3
PCI33_10
24_48MHZ/SEL
HTTCLK1
HTTCLK1
PCICLK7 PCICLK8
HTTCLK1
Clock Generator Output
FS0
FS1 FS2
CPU (MHz)
150
1 1 1
1
011 1
200.40
166.70
133.50
0 0
1
10 168.00
0
1
0
0 0
5
202
133.90
100.90
XOUT
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_F
PCI33_4
PCI33_5
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
PCICLK6
RESET
XIN
VCC3
FS0
1
FS1
48
FS2
45
CLKX1
3
CLKX2
4
FS3
31
HT_66_0
7
HT_66_1
8
HT_66_2
11
12
13
14
17
18
23
21
22
SEL_24
28
SMBDATA1
26
SMBCLK1
25
41
40
37
36
-SEL_66
6
24
SPREAD
44
Pin8 Pin11
HTTCLK2
HTTCLK2
PCICLK8
C254
0.1U25Y
R201 10KR
R187 10KR
PCI33 (MHz)
33.33
33.33
33.33
33.33
36.56100.20
30.00
X1/6
X1/6
33.63
4
CP3
X_COPPER
R207 22R
R189 22R C237 0.1U25Y
R190 22R
R194 33R
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
R191 15RST
R192 15RST
PCICLK9
HTTCLK3
PCICLK9
PCICLK9
4
CLKVCC3
C255
0.1U25Y
SB_OSC14
GUICLK
APICCLK
39P C263
X1 14M-32pf-HC49S-D
R195 33R
39P C264
RN60
8P4R-22R
RN61
8P4R-22R
RN57
8P4R-22R
CPUCLK0_H
CPUCLK0_L
FP_RST# 26,28,30
SER_24 Pin28
24MHz
1
48MHz
0
PCI33_HT66 (MHz)
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
73.12
60.00
X1/6
X1/3
67.27
C245
4.7U10Y0805
SB_OSC14 17
GUICLK 12
APICCLK 18
T* Frequency
Recheck in 0B
VCLK
GCLK_SLOT
GCLK_NB
GLAN_PCLK
PCICLK1
PCICLK2
SIO_PCLK
BIOS_PCLK
1394_PCLK
SB_PCLK
SIO48M
SMBDATA1 8,17,21,23,28
SMBCLK1 8,17,21,23,28
USBCLK_SB 16
VCLK 18
GCLK_SLOT 14
GCLK_NB 12
GLAN_PCLK 23
PCICLK1 19
PCICLK2 19
SIO_PCLK 25
BIOS_PCLK 25
1394_PCLK 20
SB_PCLK 18
SIO48M 25
CPUCLK0_H 5
CPUCLK0_L 5
Comment
Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
ICS OverClock
ICS UnderClock
Bypass mode
Bypass mode
Tri-state mode
3
CPUCLK0_H
CPUCLK0_L
Add in 0B BOM
SEL_24
FS3
FS2
FS1
FS0
FS3
FS2
FS1
FS0
HT_66_0
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
SB_OSC14
APICCLK
SB_PCLK
1394_PCLK
SIO_PCLK
PCICLK2
BIOS_PCLK
GLAN_PCLK
PCICLK1
3
C229 15P
C230 15P
R186 10KR
R185 10KR
R182 X_10KR
R180 X_10KR
R200 X_10KR
R184 X_10KR
R183 10KR
R181 10KR
R206 10KR
R202 10KR
CN17
7 8
5 6
3 4
1 2
8P4C-10P
C232 10P
C242 10P
C270 X_10P
C238 X_10P
1 2
3 4
5 6
7 8
C272 10P
C279 10P
C280 10P
CLKVCC3
CN18
8P4C-10P
2
Signal
CPUCLK# / CPUCLK 20:5:5:5:20
GCLK_SLOT
GCLK_NB
VCLK
SB_PCLK
PCICLK[1:2]
SIO_PCLK
BIOS_PCLK
1394_PCLK
GLAN_PCLK
USBCLK_SB
SIO_14
SB_OSC14
APICCLK
GUICLK
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
6:24
Clock Trace
Clock
Synthesizer
Clock
Segment
Clock
Synthesizer
CPUT_1
CPUC_1
PCI33_HT66_2
PCI33_HT66_3
PCI33_HT66_1
PCI33_F
PCI33_1
PCI33_2
PCI33_3
PCI33_4
PCI33_5
2
LT
<0.5"
<1"
<1"
Title
Size Document Number Rev
Date: Sheet of
PCB LAYOUT GIUDE
Mismatch
10mil
<0.1"
<1"
<1"
R
Lcpu
CPUCLK0_H
Lcpu
CPUCLK0_L
L_slot
R C
L_slot+4"(L_NB)
RRC
L_slot+4"(L_SB)
C
L1+3"
R C
R
R C
R
R
R C
L6(GLAN)
C
L1(PCI)
L2(MiniPCI)
C
L3(SIO)
C
L4(BIOS)
L5(1394)
R C
MICRO-STAR INt'L CO., LTD.
MSI
1
Length Range W : S
1" - 9"
1" - 8"
5" - 12"
5" - 12"
4" - 15"
1" - 12"
4" - 15"
4" - 15"
4" - 15"
Minimum
50mils
Notes
Base on GCLK_SLOT + 4"
The longest PCICLK + 3"
C
SB_PCLK
PCICLK1
The longest PCI CLK
PCICLK2
SIO_PCLK
BIOS_PCLK
1394_PCLK
Clock Synthesizer
MS-7056
1
LT
<0.5"
GCLK_SLOT
GCLK_NB
VCLK
7 36 Wednesday, July 21, 2004
Minimum
20mils
Socket
754
CLKIN_H
CLKIN_L
AGP Slot
CLK
K8M800 NB
CLK
VT8237 SB
VCLK
VT8237 SB
PCICLK
RTL8100C GLAN_PCLK
PCI-SLOT
Mini-PCI
47LM292
FWH BIOS
VT6307
0A
5
VDD_25_SUS
C137
0.1U25Y
DR_MD[63..0]
R239 4.7KR
-MSWEA 4,9
DDR_VREF
C131
102P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
1
9
101
102
DR_MD[63..0] 9,10
D D
C C
B B
VDD_25_SUS
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
SLAVE ADDRESS = 1010000B
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
Place 104p Cap. near the DIMM
4
104
112
128
136
143
156
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
184
DDR DIMM
SOCKET
VSS14
VSS15
VSS16
VSS17
100
116
124
132
139
SYSTEM MEMORY
164
172
180
15
82
184
VDDID
VDDQ12
VDDQ13
VDDQ14
VDDQ15
PIN
VSS18
VSS19
VSS20
145
152
160
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
NC(RESET#)
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
176
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR1
DDR400-CH
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAA13
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
SMBCLK1
SMBDATA1
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
-MCS0 4,9
-MCS1 4,9
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
-DR_MDQS7 9,10
MAA[13..0]
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17,21,23,28
SMBDATA1 7,17,21,23,28
MEMCLK_H5 4
MEMCLK_L5 4
MEMCLK_H0 4
MEMCLK_L0 4
MEMCLK_H7 4
MEMCLK_L7 4
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
DR_MEMDM[7..0]
3
MAA[13..0] 4,9
VDD_25_SUS
Place 104p and 1000p
Cap. near the DIMM
DR_MEMDM[7..0] 9,10
R238 4.7KR
-MSWEB 4,9
C127
0.1U25Y
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
DDR_VREF
C133
X_102P
2
VDD_25_SUS
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
104
112
128
136
143
156
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
184
DDR DIMM
SOCKET
VSS14
VSS15
VSS16
VSS17
100
116
124
132
139
164
172
180
VDDQ12
VDDQ13
PIN
VSS18
VSS19
145
152
160
15
82
VDDID
VDDQ14
VDDQ15
FETEN
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
157
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H4
16
MEMCLK_L4
17
MEMCLK_H1
137
MEMCLK_L1
138
MEMCLK_H6
76
MEMCLK_L6
75
173
10
21
111
65
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR2
DDR400-CH
1
-MCS2
-MCS3
MAB13
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
SMBCLK1
SMBDATA1
MCKE0
MCKE1
-MSCASB
-MSRASB
-MCS2 4,9
-MCS3 4,9
MEMBANKB0 4,9
MEMBANKB1 4,9
VDD_25_SUS
MEMCLK_H4 4
MEMCLK_L4 4
MEMCLK_H1 4
MEMCLK_L1 4
MEMCLK_H6 4
MEMCLK_L6 4
-MSCASB 4,9
-MSRASB 4,9
MAB[13..0] 4,9
VDD_25_SUS
A A
R136
1KRST
R135
1KRST
C142
0.1U25Y
DDR_VREF
C130
0.1U25Y
5
DDR_VREF 4
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
4
3
2
Date: Sheet of
DDR DIMM1 & 2
MS-7056
1
8 36 Wednesday, July 21, 2004
0A
5
4
3
2
1
DDR Terminations
Ver:0B
VTT_DDR_SUS VTT_DDR_SUS
D D
C C
B B
-MSCASB 4,8
-MSCASA 4,8
-MSRASB 4,8
-MSRASA 4,8
DR_MD59
DR_MD63
DR_MD58
DR_MD62
-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61
DR_MD56
DR_MD60
DR_MD51
DR_MD55
DR_MD50
DR_MD54
-DR_MDQS6
DR_MEMDM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD49
DR_MD48
DR_MD47
DR_MD46
DR_MD43
DR_MD42
-DR_MDQS5
DR_MEMDM5
-MCS1
-MCS1 4,8
-MCS3
-MCS3 4,8
-MCS0
-MCS0 4,8
-MCS2
-MCS2 4,8
-MSCASB
-MSCASA
DR_MD41
DR_MD45
-MSWEB
-MSWEB 4,8
-MSWEA 4,8
-MSWEA
-MSRASB
-MSRASA
DR_MD44
R237 27R
Change 0A BOM
from 47R to 27R
RN68 8P4R-27R0402
7 8
5 6
3 4
1 2
RN66 8P4R-27R0402
7 8
5 6
3 4
1 2
RN64 8P4R-27R0402
7 8
5 6
3 4
1 2
RN62 8P4R-27R0402
7 8
5 6
3 4
1 2
RN59 8P4R-27R0402
7 8
5 6
3 4
1 2
RN56 8P4R-27R0402
7 8
5 6
3 4
1 2
RN54 8P4R-27R0402
7 8
5 6
3 4
1 2
RN52 8P4R-27R0402
7 8
5 6
3 4
1 2
RN50 8P4R-27R0402
7 8
5 6
3 4
1 2
RN49 8P4R-27R0402
7 8
5 6
3 4
1 2
MEMBANKB0 4,8
MEMBANKA0 4,8
MEMBANKB1 4,8
MEMBANKA1 4,8
DR_MD40
DR_MD35
DR_MD39
DR_MD38
DR_MD34
DR_MEMDM4
-DR_MDQS4
DR_MD37
DR_MD33
DR_MD36
DR_MD32
MAA10
MAB10
MAA0
MAB0
MAA1
MAB1
MAA2
MAB2
DR_MD31
DR_MD27
DR_MD26
DR_MD30
MAB3
MAA3
MAA4
MAB4
DR_MEMDM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
DR_MD24
MAB6
MAA6
MAA5
MAB5
DR_MD23
DR_MD19
VTT_DDR_SUS
RN47 8P4R-27R0402
7 8
5 6
3 4
1 2
RN45 8P4R-27R0402
7 8
5 6
3 4
1 2
RN42 8P4R-27R0402
7 8
5 6
3 4
1 2
RN40 8P4R-27R0402
7 8
5 6
3 4
1 2
RN39 8P4R-27R0402
7 8
5 6
3 4
1 2
RN38 8P4R-27R0402
7 8
5 6
3 4
1 2
RN37 8P4R-27R0402
7 8
5 6
3 4
1 2
RN35 8P4R-27R0402
7 8
5 6
3 4
1 2
RN34 8P4R-27R0402
7 8
5 6
3 4
1 2
RN31 8P4R-27R0402
7 8
5 6
3 4
1 2
RN29 8P4R-27R0402
7 8
5 6
3 4
1 2
-MCS2
-MCS2 4,8
MAA8
MAB8
DR_MD22
MAA7
MAB7
DR_MD18
DR_MEMDM2
MAB9
MAA9
MAB11
MAA11
DR_MD21
-DR_MDQS2
DR_MD17
MAB12
MAA12
DR_MD16
DR_MD20
MCKE0 4,8
MCKE1 4,8
DR_MD11
DR_MD10
DR_MD15
DR_MD14
DR_MEMDM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD7
DR_MD6
DR_MD2
-DR_MDQS0
DR_MEMDM0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
RN28 8P4R-27R0402
7 8
5 6
3 4
1 2
RN27 8P4R-27R0402
7 8
5 6
3 4
1 2
RN25 8P4R-27R0402
7 8
5 6
3 4
1 2
RN23 8P4R-27R0402
7 8
5 6
3 4
1 2
RN21 8P4R-27R0402
7 8
5 6
3 4
1 2
RN20 8P4R-27R0402
7 8
5 6
3 4
1 2
RN17 8P4R-27R0402
7 8
5 6
3 4
1 2
RN13 8P4R-27R0402
7 8
5 6
3 4
1 2
RN11 8P4R-27R0402
7 8
5 6
3 4
1 2
RN9 8P4R-27R0402
7 8
5 6
3 4
1 2
-MSCASB 4,8
-MSCASA 4,8
-MSRASB 4,8
-MSRASA 4,8
-MSWEB 4,8
-MSWEA 4,8
MEMBANKB1 4,8
MEMBANKA1 4,8
MEMBANKB0 4,8
MEMBANKA0 4,8
-MCS3
-MCS3 4,8
MAB13
MAA13
MAB12
MAA12
MAB11
MAA11
MAB1
MAA1
MAB3
MAA3
MAB2
MAA2
MAB6
MAA6
MAB4
MAA4
MAB8
MAA8
MAB5
MAA5
MAA0
MAA10
MAB0
MAB10
-MSCASB
-MCS0
-MCS0 4,8
-MSCASA
-MCS1
-MCS1 4,8
MAA9
MAB9
MAB7
MAA7
-MSRASB
-MSRASA
-MSWEB
-MSWEA
MCKE1 4,8
MCKE0 4,8
CN16
8P4C-10P
CN5
8P4C-10P
CN10
8P4C-10P
CN9
8P4C-10P
CN8
8P4C-10P
CN7
8P4C-10P
CN11
8P4C-10P
CN15
8P4C-10P
CN6
8P4C-10P
CN13
8P4C-10P
CN12
8P4C-10P
CN4
8P4C-10P
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
A A
MICRO-STAR INt'L CO., LTD.
MEMCLK_L[7..0] 4,8
MEMCLK_H[7..0] 4,8
-DR_MDQS[7..0] 8,10
5
4
MEMCLK_L[7..0]
MEMCLK_H[7..0]
-DR_MDQS[7..0]
3
DR_MD[63..0] 8,10
MAB[13..0] 4,8
MAA[13..0] 4,8
DR_MEMDM[7..0] 8,10
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]
2
MSI
Title
Size Document Number Rev
Date: Sheet of
DDR Terminations Part1
MS-7056
1
9 36 Wednesday, July 21, 2004
0A
5
4
3
2
1
LAYOUT: Place on backside,
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS VDD_25_SUS
D D
C C
B B
RN10 8P4R-10R
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN12 8P4R-10R
MEMDM0 DR_MEMDM0
1 2
-MDQS0
3 4
MD2
5 6
MD6
7 8
RN15 8P4R-10R
MD7
1 2
MD3
3 4
MD8
5 6
MD9
7 8
RN19 8P4R-10R
MD12
1 2
-MDQS1 -DR_MDQS1
3 4
MEMDM1 DR_MEMDM1
5 6
MD13 DR_MD13
7 8
RN22 8P4R-10R
MD14
1 2
MD15
3 4
MD10
5 6
MD11
7 8
RN26 8P4R-10R
MD21 DR_MD21
1 2
MEMDM2 DR_MEMDM2
3 4
MD18 DR_MD18
5 6
MD22 DR_MD22
7 8
RN24 8P4R-10R
MD20
1 2
MD16 DR_MD16
3 4
5 6
-MDQS2 -DR_MDQS2
7 8
RN30 8P4R-10R
MD23
1 2
MD19 DR_MD19
3 4
MD24
5 6
MD28 DR_MD28
7 8
RN32 8P4R-10R
MD29
1 2
MD25
3 4
-MDQS3
5 6
MEMDM3 DR_MEMDM3
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
-DR_MDQS0
DR_MD2
DR_MD6
DR_MD7
DR_MD3
DR_MD8
DR_MD9
DR_MD12
DR_MD14
DR_MD15
DR_MD10
DR_MD11
DR_MD20
DR_MD17 MD17
DR_MD23
DR_MD24
DR_MD29
DR_MD25
-DR_MDQS3
RN36 8P4R-10R
MD26
1 2
MD30
3 4
MD27
5 6
MD31
7 8
RN41 8P4R-10R
MD32
1 2
MD36
3 4
MD33
5 6
MD37
7 8
RN46 8P4R-10R
-MDQS4 -DR_MDQS4
1 2
MEMDM4 DR_MEMDM4
3 4
MD34 DR_MD34
5 6
MD38 DR_MD38
7 8
RN48 8P4R-10R
MD35 DR_MD35
1 2
MD39
3 4
MD40
5 6
MD44
7 8
RN51 8P4R-10R
MD45 DR_MD45
1 2
MD41
3 4
MEMDM5 DR_MEMDM5
5 6
-MDQS5 -DR_MDQS5
7 8
RN55 8P4R-10R
MD42 DR_MD42
1 2
MD43
3 4
MD46 DR_MD46
5 6
MD47
7 8
RN58 8P4R-10R
MD48 DR_MD48
1 2
MD49
3 4
MD52 DR_MD52
5 6
MD53 DR_MD53
7 8
RN63 8P4R-10R
MEMDM6
1 2
-MDQS6
3 4
MD54
5 6
MD50 DR_MD50
7 8
RN65 8P4R-10R
MD55
1 2
MD51
3 4
MD60
5 6
MD56 DR_MD56
7 8
RN67 8P4R-10R
MD61
1 2
MD57
3 4
MEMDM7 DR_MEMDM7
5 6
-MDQS7 -DR_MDQS7
7 8
RN69 8P4R-10R
MD62 DR_MD62
1 2
MD58
3 4
MD63
5 6
MD59
7 8
DR_MD26
DR_MD30
DR_MD27
DR_MD31
DR_MD32
DR_MD36
DR_MD33
DR_MD37
DR_MD39
DR_MD40
DR_MD44
DR_MD41
DR_MD43
DR_MD47
DR_MD49
DR_MEMDM6
-DR_MDQS6
DR_MD54
DR_MD55
DR_MD51
DR_MD60
DR_MD61
DR_MD57
DR_MD58
DR_MD63
DR_MD59
evenly spaced around VTT fill.
C138
X_0.1U25Y0402
C146
0.1U16Y0402
C151
X_0.1U25Y0402
C156
0.1U16Y0402
C167
X_0.1U25Y0402
C172
0.1U16Y0402
C174
X_0.1U25Y0402
X_1U6Y0402
VTT_DDR_SUS
1 2
EC28
+
CD470U10EL11.5
C217
+
C310
X_CD100U16EL5
VTT_DDR_SUS
C125
GND
VTT_DDR_SUS
C145
0.1U16Y0402
C220
0.1U16Y0402
0.1U16Y0402
C567
C152
C566
C180
0.1U16Y0402
C190
X_0.1U25Y0402
C206
0.1U16Y0402
C218
X_0.1U25Y0402
C223
0.1U16Y0402
C227
X_0.1U25Y0402
C236
0.1U16Y0402
C154
0.1U16Y0402
47P50N_B
1U6Y0402
C568
47P50N
C161
C168
0.1U16Y0402
0.1U25Y_B
C569
0.1U16Y0402
X_0.1U25Y0402
X_0.1U25Y0402
0.1U16Y0402
X_0.1U25Y0402
X_0.1U25Y0402
X_0.1U25Y0402
C173
0.1U16Y0402
47P50N
C305
C570
C571
0.1U25Y_B
C256
C266
C275
C284
C293
C296
C175
C177
1U6Y0402
0.1U16Y0402
C573
C572 0.1U16Y0402
X_47P50N_B
C183
47P50N_B
C134
0.1U25Y0402
C575
47P50N_B
C577
0.1U25Y_B
47P50N_B
C580
47P50N_B
C581
X_0.1U25Y_B
X_0.1U25Y_B
0.1U16Y0402
47P50N_B
VTT_DDR_SUS VTT_DDR_SUS VTT_DDR_SUS VTT_DDR_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C579
C582
C185
0.1U16Y0402
All 104pF just for Cost-Down Consideration.
0.1U16Y0402
C249
C243
0.1U16Y0402
C265
C253
1U6Y0402
0.1U16Y0402
C276
0.1U16Y0402
C225
C221
0.1U16Y0402
C228
C235
1U6Y0402
0.1U16Y0402
0.1U16Y0402
VTT_DDR_SUS VDD_25_SUS
C574
47P50N
C576
X_0.1U25Y_B
C578
X_0.1U25Y_B
change 5010
to 5020
C198
C288
C209
C207
1U6Y0402
0.1U16Y0402
C292
C295
1U6Y0402
0.1U16Y0402
0.1U16Y0402
0.1U16Y0402
C215
C212
C302
0.1U16Y0402
0.1U16Y0402
1U6Y0402
C304
1U6Y0402
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS
in a single line along VTT island.
LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).
C459
4.7U10Y0805_B
3
C281
1U16Y0805
C135
1U16Y0805
C307
1U16Y0805
GND
2
C234
4.7U10Y0805
C583
X_0.1U25Y_B
change 5010
to 5020
MSI
Title
Size Document Number Rev
Date: Sheet of
5
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]
VTT_DDR_SUS
4
-MDQS[7..0] 4
-DR_MDQS[7..0] 8,9
DR_MD[63..0] 8,9
A A
MD[63..0] 4
MEMDM[7..0] 4
DR_MEMDM[7..0] 8,9
VTT_DDR_SUS
C585
C586
C584
0.1U25Y_B
X_0.1U25Y_B
0.1U25Y_B
C587
0.1U25Y_B
MICRO-STAR INt'L CO., LTD.
DDR Terminations Part2
MS-7056
10 36 Wednesday, July 21, 2004
1
C588
X_0.1U25Y_B
0A
A
AVDD2
A10
A24
A25
A26
VLDT
VSSA8VSS
VSS
A23
VLDT
VLDT
VSSB8VSS
B13
B15
VLDT
B10
U14A
VLDTA9VLDT
VSS
B17
B19
VSS
B23
B21
B24
VLDT
VSS
B22
B25
VLDT
VSS
T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
G24
M26
L24
F24
R26
P25
N26
M25
K25
H25
G26
R23
P22
N23
M22
K22
H22
G23
L26
L23
F25
B11
A12
D25
D26
C26
U24
U25
U26
V21
V22
V23
V24
V25
V26
C22
AVDD2
RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
J24
RCADP13
J22
RCADP14
RCADP15
RCLKP0
RCLKP1
RCTLP
RCADN0
RCADN1
RCADN2
RCADN3
RCADN4
J26
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
J23
RCADN13
RCADN14
RCADN15
RCLKN0
RCLKN1
RCTLN
LDTRST
LDTSTP
RPCOMP
RNCOMP
RTCOMP
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
From Claw Hammer
4 4
CADOP[0..15] 4
CLKOP0 4
CLKOP1 4
CADON[0..15] 4
3 3
CTLOP0 4
CLKON0 4
CLKON1 4
CTLON0 4
-LDTRST 26
-LDTSTOP 5,18
2 2
CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15
CLKOP0
CLKOP1
CTLOP0
CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15
CLKON0
CLKON1
CTLON0
-LDTRST
-LDTSTOP
RPCOMP
PNCOMP
RTCOMP
VDD_12_A
AGND2
C21
B26
C10
C11
VLDT
VLDT
VLDTB9VLDT
VLDT
VSSD6VSS
VSS
VSSC8VSS
VSS
D8
D12
D14
C23
D16
VLDT
VSS
B
C24
VLDT
D18
C25
D10
D11
VLDT
VLDTC9VLDT
VLDT
VSS
VSSE5VSSE6VSSE8VSSF7VSSF8VSS
D20
D22
VLDT
D23
D24
VLDT
F12
VLDT
F13
E10
E11
VLDTD9VLDT
VSS
VSS
F14
F17
E21
VLDT
VSS
F18
E22
VLDT
VSS
F26
E23
VLDT
VSS
G1
E24
VLDT
VSS
G25
VLDT
VSS
VDD_12_A
F10
F11
F15
VLDTE9VLDT
VLDT
VSSH1VSS
VSS
H2
J18
H23
VLDT
VSS
F16
J2
VLDT
VSS
F19
J3
F20
VLDT
VSS
J21
F21
VLDT
VSS
J25
F22
VLDT
VSS
K4
F23
VLDT
VSS
K10
C
K8T400M HT Interface
G21
G22
H21
J11
J12
J13
J14
J15
J16
J17
K18
K21
K23
VLDT
VSS
L10
VLDT
VSS
L11
VLDT
VLDT
VLDT
TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8
TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCLKP0
TCLKP1
TCTLP
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
TCLKN0
TCLKN1
TCTLN
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
L13
L12
L14
VLDT
VSS
L18
L15
VLDT
VSS
B12
A13
B14
A15
A17
B18
A19
B20
E12
D13
E14
D15
D17
E18
D19
E20
B16
E16
A21
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
C16
E17
A22
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
K8M800
CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15
CLKIP0
CLKIP1
CTLIP0
CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15
CLKIN0
CLKIN1
CTLIN0
VDD_12_A
VLDT
VSS
K11
VLDT
VSS
K12
VLDT
VSS
K13
VLDT
VSS
J10
K14
VLDT
VSS
K15
VLDT
VSS
K16
VLDT
VSS
K17
VLDT
VSS
D
To Claw Hammer
CLKIP0 4
CLKIP1 4
CTLIP0 4
CLKIN0 4
CLKIN1 4
CTLIN0 4
CADIN[0..15] 4
U14_1
8X
M SI
A GP
E31-0400482-A58
E31-0401490-K08
CADIP[0..15] 4
For K8M800 Only
VCC3
CP21
1 2
2 1
FB32 X_0R_B
CP16
AGND2
1 2
PNCOMP
R122 49.9RST
RTCOMP
R120 100RST
RPCOMP
R119 49.9RST
AVDD2
C447
E
C449
1U10Y_B 102P_B
VDD_12_A
AGND2
VDD_12_A
VCORE
1 1
C93
4.7U16Y1206
A
C427
X_0.22U16Y_B
C433
0.22U16Y_B
B
C434
0.22U16Y_B
C437
X_0.22U16Y_B
C439
0.22U16Y_B
C440
0.22U16Y_B
C
C442
0.22U16Y_B
C444
0.1U25Y_B
C453
0.1U25Y_B
C443
0.1U25Y_B
VDD_12_A
D
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
North Bridge K8M800 1/3
MS-7056
11 36 Wednesday, July 21, 2004
E
0A
A
B
C
D
E
K8T400M AGP 8X ,V-Link, Misc. Control
VDDQ
VCC3
AGPVREF_GC
LAYOUT: Place caps as close NB as possible
4 4
GAD[0..31] 14
3 3
GC/BE#[3..0] 14
AD_STBS0 14
AD_STBF0 14
AD_STBS1 14
AD_STBF1 14
GFRAME 14
GIRDY 14
GTRDY 14
GDEVSEL 14
GSTOP 14
GPAR 14
RBF 14
WBF 14
GREQ 14
2 2
1 1
GGNT 14
GSERR 14
GCLK_NB 7
SBA[7..0] 14
SB_STBS 14
SB_STBF 14
AGPVREF_GC 14
AGP8XDET# 14
DBIL 14
DBIH 14
GAD0
GAD1
GAD2
GAD3 VLAD2
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3
AD_STBS0
AD_STBF0
AD_STBS1
AD_STBF1
SB_STBS
SB_STBF
ST0 14
ST1 14
ST2 14
AGPPCOMP
AGPNCOMP
AGPVREF_GC
DBIL
DBIH
A
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
AF18
GD0/FPD10
AD18
GD1/FPD11
AE18
GD2/FPDVICLK
AF17
GD3/FPD09
AD17
GD4/FPD08
AD16
GD5/FPD07
AE16
GD6/FPD06
AF16
GD7/FPD05
AF14
GD8/FPDVIDET
AD14
GD9/FPDVIHS
AD13
GD10/FPD01
AE13
GD11/FPD23
AF13
GD12/FPD00
AD12
GD13/FPD22
AF12
GD14/FPD21
AE12
GD15/FPD20
AD10
GD16/FPD18
AE10
GD17/FPD17
AF10
GD18/FPD16
AD9
GD19/FPDE
AF9
GD20/FPD14
AF8
GD21/FPCLK
AE9
GD22/FPD13
AD8
GD23/FPD15
AF6
GD24/DVP1D09
AD7
GD25
AE6
GD26/DVP1D10
AD5
GD27
AF5
GD28/DVP1D07
AF4
GD29/DVP1D06
AE4
GD30/DVP1D08
AD4
GD31/DVP1D04
AD15
GCBE0/FPD03
AF11
GCBE1/SB_DA
AD11
GCBE2/FPD19
AC7
GCBE3/DVP1D11
AF15
ADSTB0S/FPD02
AE15
ADSTB0F/FPD04
AF7
ADSTB1S/FPDET
AE7
ADSTB1F/FPD12
AC9
GFRAME/FPHS
AC10
GIRDY/SB_CK
AC14
GTRDY
AC11
GDEVSEL/FPVS
AC12
GSTOP/FPDVICLK_N
AC16
GPAR/FPDVIVS
AD6
RBF
AC1
WBF/FPCLK_N
Y1
GREQ/DVI_DDCCK
AA3
GGNT/DVI_DDCDA
AC15
GSERR/FPDVIDE
A11
GCLK
AC2
SBA0/DVP1VS
AC3
SBA1/DVP1DE
AD1
SBA2/DVP1D00
AD2
SBA3/DVP1HS
AF2
SBA4/DVP1D05
AD3
SBA5/DVP1D03
AE3
SBA6/DVP1CLK
AF3
SBA7/DVP1CLK_N
AE1
SB_STBS/DVP1D02
AF1
SB_STBF/DVP1D01
AA2
ST0
AA1
ST1/DVP1DET
AB1
ST2
V1
AGPPCOMP
W1
AGPNCOMP
AC13
AGPVREF0
AC6
AGPVREF1
Y2
AGP8XDET
AC4
DBIL
AC5
DBIH
VSSQQ
T1
U1
N9
P9
R9
N5
VCCQQ
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VSSR1VSSR2VSSR3VSSR4VSSR5VSS
VSS
VSS
VSS
VSS
VSS
R10
R11
R12
R13
R14
R15
L8
K9
L9
VCC4/NCM5VCC4/NC
VCC4/NCM9VCC4/NC
VCC4/NCL5VCC4/NC
VCC4/NC
VSS
VSS
VSS
VSS
VSS
VSS
P13
P14
P15
P16
P17
P23
B
K8
VSS
P12
K5
J9
VCC4/NC
VCC4/NC
VSS
P10
P11
J4
J5
VCC4/NC
VCC4/NC
VSS
VSSP5VSS
N25
H4
H5
VCC4/NC
VCC4/NC
VSS
VSS
N16
N17
G5
H3
VCC4/NC
VCC4/NC
VSS
VSS
N14
N15
G3
G4
VCC4/NC
VCC4/NC
VSS
VSS
N12
N13
G2
VCC4/NC
VSS
N11
F1
F2
F5
F3
VCC4/NC
VCC4/NCF6VCC4/NC
VCC4/NC
VCC4/NCF4VCC4/NC
TVD00/DVP0D00/NC
TVD01/DVP0D01/NC
TVD02/DVP0D02/NC
TVD03/DVP0D03/NC
TVD04/DVP0D04/NC
TVD05/DVP0D05/NC
TVD06/DVP0D06/NC
TVD07/DVP0D07/NC
TVD08/DVP0D08/NC
TVD09/DVP0D09/NC
TVD10/DVP0D10/NC
TVD11/DVP0D11/NC
TVCLKIN/DVP0DET/NC
TVCLK/DVP0DCLK/NC
VSS
VSS
VSS
VSS
VSS
VSS
N10
M15
M16
M17
M21
M23
E2
E3
E1
D1
U14B
VCC4/NCE4VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VPAR
UPSTB
UPSTB
DNSTB
DNSTB
UPCMD
DNCMD
LVREF
LCOMPP
PWRGD
PCIRST
TESTIN
SUSTAT
DEBUG
AR/NC
AG/NC
AB/NC
RSET/NC
HSYNC/NC
VSYNC/NC
XIN/NC
INTA/NC
BISTIN/NC
SPCLK1/NC
SPCLK2/NC
SPD1/NC
SPD2/NC
TVDE/DVP0DE/NC
TVHS/DVP0HS/NC
TVVS/DVP0VS/NC
GPO0/NC
GPOUT/NC
VSS
VSS
VSS
VSS
VSS
VSS
L25
M10
M11
M12
M13
M14
K8M800
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VBE
TESTIN
VLAD0
AD20
VLAD1
AD21
AF24
VLAD3
AE24
VLAD4
AE19
VLAD5
AF20
VLAD6
AD24
VLAD7
AF25
AE21
AF19
AE23
AF23
AF22
AD22
AF26
AD23
LVREF_NB
AF21
LCOMPP
AD19
AE26
AD25
TESTIN
AC26
AD26
DEBUG
AC17
B3
A3
A2
RSET
C4
A1
B1
C6
E7
R78
D3
1KR
SPCLK1
P2
C2
SPD1
P1
C1
FP/TV_D0
J1
FP/TV_D1
K2
FP/TV_D2
K3
FP/TV_D3
L4
FP/TV_D4
K1
FP/TV_D5
L2
FP/TV_D6
L3
FP/TV_D7
M4
FP/TV_D8
L1
FP/TV_D9
M2
FP/TV_D10
M3
FP/TV_D11
M1
P4
N1
N4
N3
R432 33R_B
P3
N2
D2
VCC2_5
VSS
VSS
L17
L16
C
VLAD[0..7] 18
VBE0# 18
VPAR 18
UPSTB 18
UPSTB# 18
DNSTB 18
DNSTB# 18
UPCMD 18
DNCMD 18
C457
X_102P_B
PWROK_NB# 17
DEV_RST# 15,20,21,23,25,28
SUSST# 17
R433 X_10KR_B
R434 10KR_B
R79 80.6RST
HSYNC 15
VSYNC 15
GUICLK 7
PIRQ#A 14,16,19
SPCLK1 15
DDCCLK 15
SPD1 15
DDCDATA 15
FP/TV_D0 15
FP/TV_D1 15
FP/TV_D2 15
FP/TV_D3 15
FP/TV_D4 15
FP/TV_D5 15
FP/TV_D6 15
FP/TV_D7 15
FP/TV_D8 14,15
FP/TV_D9 15
FP/TV_D10 15
FP/TV_D11 15
FPDET/TVCLKIN 15
FP/TV_HSYNC 15
FP/TV_VSYNC 15
FPCLK/TVCLKOUT 15
Place couples
VCC2_5 Cap to Gnd.
C445
0.1U25Y_B
C451
Place under NB
VCC2_5
FB37 30L-0603-500mA_B
FB38 30L-0603-500mA_B
FB39 30L-0603-500mA_B
90.9 Ohm
R11-909AT13-Y01
For K8M800.
C454
X_0.1U25Y_B
X_0.1U25Y_B
AGPNCOMP
AGPPCOMP
LCOMPP
VDDQ
D
C559
22P_B
VCC3
C403
0.1U25Y_B
C436 1U10Y_B
C421 1U10Y_B
300RST
VCC2_5
VDDQ
K8M800 will be 0.625V(R436=1KST)
R442 4.7KR_B
R80 60.4RST
R81 60.4RST
R435 360RST_B
NB to SB V-Link
Trace
Trace
Length
<6" VLAD[0..7]
<6"
<6"
<6"
<6"
Mismatch
<10mil <6"
<0.1"
<0.1"
<0.1"
<0.1"
<0.1"
Signal
UPSTB
UPSTB#
DNDTB
DNDTB#
UPCMD
DNCMD
VBE0#
VPAR
C560
22P_B
C561
22P_B
In Bottom Side
C406
X_0.1U25Y_B
VCC2_5
C589
1U10Y_B
MSI
Title
Size Document Number Rev
Date: Sheet of
C417
0.1U25Y_B
C590
X_0.1U25Y
change 5020
to 5010
MICRO-STAR INt'L CO., LTD.
North Bridge K8M800 2/3
MS-7056
VCC2_5
R440
3KRST_B
R436
1KRST_B
Check R436
Value
W:S
20:5:10:5:20
5:10
5:10
5:10
5:10
5:10
AR 15
AG 15
AB 15
C418
X_0.1U25Y_B
C591
0.1U25Y_B
E
C452
0.1U25Y_B
LVREF_NB
C448
0.1U25Y_B
C430
X_0.1U25Y_B
C592
0.1U25Y_B
12 36 Wednesday, July 21, 2004
C431
0.1U25Y_B
0A
A
VSUSNB
C456
X_102P_B
4 4
3 3
2 2
1 1
AVDD1
RGBPLL
GND_RGBPLL
RGBPLL
GND_RGBPLL
DAC_PLL
GND_DAC
DAC_PLL
GND_DAC
VDDQ
A
AC25
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21
W15
W16
W17
W18
W21
W22
W23
W24
W25
W26
AB10
AB15
E25
E26
D5
A5
C5
B5
A6
B6
B2
C3
D4
A4
B4
A7
D7
V14
V15
V16
V17
B7
C7
R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17
V5
W5
AB2
AB3
AB4
AB5
AB6
AB9
U14C
VSUS15/VSUS25
AVDD1
AGND1
VCCPLL1/NC
VCCPLL2/NC
GNDPLL1/NC
GNDPLL2/NC
VCCPLL3/NC
GNDPLL3/NC
DACVDD/NC
GNDDAC1/NC
GNDDAC2/NC
VCCRGB/NC
GNDRGB/NC
NC
NC
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS/NC
VSS/NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K8M800
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA4
AA5
AB11
AB12
AB13
AB14
AB7
AB8
M8
N8
T2
T3
T4
T5
T8
T9
U2
U3
U4
U5
U8
U9
V10
V11
V12
V13
V2
V3
V4
V8
V9
W2
W3
W4
W9
Y3
Y4
Y5
AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26
F9
H10
H11
H12
H15
H16
H8
H9
J8
K19
L19
M19
P8
R19
R8
T19
U19
V18
V19
W10
W11
W12
W13
W14
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
AB16
AC8
AC22
AC23
AC24
AE2
AE5
AE8
AE11
AE14
AE17
AE20
AE22
AE25
VDDQ
VDDQ
B
K8T400M Power and Ground Connections
LAYOUT : Popualte caps on the bottom side of NB.
For K8M800 Only
CP23
CP24
CP25
CP26
RGBPLL
1 2
1 2
DAC_PLL VCC3
1 2
GND_DAC
1 2
AVDD1
VDDQ
FB30
0R
FB29
X_0R
FB27
X_0R
FB28
X_0R
VCC3
FB21
X_0R
Note: When use K8T800,
these power circuit for
GFX analog power should
be NOPOPed.
B
C
C422
102P_B
GND_RGBPLL
C411
102P_B
C122
102P
C
VDDQ
K8M800
C404
1U16Y0805_B
VDDQ
C429
0.1U25Y_B
C423
1U10Y_B
C412
1U10Y_B
C119
1U10Y
C405
0.1U25Y_B
C432
X_0.1U25Y_B
LAYOUT: Place caps on the bottom of NB
CB20
1U16Y0805_B
CB19
102P_B
CB7
102P
C414
X_0.1U25Y_B
C435
X_0.1U25Y_B
D
C415
X_0.1U25Y_B
C438
0.1U25Y_B
D
E
C425
X_0.1U25Y_B
C446
0.1U25Y_B
C426
X_0.1U25Y_B
C450
X_0.1U25Y_B
Title
Size Document Number R ev
Date: Sheet of
C428
0.1U25Y_B
C455
1U16Y0805_B
MICRO-STAR INt'L CO., LTD.
MSI
North Bridge K8M800 3/3
MS-7056
E
13 36 Wednesday, July 21, 2004
0A
5
4
3
2
1
+12V
VDDQ
VCC3
AGP8XDET_GC#
GGNT
ST1
WBF
SBA1
SBA3
SB_STBS
SBA5
SBA7
GAD30
GAD28
GAD26
GAD24
AD_STBS1
GC/BE#3
GAD22
GAD20
GAD18
GAD16
GFRAME
GTRDY
GSTOP
GPAR
GAD15
GAD13
GAD11
GAD9
GC/BE#0
AD_STBS0
GAD6
GAD4
GAD2
GAD0
AGPVREF_GC
AGP8XDET_GC#
3
GC/BE#[3..0] 12
FP/TV_ D 8 12,15
PIRQ#A 12,16,19
PCIRST# 16,28
GGNT 12 GREQ 12
DBIH 12
WBF 12
SB_STBS 12
AD_STBS1 12
GFRAME 12
GTRDY 12
GSTOP 12
GPAR 12
AD_STBS0 12
AGPVREF_GC 12
1 : 4X
0 : 8X
GAD[0..31] 12
SBA[7..0] 12
R125 10KR
GAD[0..31]
SBA[7..0]
GC/BE#[3..0]
Add-in Card Power
C298
X_33P
VDDQ
VCC3
3VDUAL
VCC5
VCC12
Imax
2.0A
6.0A
0.75A
2.0A
1.0A
V_Min V_MaxVUnits
1.425 1.575
3.15 3.45
3.15 3.45
4.75 5.25
11.4 12.6
PCB LAYOUT GIUDE
Signal
GD[8..15],GBE1 Shorter than 6" 5:20
AD_STBF0
AD_STBS0
GD[16..23],GBE2
GD[24..31],GBE3,
DBIL,DBIH
AD_STBF1
AD_STBS1
SBA[0..7] 5:20 Shorter than 6"
SB_STBF
SB_STBS
AGP Control Bus 5:20 Shorter than 6"
+12V
R132
1KR
G
Q15
B
MMBT3904
E C
2
Width:Spacing Length Range
5:20 GD[0..7],GBE0
25:5:25:5:25
Shorter than 6"
Shorter than 6" and
mismatch 5mil
5:20 Shorter than 6"
5:20 Shorter than 6"
25:5:25:5:25
25:5:25:5:25
VDDQ
R137
8.2KR
GPERR
D S
Q16
2N7002
R133
200RST
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number R ev
Date: Sheet of
Shorter than 6" and
mismatch 5mil
Shorter than 6" and
mismatch 5mil
VCC3
C109
0.1U25Y
AGP Slot 8X
MS-7056
1
C114
0.1U25Y
14 36 Wednesday, July 21, 2004
V
V
V
V
C118
1U10Y
0A
AGP PRO Connector
D D
C160
0.1U25Y
PIRQ#B 16,19
ST0 12 ST1 12
ST2 12
RBF 12
DBIL 12
SB_STBF 12
3VDUAL
AD_STBF1 12
GIRDY 12
GDEVSEL 12
GSERR 12
AD_STBF0 12
VDDQ
R144
3.32KRST
R142
1.47KRST
R145
1.02KRST
5
GCLK_SLOT 7
C C
B B
4X : 0.75V
8X : 0.35V
A A
VREF_CG
C163
1U10Y
GREQ
ST0
ST2
RBF
DBIL
SBA0
SBA2
SB_STBF
SBA4
SBA6
GAD31
GAD29
GAD27
GAD25
AD_STBF1
GAD23
GAD21
GAD19
GAD17
GC/BE#2
GIRDY
GDEVSEL
GPERR
GSERR
GC/BE#1
GAD14
GAD12
GAD10
GAD8
AD_STBF0
GAD7
GAD5
GAD3
GAD1
VREF_CG
D S
Q19
2N7002
VCC3
G
VDDQ
VCC
AGP1
B1
-OVRCNT
B2
5V
B3
5V
B4
USB+
B5
GND
B6
-INTB
B7
CLK
B8
-REQ
B9
3.3V
B10
ST0
B11
ST2
B12
-RBF
B13
GND
B14
RESERVED
B15
SBA0
B16
3.3V
B17
SBA2
B18
SB_STB
B19
GND
B20
SBA4
B21
SBA6
B22
RSVD/KEY
B23
GND/KEY
B24
AUX3V/KEY
B25
3.3V/KEY
B26
AD31
B27
AD29
B28
3.3V
B29
AD27
B30
AD25
B31
GND
B32
AD_STB1
B33
AD23
B34
VDDQ
B35
AD21
B36
AD19
B37
GND
B38
AD17
B39
C/-BE2
B40
VDDQ
B41
-IRDY
B42
AUX3V/KEY
B43
GND/KEY
B44
RSVD/KEY
B45
3.3V/KEY
B46
-DEVSEL
B47
VDDQ
B48
-PERR
B49
GND
B50
-SERR
B51
C/-BE1
B52
VDDQ
B53
AD14
B54
AD12
B55
GND
B56
AD10
B57
AD8
B58
VDDQ
B59
AD_STB0
B60
AD7
B61
GND
B62
AD5
B63
AD3
B64
VDDQ
B65
AD1
B66
VREF_CG
SLOT-AGP1.5
VCC3
+12V
R140
1KR
AGP8XDET_GC#
D S
G
1 : 4X
0 : 8X 1 : 4X
4
-TYPEDET
RESERVED
RESERVED
-SB_STB
RSVD/KEY
GND/KEY
RSVD/KEY
3.3V/KEY
-AD_STB1
RSVD/KEY
GND/KEY
RSVD/KEY
3.3V/KEY
-AD_STB0
VREF_GC
R139
6.49KR1%
Q18
2N7002
R138
3KRST
12V
USB-
GND
-INTA
-RST
-GNT
3.3V
ST1
-PIPE
GND
-WBF
SBA1
3.3V
SBA3
GND
SBA5
SBA7
AD30
AD28
3.3V
AD26
AD24
GND
C/-BE3
VDDQ
AD22
AD20
GND
AD18
AD16
VDDQ
-FRAME
-TRDY
-STOP
-PME
GND
PAR
AD15
VDDQ
AD13
AD11
GND
AD9
C/-BE0
VDDQ
AD6
GND
AD4
AD2
VDDQ
AD0
AGP8XDET#
0 : 8X
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
AGP8XDET# 12
A
B
C
D
E
F1
CB1
VGA1A
21
4 4
AR 12
AG 12
AB 12
R34
75RST
R35
75RST
R33
75RST
FB14 30L-0603-500mA
FB15 30L-0603-500mA
FB16 30L-0603-500mA
Change value form
22p to 15p in 0B
to MVT
C27
15P
C28
15P
C29
15P
1
2
3
4
5
6
11
7
12
8
13
9
14
10
15
23
0.1U25Y CB29
D5
3
AB
1
AG
2
AR
3 3
3
1
2
445
DN006S
7
VCC
7
8
8
6
VSYNC
6
HSYNC
5
R36
4.7KR
R39
4.7KR
VCC
C44
0.1U25Y
VSYNC 12
HSYNC 12
6723-VGA-COM
R26 2 7R
R25 2 7R
放成一列,若 驗證
沒問題再改成 排容
0.1U25Y
C33
22P
1.1A-microSMD110-S
POLY SWITCH
C31
C32
22P
22P
0A VGA&
22P
C30
22P
EMI
VCC
R24
1.8KR
VCC
R27
1.8KR
DDCDATA 12
DDCCLK 12
1.The 5V traces should be 20 mils to VGA/DFP Trace Note:
U7
51
PD15
50
PD14
47
PD13
46
45
44
43
42
41
38
37
36
35
34
31
30
25
27
20
21
10
12
14
16
19
7
55
53
29
54
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
XCLK
PCLK
SBC
SBD
DACA
DACB
DACC
DACD
RESET#
RSET
CONF_XLT
ADDR
DE
TESTMODE
VT1622AM
VCCBGAP
GNDBGAP
B
SPD1 12
FP/TV_D11
FP/TV_D10
FP/TV_D9
FP/TV_D8
FP/TV_D7
FP/TV_D6
FP/TV_D5
FP/TV_D4
FP/TV_D3
FP/TV_D2
FP/TV_D1
FP/TV_D0
FPDE
R53 33R
SPCLK1
SPD1
CVBS
C
Y
75RST
DEV_RST# 12,20,21,23,25,28
R19 4.64KRST
22P C595
CONF_XLT
ADDR
FP/TV_D11 12
FP/TV_D10 12
FP/TV_D9 12
FP/TV_D8 12,14
FP/TV_D7 12
FP/TV_D6 12
FP/TV_D5 12
FP/TV_D4 12
FP/TV_D3 12
2 2
FP/TV_D2 12
FP/TV_D1 12
FP/TV_D0 12
FPCLK/TVCLKOUT 12
FPDET/TVCLKIN 12
SPCLK1 12
R17
R16
75RST
75RST
1 1
R59 10KR
R57 10KR
A
VSYNC
HSYNC
BCO
CSO/HSO
VSO
VCCPLL
VCCOSC
VCCDAC
VCCDAC
VCC33
VCC33
VCC33
VCC25
VCC25
VCC25
VCC25
GNDPLL
GNDOSC
GNDDAC
GNDDAC
GND
GND
GND
GND
GND
GND
GND
COMP
22
23
2
XI
3
XO
BCO
61
CSO
58
VSO
60
VDDA1
64
1
5
9
13
VDDA2
26
40
57
VCC3
18
32
48
59
AVDD2_5
63
4
8
11
15
24
39
56
17
33
49
62
52
NC
C38 0.1U25Y
6
C must between pin5 & 6 with
wide trace and as close as
possible to VT1622
C48 10P
C53 10P
C51 10P
0.1U25Y_B C399
0.1U25Y_B C395
0.1U25Y C36
0.1U25Y C37
0.1U25Y_B C392
0.1U25Y C56
0.1U25Y C68
0.1U25Y_B C402
0.1U25Y_B C400
0.1U25Y C65
0.1U25Y_B C401
0.1U25Y C69
VDDA2
FP/TV_VSYNC 12
FP/TV_HSYNC 12
FP/TV_D4
FP/TV_D5
FP/TV_D6
FP/TV_D7
FP/TV_D8
FP/TV_D9
FP/TV_D10
C
T* Frequency
Recheck in 0A
R517 4.7KR
R72 4.7KR
R518 4.7KR
R70 4.7KR R18
R519 4.7KR
R520 4.7KR
R71 4.7KR
Y2
14M-32pf-HC49S-D
C39
39P
VCC3
C40
39P
ADDR CONF_XLT
VDDA2
VDDA2
VDDA2
SPCLK1
SPD1
R66
X_10KR
R61
10KR
AVDD2_5
FB17
300L-0603-300mA
FB18
X_300L-0603-300mA
VDDA1
EC4
X_C10U16EL
CP14
C49
1U10Y
VDDA2
1 2
EC5
C10U16EL
C50
1U10Y
VGND
FB
VT1621M PCB Layout Guide
C8 X_22P
CVBS
D
S
G
D1 X_BAV99-S-SOT23
D
S
G
D2 BAV99-S-SOT23
C CO
D
S
G
D3 BAV99-S-SOT23
VCC3
R44 10KR
R46 10KR
C54
X_0.1U25Y
C52
X_0.1U25Y
VCC3 VCC3
R48
X_10KR
R52
10KR
MSI
Title
Size Document Number Rev
D
Date: Sheet of
L3 X_1.8uH-0805-50mA
C14
X_270P
C9
X_330P
Add Gnd
in 0B
C10 X_47P
L1 1.8uH-0805-50mA
C15
X_150P
C11
270P
Add Gnd
in 0B
C12 X_47P
L2 1.8uH-0805-50mA
C16
X_150P
C13
270P
Add Gnd
in 0B
J4
SVIDEO_VGA
567
MICRO-STAR INt'L CO., LTD.
VGA Connector / TV-Out
MS-7056
E
FB
GND
CVBSO
YO Y
CO
YO
3 4
1 2
0A
15 36 Wednesday, July 21, 2004
A
AD[31..0] 19,20,23
4 4
3 3
C_BE#[3..0] 19,20,23
2 2
1 1
AD[31..0]
C_BE#[3..0]
FRAME# 19,20,23
DEVSEL# 19,20,23
IRDY# 19,20,23
TRDY# 19,20,23
STOP# 19,20,23
SERR# 19,23
PAR 19,20,23
PERR# 19,20,23
PCIRST# 14,28
PIRQ#A 12,14,19
PIRQ#B 14,19
PIRQ#C 19,20
PIRQ#D 19,23
PREQ#1 19
PREQ#2 19
PREQ#3 20
PREQ#4 23
PGNT#1 19
PGNT#2 19
PGNT#3 20
PGNT#4 23
A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE#0
C_BE#1
C_BE#2
C_BE#3
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR
PERR#
PCIRST#
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#E
PIRQ#F
PIRQ#G
PIRQ#H
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5
PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5
G2
AD0
J4
AD1
J3
AD2
H3
AD3
F1
AD4
G1
AD5
H4
AD6
F2
AD7
E1
AD8
G3
AD9
E3
AD10
D1
AD11
G4
AD12
D2
AD13
D3
AD14
F3
AD15
K3
AD16
L3
AD17
K2
AD18
K1
AD19
M4
AD20
L2
AD21
N4
AD22
L1
AD23
M2
AD24
M1
AD25
P4
AD26
N3
AD27
N2
AD28
N1
AD29
P1
AD30
P2
AD31
E2
CBE0
C1
CBE1
L4
CBE2
M3
CBE3
J1
FRAME
H2
DEVSEL
J2
IRDY
H1
TRDY
K4
STOP
C2
SERR
F4
PAR
C3
PERR
R1
PCIRST
A4
INTA
B4
INTB
B5
INTC
C4
INTD
D4
INTE
E4
INTF
A3
INTG
B3
INTH
A5
REQ0
B6
REQ1
C5
REQ2
D5
REQ3
P3
REQ4
R3
REQ5
A6
GNT0
D6
GNT1
C6
GNT2
E5
GNT3
R4
GNT4
R2
GNT5
GNDA1GNDA2GND
B1
B2
GND
GNDE8GND
F25
H10
H11
VCC33H9VCC33
GND
GND
J21
J25
H23
B
VCC33
GND
B
H12
VCC33
VCC3
R19
VCC33J8VCC33K8VCC33L8VCC33M8VCC33N8VCC33P8VCC33R8VCC33
USBGND
USBGND
USBGND
USBGND
USBGND
A17
A19
A21
B13
B15
USBGND
B17
B19
USBGND
USBGND
A15
A13
T19
U8
VCC33T8VCC33
VCC33
USBGND
USBGND
USBGND
B21
C13
U19
VCC33
VCC33V8VCC33
USBGND
USBGND
C14
C15
V19
V21
VCC33
USBGND
USBGND
C16
C17
W10
VCC33W9VCC33
USBGND
USBGND
C18
C19
W11
W17
VCC33
VCC33
USBGND
USBGND
C20
C21
W18
W19
VCC33
VCC33
USBGND
USBGND
D13
D15
W21
Y21
VCC33
VCC33
USBGND
USBGND
D17
D19
W8
VCC33
USBGND
USBGND
E13
D21
USBGND
USBGND
E15
E17
C
KBCK/KA20G
KBDT/KBRC
MSDT/IRQ12
USBGND
USBGND
E19
E21
H13
C
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBSUS25
PLLVDDA
PLLVDDA
PLLGNDA
PLLGNDA
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
USBP3+
USBP3-
USBP4+
USBP4-
USBP5+
USBP5-
USBP6+
USBP6-
USBP7+
USBP7-
USBOC0
USBOC1
USBOC2
USBOC3
USBOC4
USBOC5
USBOC6
USBOC7
USBCLK
USB REXT
UDPWR
UDPWREN
MSCK/IRQ1
USBGND
USBGND
USBGND
USBGND
H15
H16
H14
USBGND
USBGND
H18
H17
U29A
A22
B22
C22
D22
E22
F22
J13
J14
J15
J16
J17
J18
C24
A23
B23
D23
C23
E20
D20
A20
B20
E18
D18
A18
B18
D16
E16
A16
B16
D14
E14
A14
B14
C26
D24
B26
C25
B24
A24
A26
A25
E23
USBREXT
B25
D26
D25
W3
V1
W1
W2
VT8237-CD
CB11
X_0.1U25Y
USBVCCA
USBGNDA
USBP0
USBN0
USBP1
USBN1
USBP2
USBN2
USBP3
USBN3
USBP4
USBN4
USBP5
USBN5
USBP6
USBN6
USBP7
USBN7
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USBCLK_SB
R254
5.11KST
R255 10KR
EC41
+
X_C10U16EL
C522
0.1U25Y_B
near SB
VCC2_5
CB14
0.1U25Y
R252
820RST
KBCLK# 25
KBDAT# 25
MSCLK# 25
MSDAT# 25
D
3VDUAL
CB12
0.1U25Y
VSUS2_5
CB13
X_0.1U25Y
VCC3
C510
0.1U25Y_B
U29_1
8X
MSI
AGP
X_E31-0400482-A58
E31-0400483-A58
D
C513
0.1U25Y_B
USBP0 24
USBN0 24
USBP1 24
USBN1 24
USBP2 24
USBN2 24
USBP3 24
USBN3 24
USBP4 24
USBN4 24
USBP5 24
USBN5 24
USBP6 24
USBN6 24
USBP7 24
USBN7 24
USB_OC#1 24
USB_OC#2 24
USB_OC#3 24
USBCLK_SB 7
C512
X_0.1U25Y_B
E
VCC3
X_0.1U25Y CB18
PIRQ#D
PIRQ#B
PIRQ#A
PIRQ#C
FRAME#
IRDY#
TRDY#
DEVSEL#
PREQ#4
STOP#
SERR#
PERR#
PREQ#3
PREQ#2
PREQ#0
PREQ#1
PREQ#5
X_0.1U25Y CB17
PIRQ#H
PIRQ#G
PIRQ#F
PIRQ#E
PGNT#4
PGNT#5
PGNT#0
PGNT#2
PGNT#1
PGNT#3
RN89
8P4R-2.7KR
1 2
3 4
5 6
7 8
RN92
8P4R-2.7KR
1 2
3 4
5 6
7 8
RN91
8P4R-2.7KR
1 2
3 4
5 6
7 8
RN88
8P4R-2.7KR
1 2
3 4
5 6
7 8
R340 10KR
RN94
8P4R-2.7KR
1 2
3 4
5 6
7 8
R341 10KR
R368 10KR
RN86
8P4R-2.7KR
1 2
3 4
5 6
7 8
VCC
VCC3
C532
0.1U25Y_B
In Bottom Side
C529
C530
X_0.1U25Y_B
MSI
Title
Size Document Number Rev
Date: Sheet of
0.1U25Y_B
CB25
CB26
X_0.1U25Y_B
CB27
X_0.1U25Y_B
0.1U25Y_B
MICRO-STAR INt'L CO., LTD.
South Bridge VT8237CD 1/3
MS-7056
16 36 Wednesday, July 21, 2004
E
CB28
X_0.1U25Y_B
0A
A
J10
J11
J12
VDDJ9VDD
GNDATS
GNDATS
AB14
AC14
VDD
GNDATS
GNDATS
AD12
AD13
VDDK9VDDL9VDD
GNDATS
GNDATS
AD14
AD15
L18
VDD
GNDATS
AD16
PDREQ 22
PDDACK# 22
PDIOR# 22
PDIOW# 22
PIORDY 22
PDCS#1 22
PDCS#3 22
IRQ14 22
SDREQ 22
SDDACK# 22
SDIOR# 22
SDIOW# 22
SIORDY 22
SDCS#1 22
SDCS#3 22
IRQ15 22
STXP_1
STXN_1
SRXN_1
SRXP_1
CP20
FB36
X_601S
CP19
PDA0 22
PDA1 22
PDA2 22
SDA0 22
SDA1 22
SDA2 22
FB35
X_601S
PDD[15..0]
SDD[15..0]
R270 X_360RST
VT8237
near chipset
near chipset
1 2
C517
0.1U25Y_B
1 2
PDD[15..0] 22
4 4
SDD[15..0] 22
3 3
Using external PHY
2 2
VCC2_5
1 1
SDDACK#
X_0.1U25Y C318
103P_B C518
103P_B C521
122P_B C523
122P_B C527
+2.5VSATA
PDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
PDCS#1
PDCS#3
PDA0
PDA1
PDA2
IRQ14
SDREQ
SDIOR#
SDIOW#
SIORDY
SDCS#1
SDCS#3
SDA0
SDA1
SDA2
IRQ15
SIDEVREF
SIDECOMP
STXP1
STXN1
SRXN1
SRXP1
C520
1U10Y_B
PDD0
AA22
PDD1
Y24
PDD2
AA26
PDD3
AA25
PDD4
AB26
PDD5
AC26
PDD6
AC23
PDD7
AD25
PDD8
AD26
PDD9
AC24
PDD10
AC25
PDD11
AB24
PDD12
AB23
PDD13
AA24
PDD14
Y26
PDD15
AA23
Y23
V24
W26
Y25
Y22
V22
V23
W23
V25
W24
AD24
SDD0
AC20
SDD1
AB20
SDD2
AC21
SDD3
AE18
SDD4
AF18
SDD5
AD18
SDD6
AD19
SDD7
AF19
SDD8
AE20
SDD9
AF20
SDD10
AD20
SDD11
AE21
SDD12
AF21
SDD13
AD21
SDD14
AD22
SDD15
AF22
AD17
AD23
AF23
AE23
AF17
AF25
AF26
AF24
AC22
AE24
AE26
AC19
AB21
AB13
AC13
AF13
AE13
AB15
AC15
AF15
AE15
W12
W13
W14
W15
W16
AC17
AC11
AB17
AB11
CM2
4.7U10Y0805_B
GNDSATA
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDDACK
PDIOR
PDIOW
PDRDY
PDCS1
PDCS3
PDA0
PDA1
PDA2
IRQ14
SDD0/TBC1
SDD1/VALID
SDD2
SDD3/RXD2
SDD4/RXD3
SDD5/RXD4
SDD6/RBC0
SDD7/RBC1
SDD8/RXD5
SDD9/RXD6
SDD10/RXD7
SDD11/RXD8
SDD12/RXD9
SDD13/TXD0
SDD14/TXD1
SDD15/TXD2
SDDRQ/RXD1
SDDACK/TBC0
SDIOR/TXD4
SDIOW/TXD3
SDRDY/RXD0
SDCS1/TXD8
SDCS3/TXD9
SDA0/TXD6
SDA1/TXD5
SDA2/TXD7
IRQ15
SVREF
SCOMPP
STXP1
STXN1
SRXN1
SRXP1
STXP2
STXN2
SRXN2
SRXP2
VDDATS
VDDATS
VDDATS
VDDATS
VDDATS
VDDAS
VDDAS
VDDAS
VDDAS
SATA => (W:S=100:6:8:6:100)
STXN STXP
SRXP SRXN
A
Signal
Trace
Length
Length
Mismatch
<5mil <5mil
M9
M18
VDD
GNDATS
AE12
AE14
N18
VDD
VDDN9VDD
GNDATS
GNDATS
GNDATS
AF12
AE16
P18
VDDP9VDD
GNDATS
GNDATS
AF14
AF16
B
R18
VDDR9VDD
AC16
B
VDDT9VDD
GNDAS
GNDAS
AC12
T18
GNDAS
AB16
AB12
U18
VDDU9VDD
GNDAS
VDDV9VDD
V10
V11
V12
V13
V14
VDD
VDD
VDD
VDD
GNDF6GNDF7GNDJ5GNDK5GNDP5GND
VT8237
VT8237
3VDUAL VCC2_5
VSUS2_5
AA4
AB4
AB5
V15
V16
VDD
VDD
GND
R5
L11
AB6
V17
V18
VDD
VDD
VSUS33
VSUS33
VSUS33
VSUS33
VSUS25T4VSUS25
ACBITCLK
ACSDIN0
ACSDIN1
ACSDIN2
ACSDIN3/SLP_BTN
ACSYNC
ACSDO
ACRST
BATLOW
CPUMISS
SUSST1
AOLGP/THRM
EXTSMI
SMBALRT
PWRBTN
PWROK
CLKRUN
CPUSTP
PCISTP
INTRUDER
SUSCLK
SMBCK1
SMBDT1
SMBCK2
SMBDT2
GPIOA/Strap1
GPIOB/Strap2
GPIOC/Strap0
GPIOD/Strap3
SERIRQ
VDDA0
GNDA0
SREXT
SXO/Strap4
SXI/Strap5
VDDA33
GNDA33
GND
GND
GND
GND
GND
GND
GND
GND
GND
L13
L14
L15
L16
L12
M11
M12
M13
M14
PDDACK#
R242 10KR
1 - Disable external SATA PHY
PDCS#1
R248 10KR
R247 X_10KR
SATA master/slave mode
1 - Disable 0 - Enable
U4
PME
RING
SUSA
SUSB
SUSC
GPI0
GPI1
GPO0
GPO1
SPKR
OSC
TPO
TEST
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M15
LID
K18
U29B
T1
U3
V2
U1
V3
T2
U2
T3
W4
V4
Y1
Y2
Y3
Y4
AA1
AB1
AC1
AD2
AF1
AB7
AC7
AD6
AE1
AB3
AC4
AB2
AC3
AD1
AA2
AD3
AF2
AE2
AC2
AA3
AE3
AE5
AD5
AF5
AC6
AD9
AF8
AB8
AF9
AE9
AC10
AB10
AD11
AE10
AF10
AE11
AF11
W5
V5
M16
N11
N12
N13
N14
N15
N16
GND
VT8237-CD
VCC3
VCC3
ACSYNC
ACSDO
ACRST
C
VCC2_5
PCI_PME#
BATLOW#
CPUMISS
RING#
SUSST#
THRM#
CD_SMI#
SMB_ALERT#
ATADET1
PWRBTN#_S
PWROK_NB#
CLKRUN#
CPUSTP#
PCISTP#
INTRUDER#
SUSCLK
SMBCLK1
SMBDATA1
SMBCLK2
SMBDATA2
BB_SMB_SEL
SUSB#
SUSC#
THERM_ALERT#
ATADET0
SUSLED
GPO1
GPIOA
GPIOB
GPIOC
GPIOD
SERIRQ
SPKR
SB_OSC14
TPO
TEST
VDDA0
SREXT
R303 4.75KR1%
SXO
SXI
VDDA33
C
AC_BITCLK
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SDIN3
RN95
7
8
5
6
3
4
RN95 Remove
1
2
from 0B BOM
X_8P4R-22R
SMBCLK1 7,8,21,23,28
SMBDATA1 7,8,21,23,28
SUSB# 25,28,32
SUSC# 28
THERM_ALERT# 21
ATADET0 22
SERIRQ 25
SPKR 26
SB_OSC14 7
VCC2_5
C524
0.1U25Y_B
Solve EYE pattern
Issue
FB24 X_601S
1 2
C322
0.1U25Y
SXO
SXI
1 2
C324
15P
VT8237
8
STXP_1
STXN_1
SRXN_1
SRXP_1
1
2
3
4
5
6
7
9
1U10Y CB10
0.1U25Y CB9
AC_BITCLK 31
AC_SDIN0 31
AC_SDIN1 21
AC_SYNC 21,31
AC_SDOUT 21,31
AC_RST# 21,31
PCI_PME# 19,20,23
RING# 25
SUSST# 12
CD_SMI# 30
ATADET1 22
PWROK_NB# 12
VCC3
CP6
X2
T* Frequency
Recheck in 0A
YCRY25H
C323
15P
SATA1
SATACONN
D
VT8237
*"ACSYNC" => LPC FWH Command
0 - Enable FWH *"SA[17:16]" => LDT Fre quency
1 - Disable FWH(Default)
ACSYNC
R342 4.7KR
R380 X_4.7KR
*"ACSDO" => AutoReboot
0 - Enable
1 - Disable(Default)
ACSDO
R379 4.7KR
R344 X_4.7KR
THERM_ALERT#
INTRUDER#
AC_SDIN0
R467 X_4.7KR_B
AC_SDIN2
R343 X_4.7KR
AC_SDIN1
R370 4.7KR
AC_SDIN3
R466 4.7KR_B
TEST
R293 4.7KR
CLKRUN#
R463 4.7KR_B
SUSLED
R338 X_4.7KR
SUSCLK
CD_SMI#
RING#
CPUMISS
BATLOW#
PCI_PME#
THRM#
SUSST#
GPO1
PWBTIN#
PWROK_NB#
SMB_ALERT#
BB_SMB_SEL
SUSB#
SUSC#
ATADET0
ATADET1
SERIRQ
SPKR
CPUSTP#
PCISTP#
TPO
*"SPKR" => CPU Freq. Adjust Setting
VT8235
SMBCLK2
SMBDATA2
SMBDATA1
SMBCLK1
C349
C350
X_47P
X_47P
1
3
5
7
1
3
5
7
1
3
5
7
R468 4.7KR_B
R339 X_4.7K
R374 X_4.7K
R375 4.7K
R464 4.7K_B
1
3
5
7
1 - Disable (Default)
0 - Enable
8
6
4
2
POS STR STD
SUSA#
SUSB#
SUSC#
L
H
H
D
E
00 - 200MHz (Default)
01 - 400MHz
10 - 600MHz
11 - 800MHz
*"SA18" => LDT Width
0 - 8-Bit (Default)
1 - 16-Bit
*"SA19" => Fast command
0 - Disable (Default)
1 - Enable
VBAT
GPIOD
GPIOC
GPIOA
GPIOB
RN102
8P4R-4.7KR
1
3
5
7
Strapping
*"PDA1/SDA1" => External loop test mode
0 - Disable (Default)
1 - Enable
*"PDA2/SDA2" => ROMSIP Select
0 - Disable
1 - Enable(Default)
*"-SDCS3" => Test Mode Select
0 - Disable (Default)
1 - Enable
*"EEDI/-SDCS1" => EEPROM Select
0 - BIOS Porting - ACR
1 - External EEPROM (On-board)(Default)
R240 1KR
(VD[5])
R244 1KR
R358 4.7KR
R373 1MR
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
R301 4.7KR
VCC3
VCC3
3VDUAL
RN93
8P4R-4.7KR
RN104
8P4R-4.7KR
RN90
8P4R-4.7KR
VCC3
RN87
8P4R-4.7KR
(VD[6])
(VD[7])
7
3VDUAL
5
3
1
RN103
8P4R-1KR
VCC3
VCC3
L
L
L
L
H
L
MSI
Title
Size Document Number R ev
Date: Sheet of
R246 1KR
R243 X_1KR
R241 1KR
R372
68R
C348
X_0.1U25Y
MICRO-STAR INt'L CO., LTD.
South Bridge VT8237CD 2/3
MS-7056
E
(VD[2])
(VD[3])
2
4
6
8
PDA0
PWBTIN# PWRBTN#_S
(VD[1:0])
SA17
SA18
SA16
SA19
PDA1
PDA2
PDCS#3
17 36 Wednesday, July 21, 2004
(VD[1])
(VD[2])
(VD[0])
(VD[3])
VT8237
VT8237
VT8237
VT8237
(VD[4])
PWBTIN# 26
0A
A
N21
N22
N23
N24
N25
N26
P22
P23
P24
P25
VCCVK
VCCVK
GND
GND
R12
VCCVK
GND
R14
R13
VCCVK
VCCVK
GND
GND
R15
R16
P26
VCCVK
GND
R21
L21
K21
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
VD9
VD10
VD11
VD12
VD13
VD14
VD15
VBE
UPCMD
DNCMD
UPSTB
UPSTB
DNSTB
DNSTB
VPAR
VLREF
VCOMPP
VCLK
VIOUT
VIIN
LAD0
LAD1
LAD2
LAD3
LFRM
LREQ0
LREQ1
PWRGD
RSMRST
VBAT
RTCX1
RTCX2
L23
VCCVK
VCCVK
VCCVK
VCCVK
GND
GND
GND
P11
P12
P13
X_0.1U25Y_B
VCCVK
VCCVK
VCCVK
GND
GND
GND
P14
P15
P16
R11
In Bottom Side
C508
VLAD[0..7]
4 4
VBE0# 12
UPCMD 12
DNCMD 12
UPSTB 12
UPSTB# 12
3 3
2 2
ALL_PWRGD
1 1
DNSTB 12
DNSTB# 12
VPAR 12
R453 360RST
VCOMPP_SB W:S 10:10
VCLK 7
LPC_AD0 25
LPC_AD1 25
LPC_AD2 25
LPC_AD3 25
LPC_FRAME# 25
LPC_REQ# 25
RSMRST# 28
1 2
C341
3 4
15P
YCRY32.768C
Y6
Fix 32.768K frequency, change
C340 and C341 to 15P in 0B BOM.
VLREF_SB
VCOMPP_SB
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_REQ#
ALL_PWRGD
RSMRST#
VBAT
X1
CM1
4.7U10Y0805_B
VLAD0
VLAD1
VLAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
VBE0#
UPCMD
DNCMD
UPSTB
UPSTB#
DNSTB
DNSTB#
VPAR
VCLK
C344
X_103P
C340
15P
A
X2
VCC2_5
H25
G26
K26
J23
F26
G25
K22
K24
E24
G23
L26
L25
E26
E25
L24
M26
G24
K23
K25
J26
J24
H26
H24
F24
H22
J22
L22
F23
G22
AD8
AF7
AE7
AD7
AF6
AE6
AE8
AC5
AD4
AF4
AE4
AF3
C504
X_0.1U25Y_B
M21
M22
M23
VCCVK
VCCVK
VCCVK
VCCVK
GND
GND
GND
GND
T11
T12
T13
X_0.1U25Y_B
M24
M25
VCCVK
GND
T15
T14
B
L19
VCCVK
VCCVK
GND
GND
T16
B
M19
N19
VCCVK
GND
W22
W25
C514
0.1U25Y_B 0.1U25Y_B
P19
VCCVK
VCCVK
GND
GND
AA21
GND
AB19
GND
AB22
VSUS2_5
GND
AB25
AC18
D12
E12
MIISUS25
GND
GND
GND
AE17
AE19
AE22
C515
X_0.1U25Y_B
D9
MIISUS25
GND
GND
GND
AA9
AE25
AB18
3VDUAL VCC2_5
E11
E10
MIIVCC
MIIVCCE9MIIVCC
MIIVCC
AGPBZ/GPI6
APICD0/APICCS
APICD1/APICACK
GND
GND
GND
GND
T21
K19
AA10
C519 C506
X_0.1U25Y_B
U29C
A11
MCRS
B11
MCOL
C11
MTXENA
A10
MTXD0
B10
MTXD1
B9
MTXD2
A9
MTXD3
C10
MTXCLK
D10
MRXER
C9
MRXCLK
D8
MRXDV
C8
MRXD0
B8
MRXD1
A8
MRXD2
C7
MRXD3
A7
MDCK
B7
MDIO
D7
PHYRST
D11
EECS
B12
EEDO
A12
EEDI
C12
EECK
E7
RAMVCC
E6
RAMGND
U24
FERR
U26
A20M
T24
IGNNE
R26
INIT
T25
INTR
T26
NMI
U25
SMI
R24
STPCLK
V26
SLP
R22
GHI
P21
DPSLP
AC9
VGATE
AC8
VIDSEL
AB9
VRDSLP
AD10
R23
PCICLK
U23
APICCLK
R25
T23
T22
PLLVCC
U22
PLLGND
VT8237-CD
Impact VGA Display.
VLREF_SB W:S 20:20
C525
0.1U25Y_B
C
MTXEN
MMDIO
MII_EEDI
+2.5VRAM
GND_RAM
FERR#
A20M#
IGNNE#
CPUINIT#
INTR
NMI_SB
SMI#
STPCLK#
-LDTSTOP
GHI#
BB_INTR#
VGATE
SATAACT#
VRDSLP
AGPBZ#
SB_PCLK
APICCLK
APICD0#
APICD1#
+2.5VSBPLL
GND_SBPLL
C526
X_0.1U25Y_B
C
VCC2_5
C257
X_1U16Y0805
Place on V-Link Trace
VCC2_5 plane.
R297 2.2R
CB15
1U10Y
SB_PCLK 7
APICCLK 7
CP17
CB22
0.1U25Y
X_601S
X_601S
CP18
VLREF_SB is 0.3V
VCC2_5
Ref to VIA AN305 Doc.
K8M800 will be 0.3V(R454=470RST)
R455
360RST_B
VLR EF_SB
R454
49.9RST_B 0.1U25Y_B
vdd/8=0.3volt
1 2
FB33
FB34
1 2
C503
0.1U25Y_B
C502 C511
C208
X_1U16Y0805
VCC2_5
-LDTSTOP 5,11
SATAACT# 26
VCC2_5
D
C162
X_1U16Y0805
5VSB
BAT1
D
R257
1KR
R253
3KRST
E
ALL_PWRGD
VGATE
VCC3
R376 X_4.7K
R460 4.7KR_B
MII Lan
MMDIO
MII_EEDI
MTXEN
IGNNE#
SMI#
A20M#
CPUINIT#
STPCLK#
INTR
NMI_SB
FERR#
-LDTSTOP
APICD0#
APICD1#
APICCLK
BB_INTR#
GHI#
AGPBZ#
SATAACT#
NOTEBOOK SIGNALS
1 2
R256
1KR
Title
Size Document Number Rev
Date: Sheet of
VRDSLP
D11
BAT54C
3
MSI
R291 X_1.5KR
R288 10KR
R287 X_10KR
R290 X_10KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R457 1KR_B
R245 X_4.7KR
R249 330R
R250 330R
R456 X_4.7KR_B
R452 4.7KR_B
R451 4.7KR_B
R459 4.7KR_B
R462 4.7KR_B
R461 4.7KR_B
JBAT1
YJ103
1
3
R258
1KR
RN70
X_8P4R-680
RN74
X_8P4R-680
2
3VDUAL
VCC3
C351
X_10U10Y0805
VT8237
*"EEDI" => Eliminate Lan EEPROM
0/1:Disable/Enable
VCC3
VBAT1_1
YBA3V
VBAT
C313
103P
MICRO-STAR INt'L CO., LTD.
South Bridge VT8237CD 3/3
MS-7056
E
VBAT
0A
18 36 Wednesday, July 21, 2004
5
PCI Connectors
VCC3
D D
PIRQ#B 14,16
PIRQ#D 16,23
PCICLK1 7
PREQ#1 16
C C
IRDY# 16,20,23
DEVSEL# 1 6,20,23
PERR# 16,20,23
SERR# 16,23
B B
EC24
A A
+
X_CD1000U6.3EL15
-12V
PIRQ#B PIRQ#C
PIRQ#D
PCICLK1
PREQ#1
AD31
AD29
AD27
AD25
C_BE#3
AD23
AD21
AD19
AD17
C_BE#2
IRDY#
DEVSEL#
PLOCK#
PERR#
SERR#
C_BE#1
AD14
AD12
AD10
AD7
AD5
AD3
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B1
B2
B3
B4
B5
B6
B7
B8
B9
PCI1
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RSVD2
PRSNT2#
GND
GND
RSVD5
GND
CLK
GND
REQ#
+5V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
GND
AD12
AD10
GND
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V
ACK64#
+5V
+5V
YSLOT120
TRST#
+12V
TMS
INTA#
INTC#
RSVD1
RSVD3
GND
GND
RSVD4
RST#
GNT#
GND
RSVD6
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL#
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
AD15
+3.3V
AD13
AD11
GND
C/BE0#
+3.3V
GND
REQ64#
A1
A2
A3
A4
TDI
A5
+5V
A6
A7
A8
+5V
A9
A10
+5V
A11
A12
A13
A14
A15
A16
+5V
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
PAR
A44
A45
A46
A47
A48
A49
AD9
A52
A53
A54
AD6
A55
AD4
A56
A57
AD2
A58
AD0
A59
+5V
A60
A61
+5V
A62
+5V
IDSEL= AD16
INT#= A, B, C, D
VCC3 VCC
C96
0.1U25Y
5
C112
0.1U25Y
C113
X_0.1U25Y
C126
X_0.1U25Y
VCC3
+12V VCC VCC
PIRQ#A
3VDUAL
PGNT#1
PCI_PME#
AD30
AD28
AD26
AD24
AD22
AD20
AD18
AD16
FRAME#
TRDY#
STOP#
PAR
AD15
AD13
AD11
AD9
C_BE#0 AD8
AD6
AD4
AD2
AD0 AD1
4
AD[31..0] 16,20,23
C_BE#[3..0] 16,20,23
R527 33R
R110 3 00RST
3VDUAL
C86
X_0.1U25Y
4
AD[31..0]
C_BE#[3..0]
PIRQ#A 12,14,16
PIRQ#C 16,20
SLOT_RST#
PGNT#1 16
PCI_PME# 17,20,23
AD16
FRAME# 16,20,23
TRDY# 16,20,23
STOP# 16,20,23
PAR 1 6,20,23
IR 30
OS_SEL 30
5VSB
OS_SEL ACTIVE
INSTANT-ON
SLOT_RST# 28
VCC
3
2
1
R504 X_0
R505 10K
LOW
HIGH
IR_CON1
MLXCON2
CN-BH-S1x3-WH-M06
5 4
OS_SEL1 25
1
2
3
OS_SEL1 PIN
PIN(1-2)
PIN(2-3) WINDOWS(MCE)
Across mode
0B layout improve
OS_SEL1
X_H1X3_black
3
MINIPCI1
PIRQ#C
TP7
1
C233
0.1U25Y
C269
4.7U10Y0805
.
AD31
AD29
AD27
AD25
C_BE#3
AD23
AD21
AD19
AD17
C_BE#2
IRDY#
SERR#
PERR#
C_BE#1
AD14
AD12
AD10
AD8
AD7
AD5
AD3
AD1
C312
X_4.7U10Y0805
PCICLK2 7
PREQ#2 16 PGNT#2 16
VCC
L* Move to close
mini-PCI VCC pin.
VCC3
3
VCC3
MPCI_IRQ3 MPCI_IRQ4
C244
0.1U25Y
VCC
R450
10KR
C311
X_0.1U25Y
C248
X_0.1U25Y
101
103
105
107
109
111
113
115
117
119
121
123
C287
X_0.1U25Y
2
125
127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
100
99
102
104
106
108
110
112
114
116
118
120
122
124
128
126
MPCI_AGND
CN-MINIPCI-S124-BK
C500
0.1U25Y_B
2
IDSEL = AD21
MASTER = PREQ#2
PIRQ#C
VCC
PIRQ#B
TP1
1
.
R526 33R
VCC3
MPCI_IDSEL AD17
MPCIACT#
PLOCK#
SLOT_RST# PCICLK2
PGNT#2 PREQ#2
PCI_PME#
AD30
AD28
AD26
AD24
R449 3 00RST_B
AD22
AD20
PAR
AD18
AD16
FRAME#
TRDY#
STOP#
DEVSEL#
AD15
AD13
AD11
AD9
C_BE#0
AD6
AD4
AD2
AD0
VCC3
R236 10KR
R113 2.7KR
MSI
Title
Size Document Number R ev
Date: Sheet of
C308
X_0.1U25Y
1
3VDUAL
3VDUAL
VCC
MICRO-STAR INt'L CO., LTD.
PCI & Mini-PCI
MS-7056
1
19 36 Wednesday, July 21, 2004
0A
8
7
6
5
4
3
2
1
Put closed to VT6307
1394a OHCI Link Layer
Controller
L8
PAR 16,19,23
FRAME# 16,19,23
TRDY# 16,19,23
STOP# 16,19,23
1394_PCLK 7
R307
X_4.7KR
8
C343
0.1U25Y
AD[31..0]
VCC3_1394
C_BE#[3..0]
IRDY# 16,19,23
AD18
DEVSEL# 16,19,23
PREQ#3 16
PGNT#3 16
PERR# 16,19,23
PIRQ#C 16,19
DEV_RST#
C352 22P
PCI_PME#
VCC3
C542
0.1U25Y_B
U30
6
SCLK
5
SDA
7
WP
AT24C01-128
M33-24C0113-A26
VCC
GND
A0
A1
A2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C_BE#3
C_BE#2
C_BE#1
C_BE#0
PAR
FRAME#
IRDY#
TRDY#
STOP#
R331 100R
DEVSEL#
PREQ#3
PGNT#3
PERR#
PIRQ#C
1394_PCLK
R295 0R
R294
X_4.7KR
C541
X_0.1U25Y_B
VCC3
8
1
2
3
4
97
AD31
98
AD30
99
AD29
100
AD28
101
AD27
104
AD26
105
AD25
106
AD24
109
AD23
110
AD22
112
AD21
116
AD20
117
AD19
118
AD18
119
AD17
120
AD16
5
AD15
6
AD14
7
AD13
10
AD12
11
AD11
12
AD10
13
AD9
14
AD8
17
AD7
18
AD6
19
AD5
21
AD4
22
AD3
23
AD2
27
AD1
28
AD0
107
CBE3#
122
CBE2#
4
CBE1#
15
CBE0#
3
PAR
123
FRAME#
124
IRDY#
126
TRDY#
128
STOP#
108
IDSEL
127
DEVSEL#
96
REQ#
95
GNT#
2
PERR#
91
INTA#
93
PCICLK
92
PCIRST#
37
PME#
C329
7
D D
C C
B B
VCC3_1394
A A
AD[31..0] 16,19,23
VCC3
X_80L-0603-700mA
CP9 X_COPPER
C_BE#[3..0] 16,19,23
DEV_RST#
PCI_PME# 17,19,23
C338
C538
0.1U25Y
0.1U25Y_B
VCC3 VCC3
R308
X_4.7KR
EECK
EEDI
R296 510R
CHECK WITH BIOS COST DOWN ISSUE
X_0.1U25Y
102
94
113
VDD1
VSS1
103
125
VDD2
VSS2
111
C531
8
VDD3
VSS3
121
0.1U25Y_B
VCC3
20
VDD4
VSS4
1
33
VDD5
VSS5
9
VDD6
VSS6
16
114
VSS7
26
C330
35
VDDC1
VDDC2
VSS8
VSS9
34
0.1U25Y
24
RAMVDD
59
VCC3
6
GNDATX0
GNDARX0
GNDARX1
64
69
68
C339
0.1U25Y
VCC3_1394
39
49
62
PVDD1
PVDD2
RAMVSS
GNDATX2
GNDARX2
GNDATX1
25
83
82
D17
MBRS340-S-CASE403-03
+12V
C543 0.1U25Y_B
IDSEL = AD23
MASTER = PREQ#3
PIRQ#E
90
89
76
75
65
VDDATX0
VDDATX1
VDDARX1
VDDARX0
VSSC1
VSSC2
36
115
A C
XTPBIAS0
XTPA0P
XTPA0M
VDDATX2
VDDARX2
XTPB0P
XTPB0M
XTPBIAS1
XTPA1P
XTPA1M
XTPB1P
XTPB1M
XTPBIAS2
XTPA2P
XTPA2M
XTPB2P
XTPB2M
D6/CMCJMP
PHYRESET
CTL0/PC0JMP
CTL1/PC1JMP
D7/PC2JMP
LINKON/TSIJMP
LREQ/TSOJMP
MODE0
MODE1
LPS/CMC
SCL/EECK
SDA/EEDI
PGND1
PGND2
41
50
U32
XCPS
XREXT
D5
D4
D3
D2
D1
D0
SCLK
NC
EEDO
EECS
XI
XO
VT6307
B07-0630704-V01
74
73
72
71
70
81
80
79
78
77
88
87
86
85
84
63
66
52
58
54
55
53
57
56
51
48
47
R326 2KRST
46
45
44
43
42
40
38
67
32
31
30
29
60
61
FS2
BUS_PWR
1 2
F-MINISMDM260
EC44
CD100U16EL5
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
R471 11KRST_B
R470 1KRST_B
C536
0.1U25Y_B
EECK
EEDI
R367
1MR
+
C544
X_0.1U25Y_B
T* Frequency
Recheck in 0A
25V/CAP: EC80 NP: C93-1012511-G01 FP: 100U_16V
5
BUS_PWR
R472 6.34KRST_B
C540
47P_B
VCC3_1394
C346 10P
Y7
24.576MHZ16P_D
C347
10P
BUS_PWR
4
TPA0+
TPA0TPB0+
TPB0-
TPA1+
TPA1TPB1+
TPB1-
R397
270P
C359
TPB0TPB0+
TPA0TPA0+
TPBIAS0
R384
54.9RST
R392
54.9RST
4.99KRST
R385
54.9RST
GND shielding
R393
54.9RST
0.33U16Y C353
PCB LAYOUT GUIDE
R398
C360
R387
270P
54.9RST
TPB1TPB1+
TPA1TPA1+
R382
54.9RST
TPBIAS1
R402
CP10
1 2
X_0R0805_B
8
7
6
5
X_CMC-L02-9007020-C71
7 8
5 6
3 4
1 2
8
7
6
5
X_CMC-L02-9007020-C71
7 8
5 6
3 4
1 2
3
4.99KRST
R386
54.9RST
GND shielding
R383
54.9RST
C364
X_102P
L12
1
2
3
4
X_8P4R-0R
RN99
L10
1
2
3
4
RN96
X_8P4R-0R
0.33U16Y C354
CP11
R403
X_0R0805
1 2
TPA0P
TPA0N
TPB0P
TPB0N
BUS_PWR
TPA1P
TPA1N
TPB1P
TPB1N
Title
Size Document Number R ev
Date: Sheet of
OTHER
TPA0+
TPA0-
OTHER
W:S = 30:5:5:5:30
Length Mismatch < 25mil
5
4
3
2
1
6
7
1
6
5
4
3
2
8
MICRO-STAR INt'L CO., LTD.
MSI
2
J1394-1
SHLD
TPA+
TPATPB+
TPB-
SHLD
1394 CON4P
J1394-2
SHLD
PWR
TPA +
TPA TPB +
TPB GND
SHLD
1394-D6-BK
IEEE 1394
MS-7056
Space to other 30mil
Trace width 5mil
Space to self 5mil
Space to other 30mil
1394 CON
20 36 Wednesday, July 21, 2004
1
0A
5
N-P3055LD_TO252
C75
R32
6.49KR1%
D
S
C306
X_103P
R30
N-P3055LD_TO252
G
Q50
X_2N7002
D D
U6
C62 0.1U25Y
C63
0.1U25Y
DEV_RST# 12,15,20,23,25,28
1
2
3
4
5
6
7
FAN1_IN
FAN2_IN
VCC12
C1
C2
CHRPMP
GND
FAN1_DRV
FAN1_SEN
FAN2_DRV
FAN2_SEN
FAN3_DRV
FAN3_SEN
FANPWM1 25
FANPWM2 25
+12V
C61
0.1U25Y
C C
B B
14
13
12
11
10
9
8
FAN3_IN
VCC
R486 X_10KR
5VSB
R509 X_22R
X_103P
R31 10KR
R485 2MR
G
Q30
G
10KR
R29
6.49KR1%
Q8
G
4
+12V
D
R232
R231
X_0R0805
S
+
D
S
+
D
Q49
X_2N7002
S
EC39
C10U16EL
EC9
C10U16EL
5VSB
C303
X_102P
R64
X_0R0805
C60
X_102P
C593
1U16Y0805
4.7KR
CPUFAN1
3
2
1
FAN1X3_white
+12V
R60
4.7KR
CASEFAN1
3
2
1
FAN1X3_brown
R483 10KR
G
CPU FAN
CASE FAN
FANPWM1
D
Q48
2N7002
S
R233
27KR
R51
27KR
G
3
2
1
MDC MODULE
FANIO1 25
C441
X_0.1U25Y
VCC3
CB21
0.1U25Y
AC_SDOUT
AC_RST#
3VDUAL
MDC1
36
38 37
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
35
CN-IOC-BB-S-M30-A10
34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
33
PHONE 31
AC_SYNC
R345 22R
MDC_BITCLK
AC_SYNC 17,31
AC_SDIN1 17
MDC_BITCLK 31
R230
10KR
FANIO2 25
R47
10KR
AC_SDOUT 17,31
D
Q54
2N7002
S
AC_RST# 17,31
LM86 DIGITAL TEMPERATURE SENSOR
3VDUAL
A A
THERMDA_CPU 5
THERMDC_CPU 5
THRMTRIP# 5,28
3VDUAL
THRMTRIP#
R199 10KR
5
222P C251
U23
1
VDD
2
D+
3
DT_CRIT_A#4SMC
LM90_MSOP8
4
GND
ALERT#
SMD
5
6
SMBDATA1
7
SMBCLK1
8
THERM_ALERT# 17
SMBDATA1 7,8,17,23,28
SMBCLK1 7,8,17,23,28
16V/CAPs: EC16, EC48, EC68
NP: C96-1001610-P01 FP: 10F16VS
GND
THERMDA_CPU
THERMDC_CPU
GND
PCB Layout Guide
3
Trace Length less
then 4000mil
Trace Width 8mil
Space to self 8mil
Space to other
8mil
2
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
FAN/LM90/MDC
MS-7056
21 36 Wednesday, July 21, 2004
1
0A
5
ATA 33/66/100 Connector
PRIMARY IDE CONN.
HDDRST#
HDDRST# 28
D D
IDEACTP# 26
R347 33R
PDD_7
PDD_6
PDD_5
PDD_4
PDD_3
PDD_2
PDD_1
PDD_0
PDREQ_R
PDIOW#_R
PDIOR#_R
PIORDY_R
PDDACK#_R
IRQ14_R
PDA1_R
PDA0_R PDA2_R
PDCS#1_R
IDEACTP#
IDE1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
YJ220-Y-1
PDD_8
PDD_9
PDD_10
PDD_11
PDD_12
PDD_13
PDD_14
PDD_15
ATADET0_R
PDCS#3_R
4
R314 470R
PDD[15..0] 17
C334
X_473P16X
PDD[15..0]
PIORDY_R
IDEACTP#
IRQ14_R
PDREQ_R
PDD_7
ATADET0_R
3
R313 4.7KR
R312 10KR
R310 10KR
R309 4.7KR
R348 10KR
R311 X_15KR
VCC
2
PDREQ 17
PDIOR# 17
PIORDY 17
PDDACK# 17
PDIOW# 17
IRQ14 17
PDCS#1 17
PDCS#3 17
PDA2 17
ATADET0 17
PDA0 17
PDA1 17
PDREQ PDREQ_R
PDIOR# PDIOR#_R
PIORDY PIORDY_R
PDDACK#
RN76 8P4R-22R0402
PDIOW# PDIOW#_R
PDD14
PDD0
PDD15
RN77 8P4R-22R0402
PDD9
IRQ14
PDCS#1
PDCS#3
RN71 8P4R-22R0402
PDD12 PDD_12
PDD2 PDD_2
PDD13 PDD_13
PDD1 PDD_1
RN78 8P4R-22R0402
PDD5 PDD_5
PDD11 PDD_11
PDD3 PDD_3
RN79 8P4R-22R0402
PDD7
PDD10 PDD_10
RN80 8P4R-22R0402
PDA2 PDA2_R
ATADET0 ATADET0_R
PDA1
RN75 8P4R-22R0402
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2
1
PDDACK#_R
PDD_14
PDD_0
PDD_15
PDD_9
IRQ14_R
PDCS#1_R
PDCS#3_R
PDD_4 PDD4
PDD_7
PDD_8 PDD8
PDD_6 PDD6
PDA0_R PDA0
PDA1_R
SIORDY
mismatch
< 0.5"
< 0.5"
< 0.5"
SDD[15..0]
IDE Connector
SIORDY_R
IDEACTS#
IRQ15_R
SDREQ_R
SDD_7
ATADET1_R
R352 4.7KR
R357 10KR
R353 10KR
R350 4.7KR
R349 10KR
R354 X_15KR
VCC
SDDACK# 17
SDIOR# 17
SDIOW# 17
SDCS#1 17
SDCS#3 17
IRQ15 17
SIORDY 17
SDREQ 17
SDA2 17
ATADET1 17
SDA0 17
SDA1 17
SDD15 SDD_15
SDIOR# SDIOR#_R
SDIOW# SDIOW#_R
SDD8 SDD_8
SDD10 SDD_10
SDD11 SDD_11
SDD14 SDD_14
SDCS#1 SDCS#1_R
IRQ15 IRQ15_R
SDD12 SDD_12
SDD2 SDD_2
SDD1 SDD_1
SDD5 SDD_5
SDD0 SDD_0
SDD4 SDD_4
SDD3 SDD_3
SDD6 SDD_6
SDA2 SDA2_R
ATADET1 ATADET1_R
SDA1
1 2
SDDACK#_R SDDACK#
3 4
5 6
7 8
RN105 8P4R-22R0402
1 2
3 4
5 6
7 8
RN106 8P4R-22R0402
RN107 8P4R-22R0402
RN108 8P4R-22R0402
RN109 8P4R-22R0402
RN110 8P4R-22R0402
RN111 8P4R-22R0402
SDD_9 SDD9
1 2
3 4
SDCS#3_R SDCS#3
5 6
7 8
1 2
SDD_13 SDD13
3 4
5 6
7 8
1 2
3 4
5 6
SDD_7 SDD7
7 8
SIORDY_R SIORDY
1 2
3 4
5 6
SDREQ_R SDREQ
7 8
7 8
5 6
SDA0_R SDA0
3 4
SDA1_R
1 2
<4"
<4"
<4"
<4"
SDD[15..0] 17
C345
X_473P16X
SDIOR#
mismatch
< 0.5"
< 0.5"
< 0.5"
L2 < 4"
HDDRST#
SDD_7
SDD_6
SDD_5
SDD_4
SDD_3
SDD_2
SDD_1
SDD_0
SDREQ_R
SDIOW#_R
SDIOR#_R
SIORDY_R
SDDACK#_R
IRQ15_R
SDA1_R
SDA0_R
SDCS#1_R
<4"
<4"
<4"
<4"
R346 33R
PDIOR#
mismatch
< 0.5"
< 0.5"
< 0.5"
SIDE1
2
112
4
334
6
556
8
778
9
19
21
9
10
111112
131314
151516
171718
19
22
21
232324
252526
272728
292930
313132
333334
353536
373738
393940
D2x20_WHITE
10
12
14
16
18
22
24
26
28
30
32
34
36
38
40
PCB LAYOUT GIUDE
PIORDY
mismatch
< 0.5"
< 0.5"
< 0.5"
Signal
SDIOR#
SDIOW#
SIORDY
SDD[0..15]
SB
VT8237
SDD_8
SDD_9
SDD_10
SDD_11
SDD_12
SDD_13
SDD_14
SDD_15
R465
470R
ATADET1_R
SDA2_R
SDCS#3_R
IDE2 Group => (W:S=5:10)
L1 L2+L3
<1"
<1"
<1"
<1"
L1 < 1"
Damping
Rs
C C
B B
HDDRST# 28
IDEACTS# 26
IDE1 Group => (W:S=5:10)
Signal
PDIOR#
PDIOW#
PIORDY
PDD[0..15]
SB
VT8237
L1 L2
<1"
<1"
<1"
<1"
L1 < 1" L2 < 4"
Damping Rs
IDE Connector
A A
Lshortest Llongest
Ldiff<1"
DD[15:0]
-IOR and IORDY
(HSTROBE and DSTROBE)
5
<0.5" <0.5"
Lstrobe
4
Title
Size Document Number Rev
3
2
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
MSI
ATA 66/100/133
MS-7056
22 36 Wednesday, July 21, 2004
1
0A
A
PCI LAN RTL8110S/8100C/Add Dual Layout 8110CL
LAN_XTAL1
Y1
4 4
3 3
2 2
C18
27P
T* Frequency
Recheck in
0A
VCC
R1 1KR
R2 15KR
PIRQ#D 16,19
DEV_RST# 12,15,20,21,25,28
GLAN_PCLK 7
PGNT#4 16
PREQ#4 16
PCI_PME# 17,19,20
25MHZ
C17
27P
LAN_XTAL2
5.6K(1%) FOR RTL8100C;
2.49K(1%) FOR RTL8110S
R3 5.6KRST
AVDDH
AVDDL
MDIO0+
MDIO0-
MDIO1+
MDIO1-
CTRL25
V_12P
MDIO2+
MDIO2-
MDIO3+
MDIO3-
LAN_ISO
PGNT#4
PREQ#4
AD31
AD30
AD29
AD28
AD19
R422 100R_B
DVDD
Lan_RSET
CTRL18
1
MDI0+/TX+
2
MDI0-/TX-
3
AVDDL/AVDD33
4
VSS
5
MDI1+/RX+
6
MDI1-/RX-
7
AVDDL/AVDD33
8
CTRL25
9
VSS/NC
10
AVDDH/NC
11
NC
12
NC/AVDD25
13
VSS/NC
14
MDI2+/NC
15
MDI2-/NC
16
AVDDL/NC
17
VSS
18
MDI3+/NC
19
MDI3-/NC
20
AVDDL/AVDD33
21
VSSPST
22
GND/NC
23
ISOLATEB
24
VDD18/NC
25
INTAB
26
VDD33
27
RSTB
28
CLK
29
GNTB
30
REQB
31
PMEB
32
VDD18/VDD25
33
AD31
34
AD30
35
GND
36
AD29
37
AD28
38
VSSPST
U1
123
124
125
126
121
122
127
128
VSS
VSS
VSS
RSET
XTAL1
XTAL2
VDD18/NC
CTRL18/NC
AD2739AD2640VDD3341AD2542AD2443CBE3B44VDD18/NC45IDSEL46AD2347GND/NC48AD2249AD2150VSSPST51GND52AD2053VDD18/VDD25
AD26
AD27
AD24
AD25
C_BE#3
LAN_IDSEL
RJ45 Connector (with transformer)
Remove it in 0B BOM
LAN_TX_RX
LAN_LINK1000
X_0.1U25Y_B
X_0.1U25Y_B
X_0.1U25Y_B
X_0.1U25Y_B
R414 X_49.9RST_B
R415 X_49.9RST_B
R416 X_49.9RST_B
R417 X_49.9RST_B
R418 X_49.9RST_B
R419 X_49.9RST_B
R420 X_49.9RST_B
R421 X_49.9RST_B
A
C382
C379
1 1
C380
C381
R11 X_0R
R14 X_330R
MDIO0+
MDIO0-
MDIO1-
MDIO2+
MDIO2-
MDIO3+
MDIO3-
LAN_LINKUP
LINK1000
R410 100RST_B
R411 100RST_B
R412 X_100RST_B
R413 X_100RST_B
TX+
TXRX+
RX+
C41
103P
118
119
120
VSSPST
AVDDH/NC
AD23
AD22
LAN_TX_RX
116
117
LED0
GND/NC
VDD18/NC
AD21
AVDDL
R22
X_0R
B
R15 X_10KR
LAN_LINK1000
LAN_LINK100
106
107
108
109
110
111
112
113
114
115
EEDI
LED2
LED1
EESK
EEDO
VDD33
GND/NC
LED3/NC
VDD18/NC
RTL8110S/8100C
AD1955VDD3356AD1857AD1758AD1659CBE2B60FRAMEB61GND/NC62IRDYB63VDD18/NC
54
AD19
AD16
AD18
AD17
AD20
R8
X_0R
C35
X_103P
B
VDD33
R21
330R
C_BE#2
C620
102P
LINK1000
LAN_EECS
LAN_EESK
LAN_EEDI
LAN_EEDO
AD0
AD1
103
104
105
AD0
EECS
LANWAKEUP
VDD18/VDD25
VDD18/VDD25
64
C619
102P
LAN_LINKUP
MDIO0+
MDIO0- MDIO1+
MDIO1+
MDIO1MDIO2+
MDIO2MDIO3+
MDIO3-
LAN_LINK100
C621
102P
LAN EEPROM
U5
1
CS
2
SK
3
DI
4
DO
ATL-93C46-128x8-0.5us-SOIC8
R28
5.6KRST
AD1
102
AD2
101
VSSPST
100
GND
99
98
AD3
97
AD4
96
AD5
95
AD6
94
VDD33
93
AD7
92
CBE0B
91
VSSPST
90
AD8
89
AD9
88
M66EN/NC
87
AD10
86
AD11
85
AD12
84
VDD33
83
AD13
82
AD14
81
VSSPST
80
GND
79
AD15
78
77
CBE1B
76
PAR
75
SERRB
74
SMBDATA
73
GND/NC
72
SMBCLK
71
VDD33
70
PERRB
69
STOPB
68
DEVSELB
67
TRDYB
66
VSSPST
65
CLKRUNB
IRDY# 16,19,20
FRAME# 16,19,20
1- MDIO+ & MDIO- pairs should be
100-ohm differential impedance.
Route equal length and
VDD33
symmetrically. Separate every
pairs.
R23
330R
19
20
13
18
12
17
11
16
10
15
9
14
21
22
C622
102P
VCC
NC
NC
GND
VDD33
DVDD
LAN_USB1B
AMBER+
AMBER-
TD1+
TD1TD2+
TD2TD3+
TD3TD4+
TD4-
NC
GREEN+
GREEN-
USB_RJ45_TR
VDD33
8
7
CB2
6
X_0.1U25Y
5
AD2
AD3
AD4
AD5
AD6
AD7
C_BE#0
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
C_BE#1
R41 X_0R
R42 X_0R
PERR# 16,19,20
STOP# 16,19,20
DEVSEL# 16,19,20
TRDY# 16,19,20
IDSEL = AD24
MASTER = PREQ#4
PIRQ#F
NC
C
PAR 16,19,20
SERR# 16,19
SMBDATA1 7,8,17,21,28
SMBCLK1 7,8,17,21,28
C
TE_PNP-2SB1197K-S-SOT23
VDD33
CTRL25
1
Q5
X_BCP69
SOT-223
CTRL25
Q6
X_BCP69
SOT-223
3 2
B
4
VDD33
3 2
1
+
EC11
VDD33
C E
+
EC2
CD100U16EL5
4
Place at pin 3,7,16,20
C3
C4
0.1U25Y
0.1U25Y
X_CD100U16EL5
Place at pin 26,41,56,71,84,94,107
C393
C386
0.1U25Y_B
0.1U25Y_B
CTRL18
DVDD
8100C
2.5V 2.5V 3.3V X 2.5V
8110S
1.8V
AD[0..31] 16,19,20
C_BE#[0..3] 16,19,20
DEV_RST#
N58-22F0031-S42 for GIGALAN
N58-22F0061-S42 for 10/100
D
Q44
C397
0.1U25Y_B
C5
0.1U25Y
C387
C391
0.1U25Y_B
0.1U25Y_B
DVDDA
AVDDL
1.8V 2.5V
AD[0..31]
C_BE#[0..3]
C369
X_33P_B
D
AVDDL
C6
0.1U25Y
C389
0.1U25Y_B
VDD33
DVDD
X_0.1U25Y_B
R84
0R0805
C77
0.1U25Y
C373
0.1U25Y_B
V-12P
AVDDH
3.3V X
E
Ask Layout check the
CP13 footprint
3VDUAL VDD33
+
EC8
CD100U16EL5
C372
0.1U25Y_B
VDD33
R487 X_0R_B
R409 0R_B
CP13
1 2
R423 X_0R0805_B
V_12P
Place at pin 24,32,45,54,64,78,99,110,116
C390
VDD33
+
EC17
C375
0.1U25Y_B
C396
X_0.1U25Y_B
R6 X_0R
C26
0.1U25Y
C385
0.1U25Y_B
X_0.1U25Y_B
Place at pin
10,120
C374
0.1U25Y_B
X_CD100U16EL5
Part Value Selection:
C377
C20
X_0.1U25Y
C376
C378
0.1U25Y_B
0.1U25Y_B
AVDDH
C371
X_0.1U25Y_B
C370
0.1U25Y_B
C394
0.1U25Y_B
GbE: 8110S LAN(1000M)
TE: 8100C LAN(10/100M)
L: With LAN option
X: No Stuff
PCB LAYOUT GUIDE
OTHER
MDIO0+
MDIO0-
OTHER
Space to other 30mil
Trace width 5mil
Space to self 5mil
Space to other 30mil
W:S = 30:5:5:5:30
Total Length < 4.72 inch
Length Mismatch < 25mil
DEFAULT 10/100, for GIGALAN OPTION
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number R ev
Date: Sheet of
RTL 8110S/8100C
MS-7056
23 36 Wednesday, July 21, 2004
E
0A
5
POWER CIRCUIT FOR USB PORT 0,1,2,3
FS1
5V_STR
D D
USB_OC#1 16
USB_OC#2 16
1 2
F-MINISMDM260
R4
47KR C19
C25
0.1U25YR756KRST
R5
1KR
FRONT USB PORT
FRONT PANEL USB CONNECTOR FOR USB PORT 4,5
L11
USBN5
USBN5 16
USBP5
USBP5 16
USBN4 USB_D4-
USBN4 16
USBP4
USBP4 16
C C
NEAR USB
CONNECTOR
INTERNAL USB CONNECTOR FOR USB PORT 6,7
1
2
3
4
CMC-L02-9007020-C71
1 2
3 4
5 6
7 8
RN98
X_8P4R-0R
8
7
6
5
4
KBVCC
X_1U10Y
EC1
+
CD1000U6.3EL15
USB_D5USB_D5+
USB_D4+
SVCC1
USB1
1
2
3
4
USBX1
CONN-USBX1
USB2
1
2
3
4
USBX1
CONN-USBX1
C361
CD470U6.3EL11
3
POWER CIRCUIT FOR USB PORT 4,5,6,7
F2
5V_STR
USB_OC#3 16
1.5A-miniSMDC200-S
R395
47KR
C358
0.1U25Y
R388
56KRST
R406
1KR
NEAR USB CONNECTOR NEAR USB CONNECTOR
REAR USB PORT
5
6
5
6
USBP3 16
USBN3 16
USBN2 16
USBP2 16
USBP3
USBN3
USBN2
USBP2
2
SVCC1
C366
C367
X_1U10Y
0.1U25Y
L5
1
2
3
4
CMC-L02-9007020-C71
1 2
3 4
5 6
7 8
RN3
X_8P4R-0R
8
7
6
5
USB_D3+
USB_D3-
USB_D2-
USB_D2+
USBP4
USBN4
USBP5
USBN5
USBP0
USBN0
USBN1
USBP1
USBP2
USBN2
USBN3
USBP3
USBP6
USBN6
USBP7
USBN7
KBVCC
1
8P4R-15KR
RN97
1 2
3 4
5 6
7 8
8P4R-15KR
RN82
1 2
3 4
5 6
7 8
8P4R-15K
RN2
1 2
3 4
5 6
7 8
8P4R-15KR
RN81
1 2
3 4
5 6
7 8
LAN_USB1A
5
6
7
8
1
2
3
4
DOWN
USB_RJ45_TR
UP
23
24
25
26
27
28
29
30
B B
USBN7 16
USBP7 16
USBN6 16
USBP6 16
A A
USBN7
USBP7
USBN6
USBP6
NEAR USB
CONNECTOR
5
2 14 36 5
8 7
CN19
X_8P4C-47P
5V_STR
5V_STR
6 7
1
2
3
4
5
USB4
1
2
3
4
FAN1X4_white-2pitch
CR1
BH1X6-S
KBVCC
USB3
MS-7056
5
6
7
8
1
2
3
4
YUSB-D1
DOWN
1
UP
9
10
11
12
24 36 Wednesday, July 21, 2004
0A
R271 X_0R
USBN1 16
USBP1 16
USBN0 16
USBP0 16
R268 X_0R
USBN0 USB_D0-
USBP0 USB_D0+
PCB LAYOUT GUIDE
OTHER
USBP
USBN
OTHER
W:S = 50:7.5:7.5:7.5:50
Total Length < 12 inch
Length Mismatch < 25mil
4
Space to other 50mil
Trace width 7.5mil
Space to self 7.5mil
Space to other 50mil
5V_STR
Reverse For Dual OS
J5
1
2
3
4 5
X_CONN-USBX1_H
3
L4
8
7
6
5
CMC-L02-9007020-C71
RN1
X_8P4R-0R
HORIZONTAL
1
2
3
4
1 2
3 4
5 6
7 8
6
2
USB_D1USB_D1+
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Front/Rear USB Port
8
LPC SUPER I/O 49M292
DEV_RST# 12,15,20,21,23,28
SIO_PCLK 7
SERIRQ 17
LPC_REQ# 18
D D
C C
5VSB
B B
LPC_FRAME# 18
LPC_AD0 18
LPC_AD1 18
LPC_AD2 18
LPC_AD3 18
VCORE
FANPWM1 21
FANPWM2 21
VBAT
SUSB# 17,28,32
SIO48M 7
C473
VCC
0.1U25Y_B
Decoupling CAP.
OS_SEL1 19
FANIO1 21
FANIO2 21
VBAT
VCC3
BIOS_VER1
BIOS_VER2
BIOS_VER3
VREF
VAVCC
-12VIN
+12VIN
R481 2MR
C181
X_0.1U25Y
C467
0.1U25Y_B
U20
30
LRESET#
21
LCLK
23
SERIRQ
22
LDRQ#
29
LFRAME#
27
LAD0
26
LAD1
25
LAD2
24
LAD3
125
GPX2/GP13
123
GPY1/GP15
128
GPSA1/GP10
121
GPSA2/GP17
126
GPX1/GP12
124
GPY2/GP14
127
GPSB1/GP11
122
GPSB2/GP16
120
MSO/IRQIN0/GP20
119
MSI/GP21
101
VREF
102
VTIN
103
CPUTIN
104
SYSTIN
93
GP26
94
GP25
95
GP24
96
GP23
97
VIN3
98
VIN2
99
VIN1
100
CPU_VCORE
106
GP54
107
GP53
108
GP52
109
GP51
110
GP50
116
FANPWM1
113
FANIN1
115
FANPWM2
112
FANIN2
111
OVT#
105
GP55
118
GP22
76
CASEOPEN#
19
PME#
89
WDTO/GP33
91
GP31
92
GP30
67
PSOUT#/GP47
68
PSIN/GP46
64
SUSLED/GP37
90
PLED/GP32
72
PWRCTL#/GP42
73
SLP_SX#/GP41
18
CLKIN
61
VSB
74
VBAT
28
VCC3
12
VCC_1
48
VCC_2
77
GP36
114
VCC_4
W83627THF
7
SIO
DRVDEN0
SMI#/IRQIN1
INDEX#
MOA#
FANIN3
DSA#
FANOUT3
STEP#
WRDATA#
TRACK0#
RDDATA#
HEAD#
DSKCHG#
SLCT
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
IRRX/GP34
GP45
GP40
DCDA#
DSRA#
RTSA#
SOUTA
CTSA#
DTRA#
DCDB#
DSRB#
RTSB#
SOUTB
CTSB#
DTRB#
GA20M
KBRST
KBDATA
KBCLK
MSDATA
MSCLK
BEEP
RSMRST#/GP44
PWROK/GP43
VSS1
VSS2
GP35
VSS4(AGND)
DIR#
WE#
WP#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
IRTX
SINA
RIA#
SINB
RIB#
6
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
42
41
40
39
38
37
36
35
31
32
PE
33
34
43
44
45
46
47
88
69
87
GP40
75
DCDA#
56
DSRA#
50
SINA
53
RTSA#
51
SOUTA
54
CTSA#
49
DTRA#
52
RIA#
57
DCDB#
84
DSRB#
79
MP_RXD
82
MP_RTS
80
MP_TXD
83
CTSB#
78
MP_DTR
81
RIB#
85
59
60
63
62
66
65
58
BIOS_WP#
70
71
20
55
86
117
BEEP
MP_RXD 30
MP_RTS 30
MP_TXD 30
MP_DTR 30
R446 10KR
VCC
Q47
MMBT3904
5
ALA RM 26
4
SERIAL PORT 1
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
DOUT1
DOUT2
DOUT3
+12VIN
-12VIN
R162
10KRST
V+
V-
VCC3
+12VCOM
1
19
18
17
14
12
5
6
8
-12VCOM
10
VAVCC
C194
0.1U25Y
R160
56KRST
VREF
MS_DT
CN25
8P4C-220P50N
U4
20
VCC
LPC_REQ#
VCC
RESVD
R161 28KRST
+12V
R159 232KRST
-12V
MSDAT# 16
MSCLK# 16
KBDAT# 16
KBCLK# 16
MSDAT#
MSCLK#
KBDAT#
KBCLK#
NCTSA#
NDSRA#
NSINA
NDCDA#
RTSA#
DTRA#
SOUTA
R152 4.7KR
L7
X_08S/0805
1 2
3 4
5 6
7 8
VCC
2
RIN1
3
RIN2
4
RIN3
7
RIN4
9
RIN5
16
DIN1
15
DIN2
13
DIN3
11
GND
GD75232_SSOP20
2 1
1 2
CP2
RN100
8P4R-4.7KR
FB3 120L-0603-600mA
FB1 120L-0603-600mA
FB4 120L-0603-600mA
FB2 120L-0603-600mA
3
C398
0.1U25Y
D14
1N4148S
RIA# NRIA#
CTSA#
DSRA#
SINA
DCDA#
NRTSA
NDTRA
NSOUTA
D4
1N4148S
Power-on strap, enable 48MHz
C388
0.1U25Y
CTSB#
DSRB#
RIB#
DCDB#
RTSA#
DTRA#
SOUTA
SOUTB
RTSA#
CPU_12V
-12V
VCC
R506 4.7KR
VCC
R163 4.7KR
L: Disable KBC
L: 24MHZ
L: CFAD=2E
L: PNP Default
NRIA#
31
NCTSA#
32
NRTSA
33
NDSRA#
34
NRIA#
GP40
MP_TXD
RN33 8P4R-4.7KR
7 8
5 6
3 4
1 2
RN101 8P4R-4.7KR
7 8
5 6
3 4
1 2
H: Enable KBC SOUTA
H: 48MHZ
H: CFAD=4E
H: PNP no Default DTRA#
PS2 KEYBOARD & MOUSE CONNECTOR
JKBMS1
14
14
4
4
6
MS_CK
KB_DT
KB_CK
135
246
7
8
6
2
2
13
13
1
1
5
5
3
3
15
15
MINIDINx2-D12-ML
2
VGA1B
6723-VGA-COM
VCC
16
16
10
10
12
12
8
8
7
7
11
11
9
9
17
17
22
26
27
28
29
30
20
NDCDA#
NSINA
NSOUTA
NDTRA
NRTSA
NDSRA#
NCTSA#
NRIA#
NDCDA#
NSOUTA
NSINA
NDTRA
R12 1KR
Internal Ring Wake Up Block
NRIA_SB#
5V_STR
MS_CK
R369
10KR
KBDAT# M S_DT
KBCLK#
MSDAT#
MSCLK#
B
KBVCC
7
5
3
1
CN1
8P4C-220P50N
7
5
3
1
CN3
8P4C-220P50N
C E
MMBT3904
C7
0.1U25Y
1
2
3
4
5
6
1
8
6
4
2
8
6
4
2
NRIA_SB#
RING# 17
Q39
8 7
JKBMS2
X_BH1X6-S
VCC3
R289
4.7KR
LPC_INIT#
A A
U26_X1
BIOS
SST49LF040-33-4C-NH
8
U26_X2
BIOS
X_W49V002AP(F)
7
DEV_RST# 12,15,20,21,23,28 BIOS_PCLK 7
LPC_AD0 18
LPC_AD1 18
LPC_AD2 18
LPC Flash Rom
VCC3
DEV_RST#
PRES3 PRES4
PRES2
PRES1
PRES0
BIOS_WP#
TBL#
LPC_AD0
LPC_AD1
LPC_AD2
6
U26
1
VPP
2
RST#
3
FGPI3
4
FGPI2
5
FGPI1
6
FGPI0
7
WP#
8
TBL#
9
ID3
10
ID2
11
ID1
12
ID0
13
FWH0
14
FWH1
15
FWH2
GND16FWH3
X_PLCC-32
<Priority>
FGPI4
IC(VIL)
GNDA
VCCA
GND
INIT#
FWH4
VCC
CLK
VCC
RFU
RFU
RFU
RFU
RFU
VCC3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5
BIOS_PCLK
LPC_INIT#
LPC_FRAME#
LPC_AD3
LPC_FRAME# 18
LPC_AD3 18
VCC3
4
0.1U25Y_B CB24
X_0.1U25Y_B CB23
C507 0.1U25Y_B
C505 X_0.1U25Y_B
BIOS_VER1
BIOS_VER2
BIOS_VER3
3
R155 4.7KR
R156 X_4.7KR
R157 4.7KR
R158 X_4.7KR
R154 4.7KR
R153 X_4.7KR
VCC3
MSI
Title
Size Document Number R ev
Date: Sheet of
2
default is high
PRES4
PRES3
PRES2
PRES1
PRES0
BIOS_WP#
TBL#
RN73 8P4R-1KR
RN72 8P4R-1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
MICRO-STAR INt'L CO., LTD.
SIO W83627THF / BIOS
MS-7056
25 36 Wednesday, July 21, 2004
1
VCC3
VCC3
0A
5
VCC3
EC45
+
X_CD1000U6.3EL15
11
-12V
D D
C636
X_0.1U25Y
VCC
C C
SATAACT# 18
PS_OUT# 28
PS_ON#A 5
C319
0.1U25Y
C539 X_0.1U16X_B
Placement Error.
VCC
R469
4.7KR_B
D16 1N4148S_B
A C
R283 X_0R
VCC 5VSB
C320
0.1U25Y
C537
181P_B
12
13
14
15
16
17
18
19
20
JWR1
3.3V
-12V
GND
PS_ON
GND
GND
GND
-5V
5V
5V
ATX-PCON
4
3.3V
3.3V
GND
GND
GND
PW_OK
5V_SB
12V
3
VCC3
C325
4.7U10Y0805
PW_OK 28
PW_OK
C333
0.1U25Y
VCC
R284
4.7KR
C321
0.1U25Y
VCC3
1
2
3
4
5V
5
6
5V
7
8
9
10
C335
0.1U25Y
C332
0.1U25Y
EC50
+
CD470U16EL11.5
VCC
+12V
2
C327
0.1U25Y
CB16
0.1U25Y
POWER OK Circuits
Power On Sequence.
PSON#
PS_OUT#
PW_OK
EN_DDR
EN_VDDA_25
EN_VCORE
PG_VCORE
EN_VDD_12_A
CPU_GD
ALL_PWRGD
R164 220R
B
R165 220R
C E
Q23
MMBT3904
ALARM 25
SPKR 17
R167
2.2KRST
D6
A C
1N4148S
VCC
BZ1
BUZZER
1
IDEACTP# 22
IDEACTS# 22
B B
IDE_LED 30
A A
1
2
BOM Error change form
BAT54C to BAT54A
FP_RST# 7,28,30
5
D15
3
FP_RST#
C363
0.1U25Y
VCC
R401
330R
JFP1
1
HDD+
3
HDDRESET-5PWSW+
7
RESET+
PWSW-
9
NC
JFP1
FRONT PANEL
For MSI / Intel Front Panel
PLED
SLED
PLED1
2
PLED2
4
6
8
R400 100R
4
PLED1 28,30
PLED2 28,30
C362
0.1U25Y
Q43
D S
2N7002
G
PWBTIN# 17
MP_CTR_PWRON 30
R399
5.1KR
3
VCC2_5
ALL_PWRGD 18,28
R172 X_330R
-LDTRST 11
R179 1KR
R171 1KR
VCC
C144
0.1U25Y
2
3VDUAL
R188
4.7KR
C E
Q25
B
MMBT3904
C E
Q24
B
MMBT3904
Title
Size Document Number Rev
Date: Sheet of
VSUS2_5
VCC2_5
R196
R482
X_4.7KR
4.7KR
C E
Q26
B
MMBT3904
Reserved for Hyper-Transport
Reset Test .
MICRO-STAR INt'L CO., LTD.
MSI
Power OK/Sequence/Front Panel
MS-7056
-CPURST 5
1
0A
36 Wednesday, July 21, 2004
26
5
4
3
2
1
K8 Voltage Regular Module
D D
VCC
C115
X_22P C124
COREFB_L 5
PG_VCORE
C123 562P
R130
1KRST R128
VDIFF
IDROOP
COREFB_H 5
X_0.1U25Y
VID4
VID3
VID2
VID1
VID0
FS_ISL
COMP
FB_ISL
24
3
4
5
6
7
22
23
9
10
12
11
R116
4.7KR
VCC
R134
270KR
VCORE_EN#
VID[4..0] 5
C121
X_0.1U25Y
R127 10KRST
0R
VID[4..0]
R121
10KR
R118 154KRST
VCORE
GND
COMP1
R131 51RST
R129 51RST
VCORE_EN# 28
C C
PG_VCORE 28
VCC
Droop Compensation
CPU_12V
U19
ISL6569CB
I32-6569B02-I11
EN
VID4
VID3
VID2
VID1
VID0
PGOOD
FS/DIS
COMP
FB
VDIFF
IDROOP
CHOK1 1.1uH/25A
16
VCC
18
GND
15
GND
1
GND
20
PWM1
21
ISEN1
19
PWM2
17
ISEN2
8
OFS
2
OVP
13
VSEN
14
RGND
OFS : Voltage up offset
, 1K Ohm =10mV
C59
X_39P
VCC
D18
ISEN1
ISEN2
OFS
+
BAT54C
3
CB8
1U16Y0805
R124 3.6KRST
R126 3KRST
Offset Adjustment
CT4
CD1500U16EL20
1 2
R123
0R
VDD_12_VRM
CT3
CT1
CD1500U16EL20
CPU_12V
R111
5.1R0805
VDD_P0
CB6
1U25X0805
PWM1
CPU_12V
R109
5.1R0805
VDD_P1 U_G2A U_G2
CB5
1U25X0805
PWM2
CD1500U16EL20
U15A
HIP6602B
I33-6602B03-I11
14
VCC
3
GND
1
PWM1
U15B
PVCC5U_G2
6
PGND
2
PWM2
HIP6602B
CT2
CD1500U16EL20
C76
4.7U16Y1206
U_G1
BOOT1
PHASE1
L_G1
BOOT2
PHASE2
L_G2
C79
4.7U16Y1206
PBT1
U_G1
12
11
R107
4.7R
13
L_G1 L_G1A
4
PBT2
9
10
R106
4.7R
8
L_G2
7
BOOT1
C108
0.1U25Y
R96
2.2R0805
BOOT2
C102
0.1U25Y
R98
2.2R0805
R82
0R0805
R83
0R0805
CB3
1U16Y0805
D S
U_G1A
G
Q9
PHASE1
PHASE2
L_G2A L_G2A
09N03/DPACK
D S
G
D S
G
D S
G
Q10
06N03
CB4
1U16Y0805
Q12
09N03/DPACK
Q14
06N03
R97
R95
2.2R
C91
102P
2.2R
C95
102P
L_G1A
VCORE
CHOK2
D S
0.8u-20%
Q11
06N03
G
CHOK3
D S
0.8u-20%
Q13
06N03
G
0.8V~1.55V/42A
B B
VID4 VID3 VID2 VID1 VID0 Vout
1 1 1 1 0 0.800
1 1 1 0 1 0.825
1 1 1 0 0 0.850
1 1 0 1 1 0.875
1 1 0 1 0 0.900
1 1 0 0 1 0.925
1 1 0 0 0 0.950
R619 ORIGNAL 154KST R11-1543T13-Y01
POWER FREQENCY ADIUSTING
R11-0304T13-Y01 300KRST
VID4 VID3 VID2 VID1 VID0 Vout
0 1 1 1 0 1.200
0 1 1 0 1 1.225
0 1 1 0 0 1.250
0 1 0 1 1 1.275
0 1 0 1 0 1300
0 1 0 0 1 1.325
0 1 0 0 0 1.350
0 0 1 1 1 1.375 1 0 1 1 1 0.975
1 0 1 1 0 1.000
1 0 1 0 1 1.025
A A
1 0 1 0 0 1.050
1 0 0 1 1 1.075
1 0 0 1 0 1.100
1 0 0 0 1 1.125
1 0 0 0 0 1.150
0 1 1 1 1 1.175
5
0 0 1 1 0 1.400
0 0 1 0 1 1.425
0 0 1 0 0 1.450
0 0 0 1 1 1.475
0 0 0 1 0 1.500
0 0 0 0 1 1.525
0 0 0 0 0 1.550
1 1 1 1 1 Shutdown
4
VCORE
CT5
CD1500U6.3EL20
CD1500U6.3EL20
CD1500U6.3EL20
CT12
CD1500U6.3EL20
MOSFET Heat-Sink
PH1
2
112
E31-0500351-K08
60MIL
CPU_12V
C110
0.1U25Y
Near to Vcore Input-Chock ( CHOK1 )
CT10
CT8
2
JPW1
3
12V
4
12V
ATX12V-NPEG
CT11
CD1500U6.3EL20
CT7
CD1500U6.3EL20
PH2
112
E31-0500351-K08
1
GND
2
GND
3
CT6
CD1500U6.3EL20
CT9
CD1500U6.3EL20
R114
R112 2KRST
R439
4.64KRST_B
R438
2.8KRST_B
1.82KRST
RT1
YT472S-1N
C563
0.1U25Y_B
2
VCC
U17A
LM393_#A
I72-LM39303-T07
8 4
3
+
2
-
U17B
LM393_#A
I72-LM39303-T07
8 4
5
+
6
-
FS_ISL
MS-7056
VCC VCC
1
C111
X_0.1U16X
27 36 Wednesday, July 21, 2004
R437
Q45
2N7002_B
1
Q46
2N7002_B
7
MSI
Title
Size Document Number Rev
Date: Sheet of
X_270KST_B
R441
X_300KST_B
MICRO-STAR INt'L CO., LTD.
K8 CPU Core Power
0A
8
3VSB MODE SELECT
3VSB MODE
D D
DUAL MOSFET
SINGLE MOSFET
VDIMM LINEAR OR PWM SELECT
VDIMM MODE
LINEAR REGULATOR
PWM REGULATOR
C C
FRONT PANEL RESET BUTTON
PCIRST# INPUT
3VDLDEC#
PULL LOW
PULL HIGH
EXTRAM
PULL LOW
PULL HIGH
PCIRST# BUFFER OUTPUT
PCI SOLT PCIRST# BUFFER OUTPUT
VDDA_25
VDDA_25 To CPU
Copper trace
width > 50mils
.
B B
R222 4.7KR
SUSB# 17,25,32
THE TWO BLOCK CHOICE ONE
SUPPORT SYSTEM POWER
CONTROL
To CPU Copper trace width > 250mils , Fill
island behind DIMM > 400mils .
DDR_VTT 1. 25V
V1.0
3VDUAL
A A
C317
0.1U25Y
8
U27
8
7
6
5
W83310DS
VREF2
ENABLE
VCNTL
BOOT_SEL
9
VIN
GND
GND
VREF1
VOUT
VDD_25_SUS
1
2
3
4
7
PLED1 26,30
PLED2 26,30
FP_RST# 7,26,30
PCIRST# 14,16
HDDRST# 22
DEV_RST# 12,15,20,21,23,25
PG_VCORE 27
VCORE_EN# 27
1.25VREF 29
SLOT_RST# 19
VDDA_25
CLOSE TO CHIP
5VSB
R221
4.7KR
PS_IN#
PS_OUT# 26
C E
Q29
MMBT3904
B
Ic=200mA
Vebo=6V
Vceo=40V
DDR TERMINATION
R259 100R
100R
R260
VTT_DDR_SUS
1 2
1 2
+
+
EC37
EC42
CD1000U6.3EL15
CD1000U6.3EL15
7
MMBT3904
VCC3
+
EC27
CD100U16EL5
5VSB
6
5VSB
R234
330R
VCC
C301
R235
330R
VCC
R218
1KR
R227
330R
1U10Y
R216
4.7KR
R224
4.7KR
VCC3
C297 4.7U10Y0805
C291
0.1U25Y
5VSB
R228
330R
C300 0.1U25Y
Q31
MMBT3904
Q32
VCC3
5VSB
R226
4.7KR
DDR AND DDR II VOLT SELECT
DDRTYPE
PULL LOW
PULL HIGH
C314
0.1U25Y
6
5VSB
R217
X_1KR
R219
10KR
5VSB
R223
X_1KR
R220
10KR
1
2
3
4
5
6
7
8
9
10
11
12
C299 0.1U25Y
5VSB
R214
R211 4.7KR
VDIMM
2.5V
1.8V
3VDLDEC#
C290
X_102P
EXTRAM
FP_RST#
PCIRST#
HDD_RST#
DEV_RST#
VDD_GD
VDD_EN
1.25VREF
VCC5
SLOT_RST#
VCC3
2.5VDDA
AGND0
C289 0.47U10X
X_4.7KR
5
AMD suggest
checking CPU_GD
edge rate
39
41
42
43
44
45
46
47
48
S3#40S5#
I2C_CLK
PWR_OK
RSMRST#
I2C_DATA
CPU_PWGD
CHIP_PWGD
PLED1/EXTRAM
PLED0/3VDLDEC#
PSIN#13PSOUT#14MEMBT15SS165VSB17DDRTYPE18VDIMM_LSEN
C285
0.1U25Y
R208
2.2KRST
5
19
C277
VDIMM_LDRV
VDIMM_HSEN
VDIMM_HDRV
20
21
22
X_1U16Y0805
4
VSUS2_5
VCC3
change R value from 4.7K to 330R
R213
R215
330R
5VSB
C273
0.1U25Y
37
38
5VSB
5VUSB_DRV
1.2VLDT_DRV
1.2VLDT_SEN
TMP_FAULT#
3VSB_SEN233VSB_DRV
24
U25
GND
36
C1
35
C2
34
CHRPMP
33
AGND1
32
31
5V_DRV
30
VAGP_DRV
29
VAGP_SEN
28
WD_DET
27
26
25
MS-6_BC
WATCHING DOG TIMER SELECT
WD_DET
THESE OUTPUT AND INPUT PIN MUST
330R
BE PULL HIGH
CPU_GD 5
ALL_PWRGD 18,26
SMBCLK1 7,8,17,21,23
SMBDATA1 7,8,17,21,23
RSMRST# 18
SUSC# 17
SUSB# 17,25,32
PW_OK 26
C282
X_102P
9VSB VCC3
C267
0.1U16X
5VSB_DRV
5V_DRV
R203
R204
X_10KR
10KR
5VSB
TIMER
OFF PULL LOW
P3055LD
R209
1KRST
EC49
PULL HIGH
VCC3
EC40
+
S
Q34
G
EC32
D
D
EC34
P3055LD
S
+
CD1000U6.3EL15
CD1000U6.3EL15
VDD_25_SUS
EC38
Q33
G
+
CD1000U6.3EL15
ON
CD1000U6.3EL15
+
DDR 2.5V
+
X_CD470U10EL11.5
4
3
LINEAR MODE
CPU PWR_GD OUTPUT
CHIP PWR_GD OUTPUT
I2C BUS
I2C BUS
CONNECT TO SOUTH BRIDGE RSMRST# SIGNAL
SOUTH BRIDGE POWER CONTROL(SLP_S4# OR SUSB#) SIGNAL
SOUTH BRIDGE POWER CONTROL(SLP_S3# OR SUSC#) SIGNAL
ATX POWER OK INPUT
Add 8 vias in Pin3
CHARGE PUMP
VOLTAGE
OUTPUT
C268
1U16Y0805
THRMTRIP# 5,21
CONNECT TO CPU
C171
X_102P
THE TWO MODE ONLY ONE MODE PRESENT
SINGLE MODE DUAL MODE
THIS MODE SELECT BY PIN
47 PULL HIGH 5VSB
THE VDIMM_HSEN IN LINEAR MODE
DDRTYPE
DDR
DDR II
THIS POINT VOLT CAN'T SETTING
BELOW 2.9V
C294
3VDUAL
X_102P
VDIMM_HSEN
VREF
2.0V
1.7V
3
1 2
+
2
R210
10KR
5VSB
8
7
6
8
7
6
VDD_12_A
Routed as pour to
CPU width >
250mils .
5V_STR
5V_STR
G
5V_DUAL
D
VDDQ
Q7
PHD45N03LTA
S
VDDQ
EC15
CD470U6.3EL11
VDD_12_A
RSMRST# 18
C278
1U10Y
VCC
VCC
C129 X_C2200P16X
C128 X_C2200P16X
VCC3
V1.0
D
G
S
+
EC30
CD1000U6.3EL15
3VDUAL
Q17
1
2
3
4 5
NN-P07D03LV_SO8
Q20
1
2
3
4 5
NN-P07D03LV_SO8
Q22
PHD45N03LTA
THIS MODE SELECT BY
PIN 47 PULL LOW
3VSB REGULATE BY 5VSB AND VCC3
VCC3
Add 8 vias in Pin1
3VDUAL
EC43
CD470U10EL11.5
5V_DRV
3VSB_DRV
1 2
+
EC36
CD470U10EL11.5
MSI
Title
Size Document Number Rev
Date: Sheet of
Q28
1
2
3
4 5
NN-P07D03LV_SO8
8
7
6
5VSB
+
EC35
CD1000U6.3EL15
MICRO-STAR INt'L CO., LTD.
ACPI Power (MS-6)
MS-7056
2
1
EC20
+
CD1000U6.3EL15
28 36 Wednesday, July 21, 2004
1
0A
System Voltage Regulator
9VSB
R229
1KR
1.25VREF 28
1.25VREF
103P
C286
R212
120RST
8 4
3
+
2
-
R225
120RST
U24A
LM358_#B
1
Q27
G
VCC3
D
Dual Layout Footprint
P3055LD
S
VCC2_5
+
VCC2_5=1.25X(R596+R597)/R597
EC33
CD470U10EL11.5
3VDUAL
A C
D9
1N4001S
VT8237 Suspend 2.5V power
1
2
4
6
8
A C
D8
X_1N4148S
D7
SC431L
RN53
8P4R-33R
3 1
2
VSUS2_5 VSUSNB
1 2
EC31
+
C10U16EL
C250
0.1U25Y
VSUSNB(1.5V)=1.24*(R198+R197)/R197+Iadj*R198
RN53(min)=1.24*(R198+R197)/R197+Iadj*R198
3
5
7
R198
100RST
R197
499RST
VCC
R55 X_10R-1206
Provide 2.5V for TV Out function circuit.
VCCA AVDD2_5
EC14
X_10U16Y1206
AVDD2_5=1.25*(R74+R75)/R75+Iadj*R75
Vref Typical 1.25V, Limits 1.23V to 1.27V
Iadj Typical 55uA, Limits 100uA
U10
X_YLT1087S-0.8A
VIN3VOUT
ADJ
1
2
R74
X_100RST
R75
X_100RST
C67
10U6.3X0805
If 0A TV-Out Quality OK then use
this circuit for cost down.
AVDD2_5 VCC2_5
R476
R477
X_0R0805
X_0R0805
1 2
CP27
1 2
CP28
Vref Typical 1.24V, Limits 1.224V to 1.258V
Iadj Typical 0.15uA, Limits 0.5uA
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet of
System Voltage Regulator
MS-7056
29 36 Wednesday, July 21, 2004
0A
A
Add R507
FP_RST# 7,26,28
IR 19
4 4
3 3
R507 0R
R508 X_0R
SRS 32
MP_RTS 25
MP_DTR 25
CD_SMI# 17
C357 0.1U25Y
MP_CTR_PWRON 26
IDE_LED 26
PLED1 26,28
PLED2 26,28
BASS 32
BASS_DETECT 32
B
IR_OR_RST#
R396 300RST
VCC
C355
X_0.1U25Y
LCM1
1 2
3 4
5
7 8
11 12
13 14
15 16
17 18
19 20
21 22
23 24
H2X13(25)_black-2pitch
ROCK
POPS
CLASSIC
EQ_CYC
MP_RTS
MP_DTR
IR_OR_RST#
BASS
MP_CTR_PWRON
PLED2
IDE_LED
PLED1
OS_SEL
MP_TXD
MP_RXD
FLAT
SRS
R502 10KR
C594 0.1U25Y
C
C337
0.1U25Y
7
8
OS_SEL 19
MP_RXD 25
MP_TXD 25
FLAT 32
ROCK 32
POPS 32
CLASSIC 32
EQ_CYC 32
5VSB
135
8P4C-220P50N
246
CN22
R279 10KR
R501 10KR
VCC
135
7
7
8P4C-220P50N
246
8
8
CN20
6
10 9
26 25
135
135
7
8P4C-220P50N
8P4C-220P50N
246
CN21
246
8
CN23
D
E
16V/CAP: EC561 NP: C11-1063027-T04
2 2
1 1
STR STD
SUSB#
LHL
SUSC#
FP: C1206MS
L
A
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
B
C
D
Date: Sheet of
IDE & BlueBird
MS-7056
E
30 36 Wednesday, July 21, 2004
0A
A
4 4
HP_ON 32
VCC
SPDIFIN 32
B
DGND ANGD
HP_ON
SPDIFOUT
R92 100KR
AVDD_5VA
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
RN6
X_8P4R-15KR
C100 1U10Y
C98 1U10Y
C424 1U10Y_B
C420 1U10Y_B R488 X_4.7KR
RN7
X_8P4R-10KR
C
LEF_O
CEN_O
SROU_R
SROU_L
FB19
X_80L-0603-700mA
CP1 1U10Y
CP15 0 .1U25Y
FB31
X_80L-0603-700mA_B
ANGD
D
CPU_12V
L13
80L-0603-700mA
2 1
+12V_ASBY
EC21
10U16Y1206
U12
YLT1087S-0.8A
VIN3VOUT
16V/CAP: EC559 NP: C11-1063027-T04 FP: C1206MS
E
AVDD_5VA
2
R90
ADJ
100RST
1
R87
300RST
ANGD
C90
10U6.3X0805
R89 10KR
R88 10KR
C628 1U10Y
C408
102P_B
ANGD
C82
1U16Y0805
LINE_OUT_R 32
LINE_OUT_L 32
FRONT_MIC_L 32
FRONT_MIC_R 32
C81
X_1U16Y0805
REAR AUDIO CONNECTOR
J3B
LINE_OUT
AUDIO_6CH
J3D
6
7
8
9
17
29
SR_OUT
AUDIO_6CH
J3E
30
31
32
33
25
C/W_OUT
AUDIO_6CH
J3C
LINE_IN
AUDIO_6CH
J3A
14
15
MIC_IN
16
AUDIO_6CH
J3F
AUDIO_6CH
D
26
27
28
23
10
11
12
13
18
1
2
4
5
3
VCC
SPDIF_OUT
GND
GND
MSI
Title
Size Document Number R ev
Date: Sheet of
FB13
601S
C383
C24
470P_B
ANGD
ANGD
ANGD
FB12
ANGD
FB9
5020 change
to 5010
R495 22R_B
5010 change
to 5020
470P
20
19
21
22
24
601S
601S
601S
601S
601S
601S
601S
601S
R490 1KR
601S
ANGD
FB11
FB8
FB5
FB7
FB6
FB26
FB10
ANGD
MICRO-STAR INt'L CO., LTD.
Audio Codec
MS-7056
E
SPEAKER_R 32
SPEAKER_L 32
SROU_R
SROU_L
CN27
7
8
5
6
3
4
1
2
8P4C-470P50N_B
CLINR_2
CLINL_2
CN26
7
8
5
6
3
4
1
2
8P4C-470P50N_B
REAR_MIC_SEN
REAR_MIC_R
REAR_MIC_L
5VSB
SPDIFOUT
C2
C1
X_10P
0.1U25Y
31 36 Wednesday, July 21, 2004
ANGD
LEF_O
CEN_O
ANGD
0A
ANGD
AVDD_5VA
U13
36
35
34
NC
33
NC
32
CAP2
31
NC
30
29
28
27
VREF
26
C407 0.1U25Y_B
25
C413 1U16Y0805_B
C419 1U16Y0805_B
C416 0.1U25Y_B
CVRDA
CVRAD
CAFILT2
CAFILT1
VREFOUT
CLINR_2
CLINL_2
AVDD_5VA
AVDD_5VA
C85 1U10Y
C83 1U10Y
C_VREF
EC23
10U6.3X0805
R91 10KR
R93 10KR
IS FOR ALC658 OPTION
C
C84
0.1U25Y
ANGD
REAR_MIC_R
REAR_MIC_L
AVDD_5VA
102P_B
EC22
10U6.3X0805
C409
C107
0.1U25Y
CBITCLK
C99 1U10Y
C101
0.1U25Y
ANGD
R493
10KR
VIDEO_L
R473
X_10KR_B
VCC3
C103
0.1U25Y
R478 1KR_B
R489 X_10KR_B
R494
10KR
ANGD
R474
X_10KR_B
ANGD
1
DVDD1
2
XTL_IN
3
XTL_OUT
4
DVSS1
5
SDATA_OUT
6
BIT_CLK
7
DVSS2
8
SDATA_IN
9
DVDD2
10
SYNC
11
RESET#
12
PC_BEEP
R99
1KR
R94 X_1KR
C97 1U10Y
C94 1U10Y
R475
X_10KR_B
NC48NC47NC46NC45NC
PHONE_IN13AUX-L14AUX-R15NC16NC17CD-L18CD-GND_REF
C92 X_1U10Y
C70 X_1U10Y
C89 X_1U10Y
B
44
42NC41NC40NC39
43
NC
AVSS2
ALC658
19
REAR_MIC_SEN
38
37
AVDD2
MONO_OUT
VREFOUT
CD-R20MIC121NC22L-IN-L23L-IN-R
24
CLINR_1
CLINL_1
C87 1U10Y
L_OUT_R
L_OUT_L
AFILT2
AFILT1
AVSS1
AVDD1
ALC658
C88
1U10Y
R102 X_1MRST
Y3
24.576MHZ16P_D
C105
22P
T* Frequency
Recheck in 0A
AC_SDOUT 17,21
3 3
2 2
1 1
AC_BITCLK 17
MDC_BITCLK 21
AC_SDIN0 17
AC_SYNC 17,21
AC_RST# 17,21
FRONT_MIC_SEN 32
TV-D1X4_YELLOW
X_CD-D1X4_BLACK
PHONE 21
TVIN1
CDIN1
4
4
3
3
2
2
1
1
ANGD
4
4
3
3
2
2
1
1
ANGD
A
C106
10P
ANGD
R491 1KR
R492 1KR
TVCR
TVCL
R43
X_0R
C104
22P
CXIN
CXOUT
R103 22R
R523 22R
C627
X_10P
R479
100KR_B
RN4
X_8P4R-1KR
1
3
5
7
2
4
6
8
A
ANGD
HP_ON 31
R391 4.7KR
Q40
2N7002
G
GND
2
24
23
22
21
20
19
18
17
16
SMF
15
14
GND
13
VCC
2
3
4
5
8
6
7
1
LOUT_SL
G
D
G
S
SRS_OUTR_1
SRS_CTIN
SRS_CTOUT
SRS_SPIN
SRS_SPOUT
SRS
SRS_MOD1
SRS_MNGN
SRS_TEST SRS_PF3
SRS_SMF
AUDIO1
D
S
S
D
ANGD ANGD
OUTR_1
Value
change
ANGD
+9V_ASBY
Q42
NDS351AN
G
Q53
NDS351AN
R428
4.7KR_B
ANGD
FRONT_MIC_R 31
FRONT_MIC_SEN 31
FRONT_MIC_L 31
1
3
4 4
ANGD
5VSB
5
7
8P4C-470P50N
SPEAKER_R 31
SPEAKER_L 31
R497 4.7KR
G
3 3
2 2
1 1
SUSB# 17,25,28
SPDIFIN 31
SRS_INL
SRS_INR
SRS_BPF1
SRS_BPF2
SRS_BPF3
SRS_PF1
SRS_PF2
SRS_PF4
SRS_PF5 SRS_VREF
SRS_OUTR
SRS_OUTL
CN24
D
S
VCC
1
2
3
4
5
6
7
8
9
10
11
12
2
4
6
8
G
Q52
2N7002
VCC
R503 10MR
CN14
0.1U25Y
C368
U8
LIN
RIN
BPF1
BPF2
BPF3
PF1
PF2
PF3
PF4
PF5
ROUT
LOUT
TA2136N
R480 1KR
SPEAKER_R
SPEAKER_L
Q51
D
2N7002
S
C356
0.1U25Y
VCC3IN
SPDIF-D5
1
R500
22R
SPDIFIN
A
LOUT_SR
5VSB
C365
X_22P
CTIN
CTOUT
SPIN
SPOUT
MODE1
MODE2
MNGN
TEST
VREF
R427
AMP_INR
B
ANGD
Q41
D
NDS351AN
5
1
2
3
4
A
C
E
B
D
F
AJ310A-2 switch
S
R510
10MR
FRONT AUDIO CONNECTOR
C74 0 .1U25Y
ANGD
U11
1
OUT A
3.9KR_B
2
INA(-)
OUT B
3
INA(+)
4
GND
INB(+)
TDA1308_SOIC8
5010 change
to 5020
C558 0.1U25Y
C562 0.1U25Y
Circuit III
+12V_ASBY
R516
6.49KR1%
ANGD
B
AUDIO2
8
VDD
7
6
INB(-)
5
ANGD
U3
1
VIN
2
VOUT
3
VOUT
4
ADJ
LM317_SOIC8
R515 1KR
CP29
R85
100KR
ANGD
SRS_PF4
R512 X_0R_B
R513 X_0R_B
Value
change and
10 to 20
CP30
OUTL_1
Value
change
R431 4.7KR_B
R86 100KR
R54 110KRST
SRS_VREF
SRS_PF4
R65 4.32KRST
+9V_ASBY
ANGD
LINE_OUT_R 31
LINE_OUT_L 31
AVDD_5VA
R430 3.9KR_B
AMP_INL SRS_OUTL_1
C80
1U10Y
SRS_VREF
8
NC
7
VOUT
6
VOUT
5
NC
C
1 2
1 2
SRS_PF2
EC6
10U10Y1206
C
R511 X_20KR_B
EC48 10U10Y1206
EC47 10U10Y1206
R514 X_20KR_B
AVDD_5VA
C58 0.47U16Y
R62 3.9KR
R58 47KR
SRS_PF4
SRS_PF2
SRS_VREF
SRS_OUTR_1
SRS_OUTL_1
C21 1500p
E_OUT_L
E_OUT_R
C46 1500p
LOUT_SR
LOUT_SL
E_OUT_L
EC7 10U10Y1206
E_OUT_R
EC10 10U10Y1206
SRS_VREF
SRS_PF11
SRS_VREF
C66 0.47U16Y
R67 51KR
R68 1.3KRST
C78 0.1U25Y
EC19 C10U16EL
EC16 C10U16EL
ANGD
R425 X_0R_B
R424 X_0R_B
ANGD
R20
5.6KRST
C57 0.1U25Y
R56 1KR
C64 472P
+
+
C554 0.068u
C42 0.068u
C34 1500p
C47 1500p
R40
5.6KRST
ANGD
R524 22R0805
R525 22R0805
SRS_INL
SRS_INR
SRS_BPF1
C55
SRS_BPF2
0.1U25Y
SRS_BPF3
SRS_PF1
SRS_PF2
SRS_PF3
SRS_PF4
SRS_PF5
SRS_OUTR
SRS_OUTL
E_IN_R
E_IN_L
0.1U25Y
C384
R498
1KR
ANGD ANGD
LINE_OUT_R
LINE_OUT_L
CD470U6.3EL11
CD470U6.3EL11
1
2
3
4
5
6
7
8
9
10
11
12
16V/CAP: C565 NP: C93-1011621-G01 FP: 100U_16V
16V/CAP: EC69, EC70 NP: C11-1063027-T04
FP: C1206MS
D
22
23
24
1
2
3
4
5
20
21
14
7
U9
LIN
RIN
BPF1
BPF2
BPF3
PF1
PF2
PF3
PF4
PF5
ROUT
LOUT
X_TA2136N
D
U2
BR2
BR1
JAZZ_CTR
INR
CLASSIC_CTR
INL
POPS_CTR
BL1
ROCK_CTR
BL2
FLAT_CTR
TL
OUTL
OUTR
TR
BLED
BIAS
PT2389
R499
1KR
R426 X_0R
R429 X_0R
EC12
EC13
E
DEFAULT +9V REQUIREMENT
ROCK
POPS
CLASSIC
JAZZ
+9V_ASBY
R10
R9
4.7KR
4.7KR
Q2
D
2N7002
0.1U25Y
C43
D
G
S
ANGD
G
S
ANGD
RN112
8P4R-2.7KR
1 2
3 4
5 6
7 8
BASS 30
EQ_CYC 30
6
VCC
19
18
17
16
15
13
3D
12
BB
11
CYC
10
MUTE
9
SEL
8
GND
ROCK 30
POPS 30
CLASSIC 30
FLAT 30
BASS_DETECT 30
JAZZ
CLASSIC
POPS
ROCK
FLAT
0.1U25Y
C23
ANGD
+9V_ASBY
ANGD
R521
X_100KR_B
0.1U25Y
C22
R496
1KR
Q1
2N7002
0A BOM Error Add in MCE.
OUTR_1
OUTL_1
OUTR_1
OUTL_1
ANGD
MS-7056
SRS_VREF
SRS_VREF
E
SRS 30
32 36 Wednesday, July 21, 2004
CTIN
CTOUT
SPIN
SPOUT
MODE1
MODE2
MNGN
TEST
SMF
VREF
GND
VCC
SRS_CTOUT
23
SRS_SPIN
22
SRS_SPOUT
21
20
SRS_MOD1
19
SRS_MNGN SRS_PF21
18
SRS_TEST
17
SRS_SMF
16
SRS_VREF
15
14
13
MSI
Title
Size Document Number R ev
Date: Sheet of
SRS_CTIN
24
R50 1KR
R49 1KR
R69 1KR
R73 1KR
R77 1 KR
R76 1 KR
C73 4.7U10Y0805
EC18 10U10Y1206
+9V_ASBY
MICRO-STAR INt'L CO., LTD.
Audio EQ&SRS&Front Audio Jack
VCC3
ANGD
R108
1KR
0A
5
BULK / Decopuling
4
3
2
1
D D
VCC3
C596
C597
0.1U25Y
VCC
5010 change
to 5020
C C
5010 change
to 5020
5010 change
to 5020
B B
5010 change
to 5020
C608
+12V
C611
VCORE
C613
CLKVCC3
C623
EMI Solution
C598
C599
X_0.22U16Y
X_0.22U16Y_B
5010 change
to 5020
C609
C610
X_0.22U16Y
X_0.22U16Y_B
X_0.22U16Y_B
X_0.22U16Y_B
0.1U25Y
C612
C614
C624
X_0.22U16Y
0.1U25Y
C615
C616
X_0.22U16Y
X_0.22U16Y
C625
C626
0.1U25Y
0.1U25Y
C600
X_0.22U16Y
C635
X_0.1U25Y
C617
X_0.22U16Y
0.1U25Y
C601
C602
C603
C604
C605
C606
0.1U25Y
0.1U25Y
0.1U25Y
C618
X_0.22U16Y
X_0.22U16Y
X_0.22U16Y
VDD_25_SUS
VCC3
ANGD
0.1U25Y
C632
X_0.1U25Y
C637
X_0.1U25Y
C607
0.1U25Y
0.1U25Y
C633
47P50N
C629
X_0.1U25Y
0.1U25Y
C634
X_0.1U25Y
C630
X_0.1U25Y
C631
X_0.1U25Y
A A
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
BULK / Decoupling
MS-7056
1
33 36 Wednesday, July 21, 2004
0A
5
K8 CPU Power
4
NB & SB & AGP Power
3
2
1
Other Power
DDR Side CPU Side
K8 Vcore ->
"VCORE" (42A)
D D
VDDA_2.5 Power ->
DDR Power ->
"VDD_25_SUS"
(9.5A)
"VDDA_25" (0.11A)
DDR-VTTPower ->
HT Power ->
"VTT_DDR_SUS" (5.21A)
"VDD_12_A"&"VLDT0"
NB & SB Core-Power
-> "VCC2_5" (?A)
NB & SB Core-Suspend
Power -> "VSUS2_5" (?A)
NB AGP8X Power ->
"VDDQ" (1.5A)
5VDU
3VDU
DDR_3VDUAL
9VSB
(2A)
ATX Power
Supply
VSUS2_5 -> SB
C C
+5VSB
5VDUAL 3VDUAL
VCC
P3VA ->
For 1394
Charge Pump
-> 9VSB
B B
+12V
VCORE ->
K8 CPU
+5VR ->
Audio
DDR_25_SUS
-> DDR
DDR_3VDUAL
VDDA_25 ->
K8 CPU(I/O)
VCC3
VTT_DDR_SUS
-> DDR
VDDQ
A A
-> AGP
-12V
5
VCC2_5 ->
NB & SB (
VLINK )
4
VDD_12_A
-> HT
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
3
2
Date: Sheet of
Power Generation
MS-7056
1
34 36 Wednesday, July 21, 2004
0A
MH6
MH1
MH5
MH2
MH7
X_HOLE_SCREW
CPU Holes
MH8
X_HOLE_SCREW_2
FM16
X
X_FM
FM21
X
X_FM
FM20
X
X_FM
FM3
X
X_FM
X_HOLE_SCREW
X_HOLE_SCREW_2
FM24
X
FM22
X
FM1
X
X_FM
FM23
X
X_FM
MH10
X_FM
X_FM
X_HOLE_SCREW
MH11
X_HOLE_SCREW_2
FM10
X
X_FM
FM5
X
X_FM
FM15
X
FM2
X
X_FM
X_FM
X_HOLE_SCREW
MH9
X_HOLE_SCREW_2
X_FM
X_FM
FM14
X
X_FM
FM4
X
X_FM
FM11
X
FM7
X
ANGD
FM19
X
FM18
X
X_FM
X_FM
X_HOLE_SCREW
PCB1
P01-705600A-P42
P01-7056100-G37
FM9
X
FM13
X
FM8
X_FM
FM6
X_FM
X
X_FM
X
X_FM
FM17
X
X_FM
FM12
X
X_FM
HOLE
MH3
MH4
Impedance Test
1
HOLE
1
VCC
T1
1
2
X_YJ102
T2
1
2
X_YJ102
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Screw Hole and FMark
MS-7056
35 36 Wednesday, July 21, 2004
0A
5
4
3
2
1
Revision Initial ver:0A on
D D
0A Revision History (Changes from MS-6741 Rev 0B)
Sheet Ap. Date
C C
De sciption
0B Revision History (Changes from MS-6741 Rev 0A)
Ap. DateDe sciption Sheet
B B
A A
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
History
MS-7056
1
36 36 Wednesday, July 21, 2004
0A