MSI MS-6742 Schematics
1
Cover Sheet 1
Block Diagram
GPIO
Intel mPGA478B CPU - Signals
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP & LAN Signals
DDR DIMM 1,2
LAN RTL8101L
ICH4(1)
ICH4(2)
ICS952619 & FWH & FDD
A A
LPC I/O -W83627HF
AC97 Audio
AGP 4X/8X Slot & FAN
PCI Slots 1 & 2 & 3
PCI Slots 4 & 5 & 6
ATA33/66/100 IDE & Video Connectors
USB Connectors
ATX & Front Panel
2
3
4
5Intel mPGA478B CPU - Power
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21W83302 ACPI controller
22
MS(6742)
Intel (R) Springdale (GMCH) + ICH4 Chipset
Intel Northwood & Prescott mPGA478B Processor
CPU:
Intel Northwood/Prescott
System Chipset:
Intel Springdale - GMCH (North Bridge)
Intel ICH5 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
AC'97 Codec -- C-medin/ALC650
LPC Super I/O -- W83627HF
LAN --RTL8101L
CLOCK --ICS 952619
Main Memory:
DDR * 2 (Max 2GB)
Expansion Slots:
PCI2.3 SLOT * 6
Intersil PWM:
Controller: Intersil 6556B
Driver: Intersil 6601B,6602B
/ Intersil 6301
Version 0A
VRM 9.0 FMB2
DLED BRACKET
23
24
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
1
Date: Sheet of
COVER SHEET
MS-6742
1 27Tuesday, December 17, 2002
0A
1
VRM 10
Intersil 6556
Intel mPAG478B Processor
Block Diagram
3-Phase PWM
FSB
AGP 1.5V
4X/8X
Connector
Analog
Video
Springdale
Out
Kenai II
/
Kinnereth R
IDE Primary
IDE Secondary
A A
USB Port 0
CSA
LCI
UltraDMA 33/66/100
ICH4
Link
HUB
64bit DDR
Channel 1
64bit DDR
Channel 2
2 DDR
DIMM
Modules
(1+1)
PCI CNTRL
PCI ADDR/DATA
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
PCI Slot 6
USB Port 1
USB Port 2
USB
LPC Bus
USB Port 3
USB Port 4
LPC SIO
USB Port 5
Winbond
83627HF
AC'97 Codec
AC'97 Link
Flash
Keyboard
Mouse
Floopy Parallel Serial
1
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
MS-6742
2 27Tuesday, December 17, 2002
0A
1
ICH5
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23
I
PREQ#B
I
PREQ#B
I
PIRQ#E
I
PIRQ#F
I
PIRQ#G
I
PIRQ#H
I
GPI6
I
GPI7
I
CSA_PME#
I
OC4#
I
OC5#
I
SIO_SMI#
I
EXTSMI#
I
SIO_PME#
I OC#6
OC#7
I
PGNT#A
O
O
PGNT#B
O GPO18
BIOS_WP#
O
O
GPO20
O GPO21
OD
O
GPO23
GPIO 24 I/O GPIO24
GPIO 25 I/O LAN_DISABLE#
FunctionTypeGPIO Pin
A A
*
GPIO 27
GPIO 28
GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
GPIO 49
I/O
GPIO27
I/O GPIO28
I/O
GPIO32
I/O
GPIO33
I/O
GPIO34
I
GPI41
I
O PGNT#4
CPUPWRGD
OD
Power well
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
default output
default output
default output
default output
default output
default output
default output
PCI Config.
DEVICE
INTA#
INTB#
PCI_REQ#0PCI Slot 1
PCI_GNT#0
INTC#
INTD#
PCI Slot 2
INTB#
INTC#
PCI_REQ#1 AD17 PCICLK1
PCI_GNT#1
INTD#
INTA#
PCI Slot 3 PCI_REQ#2 AD18
INTC#
INTD#
PCI_GNT#2
INTA#
INTB#
INTD#
PCI_REQ#3PCI Slot 4
INTA# PCI_GNT#3
INTB#
INTC#
PCI Slot 5
INTB#
INTC#
PCI_REQ#4 AD21 PCICLK4
PCI_GNT#4
INTD#
INTA#
PCI Slot 6 PCI_REQ#A AD20
INTA#
INTB#
PCI_GNT#A
INTC#
INTD#
IDSEL
AD16
AD19
DDR DIMM Config.
DEVICE
DIMM 1 MCLK_A0/MCLK_A0#
DIMM 2
1010000B
1010001B
CLOCKADDRESS
MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
CLOCKREQ#/GNT#
PCICLK0
PCICLK2
PCICLK3
PCICLK5
CLK GEN PIN OUTMCP1 INT Pin
13 (PCI_CLK0)
14 (PCI_CLK1)
15 (PCI_CLK2)
16 (PCI_CLK3)
19 (PCI_CLK4)
20 (PCI_CLK5)
FWH
Function
GPI 0 PD_DET
GPI 1
*
GPI 3
*
TypeGPIO Pin
I
I
SD_DET
I
Pull down through 1K ohms (unused)GPI 2
Pull down through 1K ohms (unused)
I
Pull down through 1K ohms (unused)GPI 4
I
PCI RESET DEVICE
Signals
PCIRST#1
HD_RST#
Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Scondary IDE
Target
MSI
Title
Size Document Number Rev
1
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
General Purpose Spec
MS-6742
3 27Tuesday, December 17, 2002
0A
8
7
6
5
4
3
2
1
CPU SIGNAL BLOCK
HA#[3..31]6
HA#17
HA#25
HA#27
HA#30
D D
CPU1A
HDBI#0
HDBI#[0..3]6
FERR#11
STPCLK#11
HINIT#11,13
HDBSY#6
HDRDY#6
HTRDY#6
HADS#6
HLOCK#6
HBNR#6
HIT#6
HITM#6
HBPRI#6
C C
B B
HDEFER#6
CPU_TMPA14
VTIN_GND14
THERMTRIP#11
PROCHOT#6
IGNNE#11
SMI#11
A20M#11
SLP#11
BOOT23
BSEL013
BSEL113
CPU_GD12
CPURST#6
HD#[0..63]6
HDBI#1
HDBI#2
HDBI#3
IERR#
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
THERMTRIP#
PROCHOT#
BOOT
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
V22
HA#31
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
A32#
A31#
A30#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
U21
D45#
V25
U23
U24
U26
T23
T22
T25
T26
HA#29
A29#
D44#
R24
HA#28
A28#
D43#
R25
A27#
D42#
P24
HA#26
A26#
D41#
R21
A25#
D40#
N25
HA#24
A24#
D39#
N26
HA#22
HA#23
A23#
D38#
M26
A22#
D37#
N23
HA#21
A21#
D36#
M24
HA#20
A20#
D35#
P21
HA#19
A19#
D34#
N22
HA#18
A18#
D33#
M23
A17#
D32#
H25
HA#16
A16#
D31#
K23
HA#15
A15#
D30#
J24
HA#14
A14#
D29#
L22
HA#12
HA#13
A13#
D28#
M21
HA#11
A12#
D27#
H24
A11#
D26#
G26
HA#10
A10#
D25#
L21
HA#9
A9#
D24#
D26
HA#8
A8#
D23#
HA#7
F26
A7#
D22#
E25
HA#6
A6#
D21#
F24
HA#5
A5#
D20#
F23
HA#4
A4#
D19#
G23
HA#3
A3#
D18#
VID2
VID4
VID3
VID5
AE25A5A4
AD26
AC26
AE1
AE2
AE3
AD2
AD3
DBR#
VSS_SENSE
VCC_SENSE
D17#
D16#
D15#
D14#
D13#
D12#
E24
H22
D25
J21
D23
C26
H21
D11#
G22
ITP_CLK1
ITP_CLK0
D10#
D9#
D8#
B25
C24
VID5#
VIDPWRGD
D7#
D6#
C23
B24
D22
VID4#
D5#
C21
VID3#
D4#
A25
VID1
AE4
VID2#
D3#
A23
VID1#
D2#
VID0
AE5
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D1#
D0#
ZIF-SOCKET478
B22
B21
{Priority}
VCC_SENSE 23
VSS_SENSE 23
VID_GD 21,23
VID[0..5] 23,24
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
TESTHI12
TESTHI11
TESTHI1
TESTHI0
HRS#2
HRS#1
HRS#0
HBR#0
COMP1
COMP0
GTLREF
C116 C220P16X
VIDPWRGD DC Specifications
GTLREF 6
HREQ#[0..4] 6
VCCP
CPU_CLK# 13
CPU_CLK 13
HRS#[0..2] 6
HBR#0 6
HADSTB#1 6
HADSTB#0 6
HDSTBP#3 6
HDSTBP#2 6
HDSTBP#1 6
HDSTBP#0 6
HDSTBN#3 6
HDSTBN#2 6
HDSTBN#1 6
HDSTBN#0 6
NMI 11
INTR 11
Min MaxTyp
0.9
VIL
VIH
It must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
VIDGD rising time is 150ns.
X7R
{VOLTAGE}
R69 62R
R137 62R
R97 62R
R87 62R
R78 62R
R106 61.9R1%
R109 61.9R1%
CPU GTL REFERNCE VOLTAGE BLOCK
0.3
VCCP
R142
49.9R1%
0.63*Vccp
GTLREF
C197
R153
C0.1U16X
100R1%
X7R X7R
CPU ITP BLOCK
ITP_TDI
ITP_TRST#
ITP_TMS
ITP_TDO
ITP_TCK
R76 150R
R92 680R
R104 39R
R77 75R
R81 27R
VCCP
VCCP
HD#52
HD#53
HD#50
HD#51
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#40
HD#41
HD#38
HD#39
HD#36
HD#37
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#18
HD#19
HD#16
HD#17
HD#15
HD#14
HD#12
HD#13
HD#10
HD#11
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0
CPU STRAPPING RESISTORS
RN95
A A
8
7
8P4R-62R
BPM#4
BPM#5
BPM#1 CPU_GD
BPM#2
BPM#3
BPM#0
R91 62R
R89 62R
12
VCCP
34
56
78
6
ALL COMPONENTS CLOSE TO CPU
PROCHOT#
HBR#0
CPURST#
IERR#
5
R140 120R
R75 300R
R101 220R
R86 62R
R588 62R
VCCP
MSI
Title
Size Document Number Rev
4
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Signals
2
MS-6742
4 27Friday, January 03, 2003
1
0A
8
7
6
5
4
3
2
1
D15
D17
VCC
VCC
VSS
VSS
E7E9F10
D19D7D9
VCC
VSS
VCC
VSS
VCC_VID
C33
X_C1U10Y
E10
E12
E14
E16
E18
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
F12
F14
F16
F18F2F22
F25F5F8
CPU VOLTAGE BLOCK
VCC_VID21
VID Voltage is from 1.14V to 1.32V.
It is derived from 3.3V.
It should be able to source 150mA.
D D
VCCP
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
VCC
VSS
AF19
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
C15
C17C2C19
C22
C25C5C7C9D12
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AA23
C C
B B
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC22
AC25
VSS
VSS
AA4
VSS
AA7
VSS
AA9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB3
VSS
AB6
VSS
AB8
VSS
VSS
VSS
VSS
VSS
VSS
AC2
VSS
VSS
VSS
AC5
VSS
AC7
VSS
AC9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
VSS
AF6
AF8
B10
B12
B14
B16
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B18
B23
B20
B26B4B8
C11
C13
It drives the power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D16
D18
D20
VSS
D21D3D24D6D8E1E11
D14
VCC
VSS
C10
C12
C14
C16
C18
C20C8D11
D13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E13
E15
E17
E19
E23
E4
E26
E20E8F11
VCC
VCC
VSS
VSS
VCC
VSS
G21G6G24
F13
F15
VCC
VCC
VSS
VSS
G3H1H23
1.2V 150mA
C41
0.1u
Near processor
F17
F19
F9
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
H26H4J2
AF4
VCC-VID
VSS
AD20
AF3
VCC-VIDPRG
VSS
VSS
VSS
J22
J25J5K21
AE23
VCCA
VSSA
VCC-IOPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZIF-SOCKET478
{Priority}
CPU_IOPLL
C38
C46
{VOLTAGE}
VSSA
X_C10U10Y0805
{VOLTAGE}
C10U10Y0805
AD22
Y5
The ESL is less than 5nH, and the ESR is less than 0.3ohm.
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
It support DC current if 100mA.
L2 10U100m_0805
L3 10U100m_0805
DC voltage drop should
be less than 70mV.
VCCP
CPU DECOUPLING CAPACITORS
VCCP
A A
Place these caps within socket cavity Place these caps within south side of processor
VCCP VCCP VCCPVCCP VCCP
C93
C10U10Y1206
C89
C10U10Y1206
C85
C10U10Y1206
C77
C10U10Y1206
C72
C10U10Y1206
C67
C10U10Y1206
8
C94
C10U10Y1206
C90
C10U10Y1206
C86
C10U10Y1206
C78
C10U10Y1206
C73
C10U10Y1206
C68
C10U10Y1206
7
C24
X_C10U10Y1206
C12
X_C10U10Y1206
C16
X_C10U10Y1206
C8
X_C10U10Y1206
C29
C10U10Y1206
C21
C10U10Y1206
Place these caps within north side of processor
C23
C10U10Y1206
C25
C10U10Y1206
C27
C10U10Y1206
C13
X_C10U10Y1206
C15
X_C10U10Y1206
C10
X_C10U10Y1206
6
C22
X_C10U10Y1206
C14
X_C10U10Y1206
C11
X_C10U10Y1206
C26
X_C10U10Y1206
C28
X_C10U10Y1206
C9
X_C10U10Y1206
C118
C10U10Y1206
C120
C10U10Y1206
C122
C10U10Y1206
C119
X_C10U10Y1206
C121
X_C10U10Y1206
MSI
Title
Size Document Number Rev
5
4
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Power
2
MS-6742
5 27Tuesday, January 07, 2003
1
0A
8
HA#[3..31]4
D D
HADSTB#04
HADSTB#14
HBR#04
HREQ#[0..4]4
HRS#[0..2]4
BSEL0_SPG13
BSEL1_SPG13
HBPRI#4
HBNR#4
HLOCK#4
HADS#4
HIT#4
HITM#4
HDEFER#4
HTRDY#4
HDBSY#4
HDRDY#4
MCH_CLK13
MCH_CLK#13
MS5_POK21
CPURST#4
PCIRST#110,14,21
PROCHOT#4
R162 20R1%
GTLREF4
VTT
NEXT
GMCH
8
ICH_SYNC#
GTLREF
0.63*Vccp
R189 X_200R1%
X7R
HSWING
X7R
C C
B B
A A
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
HRCOMP
HSWING
C191
X_C0.01U50X
C149
C0.01U50X
{VOLTAGE}
VCCA_FSB
VCCA_DPLL
D26
D30
L23
E29
B32
K23
C30
C31
J25
B31
E30
B33
J24
F25
D34
C32
F28
C34
J27
G27
F29
E28
H27
K24
E32
F31
G30
J26
G26
B30
D28
B24
B26
B28
E25
F27
B29
J23
L22
C29
J21
K21
E23
L21
D24
E27
G24
G22
C27
B27
B7
C7
AE14
E8
AK4
AJ8
L20
L13
L12
E24
C25
F23
C147
C0.1U16X
{VOLTAGE}
1/4*Vccp
C143 0.1u
U10A
VCCP
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
DBSY#
DRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
CPURST#
RSTIN#
ICH_SYNC#
PROCHOT#
BSEL0
BSEL1
HDRCOMP
HDSWING
HDVREF
R186
301R1%
R150
100R1%
7
B3
A31
VCCA_FSB
VCCA_DPLL
VSS
VSS
C10
C8
7
B4
VCCA_FSB
VSS
C12
C14
VCC_AGP
J6J7J8J9K6K7K8K9L6L7L9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C16
VSS
C18
C20
C22
C24
C26
C28D1D11
D9
0.1u
VCC
VSS
VCC
VSS
D13
C208
L10
VCC
VSS
D15
I=35mA
L11
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
D17
D19
D21
I=30mA
VCCA_FSB
0.1u
VCCA_DPLL
M10
D23
6
N11N9P10
P11
R11
T16
N10
M11M8M9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D25
D27
D29
D31
D33
D35
E3
E1
+
EC24
C205
X_C1U10X0805
ESR is 0.1mohm to GMCH
+
EC26
X_C1U10X0805
6
VCC
VSS
T17
F1
T18
VCC
VSS
F3F5F8
VCC
VSS
T19
U16
T20
VCC
VCC
VSS
VSS
F10
U17
U20
V16
V18
V20
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
F18
F20
F14
F16
F12
CP7
L5 X_0.82U30m
CP8
L7 X_100N300m
W16
F22
5
W19
W20
Y16
Y17
Y18
Y19
Y20
A3
A33
A35B2B25
B34C1C23
C35
E26
M31
AF13
AF23
AJ12
R25
VCC
VSS
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G31
G35
G28
VSS
VSS
VSS
H12
H14
H16H2H20
H5
H18
H8
H9
VCC_AGP
VCC_AGP
5
VCC
VCC
VSS
VSS
F24
F26
X
X
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H22
VSS
H24
H26
H30
H33
J10
J12
J14
J16
ICH_SYNC# MS5_POK ICH_PWROK
4
AN1
AP2
AR3
AR33
AR35
A7A9A11
A13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J18
J20
J22
0 0
1
1 1 1
VSS
J28
J32
J35
K11
K12
K14
K16
10
0
MS5_POK21
4
3
VTT
VSS
M30
VTT
VSS
M33N1N4
3
VTT
VTT
VSS
VSS
R333
X_220R
VTT_FSB1
VTT_FSB2
A15
A21
HD0#
VTT
VTT
HD1#
HD2#
VTT_FSB
VTT_FSB
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
VSS
INTEL-SpringDale
{Priority}
R332
X_1KR
C179 C0.47U16Y
C165 C0.47U16Y
HD#0
B23
HD#1
E22
HD#2
B21
D20
HD#3
HD#4
B22
HD#5
D22
HD#6
B20
HD#7
C21
E18
HD#8
HD#9
E20
HD#10
B16
HD#11
D16
HD#12
B18
B17
HD#13
HD#14
E16
HD#15
D18
HD#16
G20
HD#17
F17
E19
HD#18
HD#19
F19
HD#20
J17
HD#21
L18
HD#22
G16
G18
HD#23
HD#24
F21
HD#25
F15
HD#26
E15
HD#27
E21
J19
HD#28
HD#29
G14
HD#30
E17
HD#31
K17
HD#32
J15
L16
HD#33
HD#34
J13
HD#35
F13
HD#36
F11
HD#37
E13
K15
HD#38
HD#39
G12
HD#40
G10
HD#41
L15
HD#42
E11
K13
HD#43
HD#44
J11
HD#45
H10
HD#46
G8
HD#47
E9
B13
HD#48
HD#49
E14
HD#50
B14
HD#51
B12
HD#52
B15
D14
HD#53
HD#54
C13
HD#55
B11
HD#56
D10
HD#57
C11
E10
HD#58
HD#59
B10
HD#60
C9
HD#61
B9
HD#62
D8
B8
HD#63
HDBI#0
C17
HDBI#1
L17
HDBI#2
L14
C15
HDBI#3
B19
C19
L19
K19
G9
F9
D12
E12
ICH_PWROK 12
VTT
D5D6D7E6E7
F7
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
M26
L25
L26
L35
L31
Q45 X_N-MMBT3904_SOT23
VCC3
Q47 X_N-MMBT3904_SOT23
R383 X_220R
R331 0R
A4A5A6B5B6C5C6
VTT
VTT
VSS
VSS
M27
M28
VCC3
A16
A20
A23
A25
A27
A29
A32
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K18
VSS
K33
K20
K22
K25
K27
K29
L24M3M6
0
0
0
ICH_SYNC#
MS5_POK
2
HD#[0..63] 4
VTT
HDBI#[0..3] 4
HDSTBP#0 4
HDSTBN#0 4
HDSTBP#1 4
HDSTBN#1 4
HDSTBP#2 4
HDSTBN#2 4
HDSTBP#3 4
HDSTBN#3 4
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Springdale - CPU Signals
MS-6742
2
C195
X_C1U10Y
C201
X_0.1u
1
6 27Friday, January 03, 2003
1
0A
8
MCS_A#09
MCS_A#19
D D
MRAS_A#9
MCAS_A#9
MWE_A#9
MA_A[0..12]9
MBA_A09
MBA_A19
C C
MDQM_A[0..7]9
MDQS_A[0..7]9
MCLK_A09
MCLK_A#09
MCLK_A19
MCLK_A#19
MCLK_A29
MCLK_A#29
B B
C0.01U50XC269
C0.01U50XC263
C0.01U50XC270
0.1uC136
C135 X_C2.2U6.3Y
MDQ_A[0..63]9 MCKE_A[0..1] 9
U10B
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AC33
SRAS_A#
Y34
SCAS_A#
AB34
SWE_A#
AJ34
MA_A0
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
XRCOMP
XCOMPH
XCOMPL
XVREF
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21
AL34
AM34
AP32
AP31
AM26
AE33
AH34
AP12
AP16
AM24
AP30
AF31
W33
AN11
AP15
AP23
AM30
AF34
AK32
AK31
AP17
AN17
AK33
AK34
AM16
AL16
M34
H32
V34
M32
H31
N33
N34
P31
P32
AK9
AN9
AL9
E34
SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12
SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5
SBA_A0
SBA_A1
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SMDCLK_A0
SMDCLK_A0#
SMDCLK_A1
SMDCLK_A1#
SMDCLK_A2
SMDCLK_A2#
SMDCLK_A3
SMDCLK_A3#
SMDCLK_A4
SMDCLK_A4#
SMDCLK_A5
SMDCLK_A5#
SMXRCOMP
SMXCOMPVOH
SMXCOMPVOL
SMVREF_A
C144 C0.47U16Y
C162 C0.22U16Y
C170 C0.01U50X
C234 C0.22U16Y
7
MDQ_A1
MDQ_A0
AP10
AP11
SDQ_A0
E35
MDQ_A2
MDQ_A3
MDQ_A4
AM12
AN13
AM10
SDQ_A1
SDQ_A2
SDQ_A3
VCC_DDR
VCC_DDR
VCC_DDR
AA35
R35
AR21
MDQ_A6
MDQ_A7
MDQ_A5
AL10
AL12
AP13
SDQ_A4
SDQ_A5
SDQ_A6
VCC_DDR
VCC_DDR
VCC_DDR
AL7
AR15
AL6
MDQ_A9
MDQ_A8
MDQ_A10
AP14
AM14
AL18
SDQ_A7
SDQ_A8
SDQ_A9
VCC_DDR
VCC_DDR
VCC_DDR
AM1
AM2
AN8
MDQ_B[0..63]9
MDQ_A11
MDQ_A12
MDQ_A13
AP19
AL14
AN15
SDQ_A10
SDQ_A11
SDQ_A12
VCC_DDR
VCC_DDR
VCC_DDR
AP3
AP4
AP5
VCC_DDR
MDQ_A14
MDQ_A15
MDQ_A16
AP18
AM18
AP22
SDQ_A13
SDQ_A14
SDQ_A15
VCC_DDR
VCC_DDR
VCC_DDR
AR4
AP6
AP7
MDQ_A17
MDQ_A18
MDQ_A19
AM22
AL24
AN27
SDQ_A16
SDQ_A17
SDQ_A18
VCC_DDR
VCC_DDR
VCC_DDR
AR5
AR7
AR31
MDQ_A21
MDQ_A20
MDQ_A22
AP21
AL22
AP25
SDQ_A19
SDQ_A20
SDQ_A21
VCC_DDR
SDQ_B0
AJ10
AE15
MDQ_B0
MDQ_B1
6
MDQ_A24
MDQ_A23
AP27
AP28
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_B1
SDQ_B2
SDQ_B3
AL11
AE16
MDQ_B2
MDQ_B3
MDQ_A25
MDQ_A26
AP29
AP33
AM33
SDQ_A25
SDQ_A26
SDQ_B4
SDQ_B5
AL8
AF12
AK11
MDQ_B5
MDQ_B4
MDQ_A29
MDQ_A28
MDQ_A27
AM28
AN29
SDQ_A27
SDQ_A28
SDQ_B6
SDQ_B7
AG12
AE17
MDQ_B8
MDQ_B7
MDQ_B6
MDQ_A30
MDQ_A31
AM31
AN34
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_B8
SDQ_B9
SDQ_B10
AL13
AK17
MDQ_B10
MDQ_B9
MDQ_A33
MDQ_A32
AH32
AG34
SDQ_A32
SDQ_A33
SDQ_B11
SDQ_B12
AL17
AK13
MDQ_B11
MDQ_B12
MDQ_A34
MDQ_A35
AF32
AD32
AH31
SDQ_A34
SDQ_A35
SDQ_B13
SDQ_B14
AJ14
AJ16
AJ18
MDQ_B14
MDQ_B13
MDQ_A36
MDQ_A37
MDQ_A38
AG33
AE34
SDQ_A36
SDQ_A37
SDQ_B15
SDQ_B16
AE19
AE20
MDQ_B15
MDQ_B17
MDQ_B16
MDQ_A40
MDQ_A39
AD34
AC34
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_B17
SDQ_B18
SDQ_B19
AG23
AK23
MDQ_B18
MDQ_B19
MDQ_A41
MDQ_A42
AB31
V32
SDQ_A41
SDQ_A42
SDQ_B20
SDQ_B21
AL19
AK21
MDQ_B20
MDQ_B21
MDQ_A43
MDQ_A44
V31
AD31
AB32
SDQ_A43
SDQ_A44
SDQ_B22
SDQ_B23
AJ24
AE22
AK25
MDQ_B22
MDQ_B23
5
MDQ_A45
MDQ_A46
MDQ_A47
U34
U33
SDQ_A45
SDQ_A46
SDQ_B24
SDQ_B25
AH26
AG27
MDQ_B24
MDQ_B26
MDQ_B25
MDQ_A49
MDQ_A48
T34
T32
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_B26
SDQ_B27
SDQ_B28
AF27
AJ26
MDQ_B27
MDQ_B28
MDQ_A51
MDQ_A50
K34
K32
T31
SDQ_A50
SDQ_A51
SDQ_B29
SDQ_B30
AJ27
AD25
AF28
MDQ_B30
MDQ_B29
MDQ_A52
MDQ_A53
MDQ_A54
P34
L34
SDQ_A52
SDQ_A53
SDQ_B31
SDQ_B32
AE30
AC27
MDQ_B31
MDQ_B33
MDQ_B32
MDQ_A56
MDQ_A55
L33
J33
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_B33
SDQ_B34
SDQ_B35
AC30
Y29
MDQ_B35
MDQ_B34
MDQ_A57
MDQ_A58
H34
E33
SDQ_A57
SDQ_A58
SDQ_B36
SDQ_B37
AE31
AB29
MDQ_B37
MDQ_B36
MDQ_A59
MDQ_A60
F33
K31
J34
SDQ_A59
SDQ_A60
SDQ_B38
SDQ_B39
AA26
AA27
AA30
MDQ_B38
MDQ_B39
MDQ_A61
MDQ_A62
MDQ_A63
G34
F34
SDQ_A61
SDQ_A62
SDQ_B40
SDQ_B41
W30
U27
MDQ_B40
MDQ_B41
MDQ_B42
MCKE_A0
AL20
SCKE_A0
SDQ_A63
SDQ_B42
SDQ_B43
SDQ_B44
T25
AA31
MDQ_B44
MDQ_B43
MCKE_A1
AN19
AM20
SCKE_A1
SCKE_A2
SDQ_B45
SDQ_B46
V29
U25
MDQ_B45
MDQ_B46
4
AP20
AB25
SCKE_A3
SDQ_B47
SDQ_B48
R27
P29
R30
MDQ_B47
MDQ_B48
AC26
AC25
VCCA_DDR
VCCA_DDR
VCCA_DDR
SDQ_B49
SDQ_B50
SDQ_B51
K28
L30
MDQ_B51
MDQ_B49
MDQ_B50
VCCA_DDR
AN4
AL35
VCCA_DDR
SDQ_B52
SDQ_B53
R31
R26
P25
MDQ_B53
MDQ_B52
MDQ_B54
0.1uC200
AM3
AN5
AM5
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B54
SDQ_B55
SDQ_B56
L32
K30
H29
MDQ_B55
MDQ_B56
MDQ_B57
AM6
AM7
AM8
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B57
SDQ_B58
SDQ_B59
F32
G33
N25
MDQ_B59
MDQ_B58
MDQ_B60
VCC_DDR
AN2
AN6
AN7
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B60
SDQ_B61
SDQ_B62
M25
J29
G32
MDQ_B63
MDQ_B62
MDQ_B61
N35
N32
VSS
VCC_DDR
SDQ_B63
SCKE_B0
AK19
AF19
MCKE_B0
MCKE_B1
3
P3P6P8
VSS
VSS
VSS
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMYRCOMP
SMYCOMPVOH
SMYCOMPVOL
SCKE_B1
SCKE_B2
SCKE_B3
INTEL-SpringDale
{Priority}
AG19
AE18
SCS_B0#
VSS
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12
SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5
SBA_B0
SBA_B1
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SMVREF_B
Its current is 5.1A.
U26
T29
V25
W25
W26
W31
W27
AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20
AE27
AD26
AL29
AL27
AE23
Y25
AA25
AG11
AG15
AE21
AJ28
AC31
U31
M29
J31
AF15
AG13
AG21
AH27
AD29
U30
L27
J30
AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30
AA33
R34
R33
AP9
MCKE_B[0..1] 9
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
YRCOMP
YCOMPH
YCOMPL
YVREF
MCS_B#0 9
MCS_B#1 9
MRAS_B# 9
MCAS_B# 9
MWE_B# 9
MA_B[0..12] 9
MBA_B0 9
MBA_B1 9
MDQM_B[0..7] 9
MDQS_B[0..7] 9
MCLK_B0 9
MCLK_B#0 9
MCLK_B1 9
MCLK_B#1 9
MCLK_B2 9
MCLK_B#2 9
C0.01U50XC160
C0.01U50XC159
C0.01U50XC132
0.1uC262
2
R291 150R1%
R286 150R1%
C268 X_C2.2U6.3Y
1
VCC_DDR
{VOLTAGE}
C241 0.1u
VCC_DDR_C3
XRCOMP
YRCOMP
7
VCC_DDR_C2
R290 42.2R1%
R287 42.2R1%
R180 42.2R1%
R161 42.2R1%
values still need verification
XCOMPL
VCC_DDR
VCC_DDR_C3
XCOMPH
AA35AA33
6
R289 30.1KR1%
R283 10KR1%
R251 10KR1%
R252 30.1KR1%
VCC_DDR
VCC_DDR
YCOMPL
R143 30.1KR1%
R145 10KR1% L10 X_1U1_1206
R33
YCOMPH
R166 10KR1%
R146 30.1KR1%
R34
5
VCC_DDR_C2
R35
VCCA_DDR
C239
0.1u
4
CP9 X
+
EC29
X_C1U10X0805
ALE
MSI
VCC_AGP
Title
Size Document Number Rev
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Springdale - Me mory Signals
MS-6742
2
7 27Friday, January 03, 2003
0A
1
A A
8
8
7
6
5
4
3
2
1
C266 0.1u
C243 0.1u
VCC_AGP
P26
P27
P28
P30
P33R1R4
R32T1T3
T6T8T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE32
AE35
AF3
AF11
AF14
AF6
AF9
AD30
VSS
AD33
VSS
AD28
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE1
AE10
AE11
AE12
AE13
AE25
AE26
AE4
U10C
AE6
GAD[0..31]16
D D
C C
GC_BE#[0..3]16
AD_STB016
AD_STB#016
AD_STB116
AD_STB#116
GGNT#16
ST[0..2]16
GFRAME#16
GIRDY#16
GTRDY#16
GDEVSEL#16
GSTOP#16
GAD0
GAD1
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3
ST0
ST1
ST2
RBF#
RBF#16
WBF#
WBF#16
GPAR16
B B
A A
VCC_AGP
SBA[0..7]16
SB_STB16
SB_STB#16
DBI_LO16
R243 43.2R1%
C0.01U50XC251
GSWING16
C0.01U50XC265
AGP_REF16
MCH_6613
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
PIPE#16
GRCOMP
GSWING
GAD0/DVOB_HSYNC
AC11
GAD1/DVOB_VSYNC
AD5
GAD2/DVOB_D1
AE5
GAD3/DVOB_D0
AA10
GAD4/DVOB_D3
AC9
GAD5/DVOB_D2
AB11
GAD6/DVOB_D5
AB7
GAD7/DVOB_D4
AA9
GAD8/DVOB_D6
AA6
GAD9/DVOB_D9
AA5
GAD10/DVOB_D8
W10
GAD11/DVOB_D11
AA11
GAD12/DVOB_D10
W6
GAD13/DVOBC_CLKINT
W9
GAD14/DVOB_FLDSTL
V7
GAD15/MDDC_DATA
AA2
GAD16/DVOC_VSYNC
Y4
GAD17/DVOC_HSYNC
Y2
GAD18/DVOC_BLANK#
W2
GAD19/DVOC_D0
Y5
GAD20/DVOC_D1
V2
GAD21/DVOC_D2
W3
GAD22/DVOC_D3
U3
GAD23/DVOC_D4
T2
GAD24/DVOC_D7
T4
GAD25/DVOC_D6
T5
GAD26/DVOC_D9
R2
GAD27/DVOC_D8
P2
GAD28/DVOC_D11
P5
GAD29/DVOC_D10
P4
GAD30/DVOBC_INTR#
M2
GAD31/DVOC_FLDSTL
Y7
GCBE0/DVOB_D7
W5
GCBE1/DVOB_BLANK#
AA3
GCBE2
U2
GCBE3/DVOC_D5
AC6
GADSTBF0/DVOB_CLK
AC5
GADSTBS0/DVOB_CLK#
V4
GADSTBF1/DVOC_CLK
V5
GADSTBS1/DVOC_CLK#
N6
GREQ
M7
GGNT
N3
GST0
N5
GST1
N2
GST2
R10
GRBF
R9
GWBF
U6
GFRAME/MDVI_DATA
V11
GIRDY/MI2CCLK
AB5
GTRDY/MDVI_CLK
AB4
GDEVSEL/MI2CDATA
W11
GSTOP/MDDC_CLK
AB2
GPAR/ADD_DETECT
H4
GCLKIN
R6
GSBA0#/ADD_ID0
P7
GSBA1#/ADD_ID1
R3
GSBA2#/ADD_ID2
R5
GSBA3#/ADD_ID3
U9
GSBA4#/ADD_ID4
U10
GSBA5#/ADD_ID5
U5
GSBA6#/ADD_ID6
T7
GSBA7#/ADD_ID7
U11
GSBSTBF
T11
GSBSTBS
M4
DBI_HI
M5
DBI_LO
AC2
GRCOMP/DVOBC_RCOMP
AC3
GVSWING
AD2
GVREF
T30
T33
T10
T26
T27
T28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF16
AF18
AF20
AF22
AF24
AF25
AF30
VSS
AF33
T35
VSS
VSS
AG4
U4
U18
VSS
VSS
VSS
VSS
AG8
AG14
V6
U19
U32V3V8V9V10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG16
AG18
AG20
AG22
VSS
VSS
AG24
VSS
VSS
AG26
VSS
VSS
AG28
VSS
VSS
V17
AG32
VSS
VSS
V19
AG35
V27
V33
V30W4W17
VSS
VSS
VSS
VSS
VSS
VSS
AH12
AH14
AH16
Y3
W18
W32Y6Y8Y9Y26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH18
AH20
AH22
AH24
V26
V28
VSS
VSS
VSS
VSS
VSS
VSS
AH10
AH3
AH6
VSS
VSS
AH30
VSS
VSS
AH33
Y28
Y30
Y33
Y35
Y27
AA1
AA4
AA32
AB10
AB26
AC1
AC4
AC32
AB27
AB3
AB6
AB8
Y10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK3
AJ1
AJ4
AJ9
AJ32
AJ35
AK8
AK10
AB9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK16
AK18
AK20
AK22
AK24
AK26
AK28
VSS
AL1
VSS
VSS
AK12
AK14
AC35
AB28
AB30
AB33
AD3
VSS
VSS
VSS
AL32
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM13
AM15
AM17
AM19
AM11
AM9
AM21
VSS
VSS
VSS
VSS
AD6
AM23
VSS
VSS
AD8
AM25
VSS
VSS
AD9
AM27
VSS
VSS
AD10
AM29
VSS
VSS
AM35
VSS
AN10
L1L5Y1J1J2J3K2K3K4K5J4J5L4L2L3
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
LAN CSA port
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN20
AN22
AN24
AN26
AN28
AN30
AN32
VSS
AR9
AN12
AN14
AN16
AN18
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
AR11
AR13
AR16
AG1
Y11
VCCA_AGP
VCCA_AGP
HI10
HI_STRF
HI_STRS
HI_RCOMP
HI_SWING
HI_VREF
CI10
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
DDCA_CLK
DDCA_DATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED#
REFSET
VCC_DAC
VCC_DAC
VCCA_DAC
VSSA_DAC
EXTTS#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VSS
VSS
VSS
INTEL-SpringDale
AR23
AR20
{Priority}
HL0
AF5
HI0
HL1GAD2
AG3
HI1
HL2
AK2
HI2
HL3
AG5
HI3
AK5
HL4
HI4
HL5
AL3
HI5
HL6
AL2
HI6
HL7
AL4
HI7
HL8
AJ2
HI8
AH2
HL9
HI9
HL10
AJ3
AH5
AH4
HL_COMP
AD4
HL_SWING
AE3
HL_VREF
AE2
AK7
CI0
AH7
CI1
AD11
CI2
AF7
CI3
AD7
CI4
AC10
CI5
AF8
CI6
AG7
CI7
AE9
CI8
AH9
CI9
AG6
AJ6
AJ5
CI_RCOMP
AG2
AF2
AF4
G4
F2
H3
E2
G3
H7
G6
H6
G5
F4
RED
E4
GSET
D2
G1
G2
C217
C0.01U50X
C2
C213
D3
C0.01U50X
AP8
AG9
AG10
AN35
AP34
AR1
AR25
VSS
AR27
VSS
AR29
VSS
AR32
VSS
Springdale Decoupling Capacitors
C228
0.1u
C222
X_0.1u
R261 52.3R1%
R270 52.3R1%
CI_SWING
CI_VREF
R220 137R1%
VCC_AGP
VCC_AGP
HL[0..10] 11
HI_RCOMP Calculation
R=[(1.5V-08V)/0.8V]*60ohm=52.5ohm
HL_STRF 11
HL_STRS 11
C0.01U50XC252
VCC_AGP
C0.01U50XC282
VCC_AGP
C0.01U50XC250
C0.01U50XC276
DOT_48 13
3VDDCCL 19GREQ#16
3VDDCDA 19
CRT_VSYNC 19
CRT_HSYNC 19
CRT_B 19
CRT_G 19
CRT_R 19
VCC3
VCCA_DAC
R262 226R1%
R255 147R1%
+
EC27
X_C1U10X0805
R281 113R1%
CP10 X
L9 X_100N300m
CI_SWING
CI_VREF
VCC_DAC
1.7V/60mA
800mV
350mV
H_SWING=(0.8*VCC_AGP)+-2%
7
800mV
H_SWING 11
350mV
H_VREF 11
VCCP
VCC_AGP
C156
0.1u
6
C260
0.1u
5
VCC_DDR
4
C264
0.1u
C261
0.1u
MSI
Title
Size Document Number Rev
3
Date: Sheet of
MICRO-STAR INt'L CO., LTD.
Intel Springdale - AGP & HLink & LAN Signals
2
MS-6742
8 27Friday, January 03, 2003
1
0A
VCC_AGP
R345 226R1%
R344 147R1%
R342 113R1%
8
HL_SWING
H_SWING
R343 0R
C317 0.1u
HL_VREF
H_VREF
R355 0R
C324 0.1u
H_SWING=(0.233*VCC_AGP)+-2%
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