MSI MS-6728 Schematics
5
4
3
2
1
MS-6728 ATX
*INTEL mPGA 478B Processor
D D
*INTEL Springdale GMCH / ICH5 Chipset
(DDR 333 / AGP 8X) / (integrated serial ATA)
*INTEL 82547EI Gigabit LAN
*VT6306 1394a OHCI Link Layer Controller
*PDC20376 Serial ATA Controller
*Winbond 83627THF LPC I/O
*Audio codec 6 channel support
*USB 2.0 support x8 (integrated into ICH5)
*Jump Less support
C C
B B
Title Page
Cover Sheet 1
Block Diagram
Clock Synthesizer 6
Intel Springdale 7,8,9
System Memory
AGP SLOT
82547EI Gigabit LAN
ICH5
PCI Slot / MS-1
Audio Codec / 6 Channel connector
Serial ATA Controller / Connectors
ATA 66/100 Connectors
1394 Controller
Front USB Port
Rear USB Port
W627THF LPC I/O / FWH
KB/MS/LPT/COM Port/FAN
CPU Vcore / DLED
VRM 10 HIP6556
MS-5 ACPI Controller
ATX connector / Front Panel
PCI Device & MS-1 Diagram
HISTORY
/ DDR Terminations
2
3GPIO SPEC
4,5Intel mPGA478B
10,11
12
13,14
15,16
17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MS-6728 ver:0A
LAN component
SATA component
1394 component
Standard BOM (without SATA /
1394 HC)
SMT
DIP
Total
Option A BOM (with SATA /
without 1394 HC)
SMT
DIP
Total
Option B BOM (without SATA /
with 1394 HC)
SMT
DIP
Total
Option C BOM (for ALL)
SMT
DIP
Total
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
1
Cover Sheet
MS-6728
Last Revision Date:
Thursday, November 21, 2002
Sheet
1 33
of
Rev
0A
5
4
3
2
1
Block Diagram
Intel mPGA478B
D D
FSB 533/667
A
AGP 8X /Fast Write
G
P
C C
Intel 82547EI
Gigabit LAN
CSA
Springdale
2 channel DDR 333
D
D
I
I
M
M
M
M
2
1
D
D
I
I
M
M
M
M
3
4
Hub Link
6 PCI Slots
Serial ATA
B B
Front x3
SATA Con x2
IDE Con x1
1394
Controller
SATA/IDE
Controller
PCI-33
ICH5
Dual ATA 33/66/100
LPC BUS
I
I
D
D
E
E
1
2
USB 2.0
SUPER I/OFWH
AC97
Codec
AC-LINK
A A
Rear x4 Front x4
5
4
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
3
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Block Diagram
MS-6728
1
Last Revision Date:
Sheet
Rev
0A
Thursday, November 21, 2002
33
2
of
5
4
3
2
1
GPIO FUNCTION
ICH5
D D
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
C C
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23
FunctionTypeGPIO Pin
I
PREQ#B
I
PREQ#B
I
PIRQ#E
I
PIRQ#F
I
PIRQ#G
I
PIRQ#H
I
GPI6
I
GPI7
I
CSA_PME#
I
OC4#
I
OC5#
I
SIO_SMI#
I
EXTSMI#
I
SIO_PME#
I OC#6
OC#7
I
PGNT#A
O
O
PGNT#B
O GPO18
BIOS_WP#
O
O
GPO20
O GPO21
OD
O
GPO23
GPIO 24 I/O GPIO24
GPIO 25 I/O
GPIO 27
GPIO 28
*
GPIO 32
B B
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
GPIO 49
LAN_DISABLE#
I/O
GPIO27
I/O GPIO28
I/O
GPIO32
I/O
GPIO33
I/O
GPIO34
I
GPI41
I
O PGNT#4
CPUPWRGD
OD
FWH
Function
GPI 0 PD_DET
GPI 1
*
GPI 3
*
A A
TypeGPIO Pin
I
I
SD_DET
I
Pull down through 1K ohms (unused)GPI 2
Pull down through 1K ohms (unused)
I
Pull down through 1K ohms (unused)GPI 4
I
5
Power well
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
default output
default output
default output
default output
default output
default output
default output
4
DDR DIMM Config.
DEVICE
DIMM 1 MCLK_A0/MCLK_A0#
DIMM 2
1010000B
1010001B
CLOCKADDRESS
MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
PCI RESET DEVICE
Signals
PCIRST#_ICH5 AGP,FWH,MS-5
PCIRST#1
HD_RST#
Target
Springdale,LAN, Super I/O,SATA,
1394,MS-1
PCI slot 1-6PCIRST#2
Primary, Scondary IDE
PCI
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
SERIAL ATA INT#E AD25
1394 INT#F AD26
MS-1
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
INT#B
INT#C
INT#D
INT#A
INT#A
INT#BPCI SLOT 6
INT#C
INT#D
3
IDSEL
AD16
AD17
AD18
AD19
AD20
AD21
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3
PREQ#4
PGNT#4
PREQ#5
PGNT#5
PCI6REQ#
PCI6GNT#
SATA_GNT#
SATA_REQ#
1394_GNT#
1394_REQ#
PREQ#0
PGNT#0
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
SATA_PCLK
1394_PCLK
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
GPIO Spec.
MS-6728
Last Revision Date:
Thursday, November 21, 2002
Sheet
3 33
1
Rev
0A
of
5
4
3
2
1
CPU SIGNAL BLOCK
HA#[3..31]7
D D
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
CPU1A
A35#
A34#
HDBI#0
HDBI#[0..3]7
FERR#16
STPCLK#16
HINIT#16,25
HDBSY#7
HDRDY#7
HTRDY#7
HADS#7
HLOCK#7
HBNR#7
HIT#7
HITM#7
C C
B B
HBPRI#7
HDEFER#7
CPU_TMPA25
VTIN_GND25
TRMTRIP#16
PROCHOT#7
IGNNE#16
SMI#16
A20M#16
SLP#16
BOOT28
BSEL06
BSEL16
CPU_GD16
CPURST#7
HD#[0..63]7
HDBI#1
HDBI#2
HDBI#3
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
PROCHOT#
BOOT
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
A33#
D53#
D52#
D51#
D50#
D49#
D48#
V22
U21
V25
U23
U24
U26
T23
HA#31
A32#
D47#
T22
HA#30
A31#
D46#
T25
HA#29
A30#
D45#
T26
HA#28
A29#
D44#
R24
HA#27
A28#
D43#
R25
HA#26
A27#
D42#
P24
HA#25
A26#
D41#
R21
HA#24
A25#
D40#
N25
HA#23
A24#
D39#
N26
A23#
D38#
HA#22
A22#
D37#
M26
HA#21
A21#
D36#
N23
HA#20
A20#
D35#
M24
HA#19
A19#
D34#
P21
HA#18
A18#
D33#
N22
HA#17
A17#
D32#
M23
HA#16
A16#
D31#
H25
HA#15
A15#
D30#
K23
HA#14
A14#
D29#
J24
HA#13
A13#
D28#
L22
HA#12
A12#
D27#
M21
HA#11
A11#
D26#
H24
HA#10
A10#
D25#
G26
HA#9
L21
A9#
D24#
HA#8
D26
A8#
D23#
HA#7
F26
A7#
D22#
HA#6
E25
A6#
D21#
HA#5
F24
A5#
D20#
HA#4
F23
A4#
D19#
HA#3
G23
A3#
D18#
E24
D17#
H22
AE25A5A4
DBR#
D16#
D15#
D14#
D25
J21
VCC_SENSE
VSS_SENSE
D13#
D12#
D11#
D23
C26
H21
AD26
AC26
ITP_CLK1
ITP_CLK0
D10#
D9#
G22
B25
AD2
D8#
C24
C23
VID4
VID3
VID5
AE1
AE2
AD3
VID4#
VID5#
VIDPWRGD
D7#
D6#
D5#
B24
D22
C21
VID2
AE3
VID3#
D4#
A25
VID1
AE4
VID2#
D3#
A23
VID0
AE5
VID1#
D2#
B22
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
TESTHI12
TESTHI11
TESTHI10
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D1#
D0#
B21
VCC_SENSE 28
VSS_SENSE 28
VID_GD 28,29
VID[0..5] 27
AA21
AA6
F20
F6
AB4
BPM5#
AA5
BPM4#
Y6
BPM3#
AC4
BPM2#
AB5
BPM1#
AC6
BPM0#
H3
REQ4#
J3
REQ3#
J4
REQ2#
K5
REQ1#
J1
REQ0#
AD25
A6
Y3
W4
TESTHI9
U6
TESTHI8
AB22
TESTHI7
AA20
TESTHI6
AC23
TESTHI5
AC24
TESTHI4
AC20
TESTHI3
AC21
TESTHI2
AA2
TESTHI1
AD24
TESTHI0
AF23
BCLK1#
AF22
BCLK0#
F4
RS2#
G5
RS1#
F1
RS0#
V5
AP1#
AC1
AP0#
H6
BR0#
P1
COMP1
L24
COMP0
L25
DP3#
K26
DP2#
K25
DP1#
J26
DP0#
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
PGA-S478-GD10-F02
{Priority}
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI2
TESTHI1
TESTHI0
HRS#2
HRS#1
HRS#0
HBR#0
COMP1
COMP0
C3 220p_X7R
VIDPWRGD DC Specifications
GTLREF 7
HREQ#[0..4] 7
VCCP
CPU_CLK# 6
CPU_CLK 6
HRS#[0..2] 7
HBR#0 7
HADSTB#1 7
HADSTB#0 7
HDSTBP#3 7
HDSTBP#2 7
HDSTBP#1 7
HDSTBP#0 7
HDSTBN#3 7
HDSTBN#2 7
HDSTBN#1 7
HDSTBN#0 7
NMI 16
INTR 16
Min MaxTyp
0.9
VIL
VIH
It must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
VIDGD rising time is 150ns.
{VOLTAGE}
R4 62
R5 62
R6 62
R8 62
R9 62
R13 62
R15 62
R537 62
R16 61.9RST
R17 61.9RST
CPU GTL REFERNCE VOLTAGE BLOCK
0.3
VTT
VCCP
R1
R2
200RST
GTLREF
C1
0.1u_X7R
{VOLTAGE}
0.63*Vccp
C2
104P
R3
169RST
200RST
CPU ITP BLOCK
ITP_TDI
ITP_TRST#
ITP_TMS
ITP_TDO
ITP_TCK
R7 150
R10 680
R11 39
R12 75
R14 27
VCCP
VCCP
HD#1
HD#6
HD#4
HD#3
HD#5
HD#7
HD#8
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#19
HD#18
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
HD#9
HD#2
HD#0
CPU STRAPPING RESISTORS
A A
5
BPM#4
R18 62
BPM#5
R19 62
BPM#2 CPU_GD
R21 62
BPM#3
R23 62
BPM#1
R25 62
BPM#0
R27 62
VCCP
4
ALL COMPONENTS CLOSE TO CPU
PROCHOT#
HBR#0
CPURST#
R20 62
R22 300
R24 220
R26 62
VCCP
3
Micro Star Restricted Secret
Title
Intel mPGA478B - Signals
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
MS-6728
1
Last Revision Date:
Thursday, November 21, 2002
Sheet
4 33
Rev
0A
of
5
4
3
2
1
E20E8F11
VCC
VCC
VSS
VSS
VCC
VSS
C4
105P
VCC
VSS
G21G6G24
1.2V 150mA
Near processor
F13
F15
F17
F19
VCC
VCC
VCC
VSS
VSS
VSS
G3H1H23
104P
VCC
VSS
C5
OFFPAGELEFT-R
C6
AE23
AD20
AF4
AF3
F9
VCC
VSS
VSS
H26H4J2
VCC-VID
VSS
VSS
J22
VCC-IOPLL
VCC-VIDPRG
VSS
VSS
VSS
VSS
J25J5K21
VCCA
AD22
VSSA
Y5
VSS
Y25
VSS
Y22
VSS
Y2
VSS
W6
VSS
W3
VSS
W24
VSS
W21
VSS
V4
VSS
V26
VSS
V23
VSS
V1
VSS
U5
VSS
U25
VSS
U22
VSS
U2
VSS
T6
VSS
T3
VSS
T24
VSS
T21
VSS
R4
VSS
R26
VSS
R23
VSS
R1
VSS
P5
VSS
P25
VSS
P22
VSS
P2
VSS
N6
VSS
N3
VSS
N24
VSS
N21
VSS
M5
VSS
M25
VSS
M22
VSS
M2
VSS
L4
VSS
L26
VSS
L23
VSS
L1
VSS
K6
VSS
K3
VSS
K24
VSS
PGA-S478-GD10-F02
{Priority}
C9
105P
105P
The ESL is less than 5nH, and the ESR is less than 0.3ohm.
CPU_IOPLL
C7
X_22u/1206
VSSA
It support DC current if 100mA.
L1 10uH-1206-100mA
L2 10uH-1206-100mA
DC voltage drop should
be less than 70mV.
C8
10U/1206
VCCP
VCC_VID29
VCC_VID
CPU VOLTAGE BLOCK
VID Voltage is from 1.14V to 1.32V.
D D
VCCP
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
C C
B B
AA19
AA23
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC22
AC25
VSS
VSS
VSS
VSS
AA4
VSS
AA7
VSS
AA9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB3
VSS
AB6
VSS
AB8
VSS
VSS
VSS
VSS
VSS
VSS
AC2
VSS
VSS
VSS
AC5
VSS
AC7
VSS
AC9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
VSS
AF6
AF8
B10
B12
B14
B16
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B18
B23
B20
B26B4B8
C11
C13
AF19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C15
C17C2C19
C22
C25C5C7C9D12
It is derived from 3.3V.
It should be able to source 150mA.
It drives the power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D16
D18
D20
VSS
D21D3D24D6D8E1E11
D14
C10
C12
C14
C16
C18
C20C8D11
D13
D15
D17
D19D7D9
E10
E12
E14
E16
E18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E13
E15
E17
E19
E23
E7E9F10
E4
E26
VSS
F12
F14
F16
F18F2F22
F25F5F8
CPU DECOUPLING CAPACITORS
C10
10U/1206
C17
10U/1206
C24
10U/1206
C31
10U/1206
C38
A A
5
10U/1206
C45
10U/1206
Place these caps within socket cavity Place these caps within north side of processor
C11
10U/1206
C18
10U/1206
C25
10U/1206
C32
10U/1206
C39
10U/1206
C46
10U/1206
VCCP
4
C12
10U/1206
C19
10U/1206
C26
10U/1206
C33
10U/1206
C40
10U/1206
C47
10U/1206
VCCP VCCPVCCP VCCP
C13
10U/1206
C20
10U/1206
C27
10U/1206
C34
X_10U/1206
C41
10U/1206
C48
10U/1206
C14
X_10U/1206
C21
10U/1206
C28
X_10U/1206
C35
10U/1206
C42
10U/1206
C49
10U/1206
Micro Star Restricted Secret
Title
Intel mPGA478B - Power
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
MS-6728
1
Last Revision Date:
Thursday, November 21, 2002
Sheet
5 33
Rev
0A
of
5
4
3
2
1
Clock Synthesizer
FS_A
*Trace less 0.5"
D D
C C
CP1 X
VCC3
Use 2 VIA hole on BEAD both side
FB1
C50
104P
CP2 X
FB2 X_80-0805-3A
VCC3
Use 2 VIA hole on BEAD both side
X_80-0805-3A
EC1
+
10U/16V/S
VCC3V
C64
104P
SMBDATA_ISO
SMBCLK_ISO
U1
41 39
C51
104P
C52
104P
C53
104P
C57
104P
C60
104P
C61
104P
C62
104P
C65
103P
CPU_VDD CPU0#
44
CPU_GND
35
SRC_VDD
38
SRC_GND
28
3V66_VDD
10
PCI_VDD
11
PCI_GND
17
PCI_VDD
18
PCI_GND
25
48_VDD
24
48_GND
3
REF_VDD
6
REF_GND
48
*120k Pull-up
VDDA
**120k Pull-down
47
GND
33
SDATA
32
SCLK
CPU0
CPU1
CPU1#
SRC
SRC#
3V66_0
3V66_1
3V66_2
3V66_3/VCH3V66_GND
**FS2/PCI_F0
**FS4/PCI_F1
PCI_F2
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
PCI7
**SEL24_48#/24_48
**FS3/48M_0
*FS_A/REF_0
*FS_B/REF_1
XOUT
VTT_PWRGD/PD#
RESET#
IREF
ICS952607
XIN
CPUCLK
40
CPUCLK#
MCHCLK
43
MCHCLK#
42
SATA100
37
SATA100#
36
MCH66
31
ICH66
30
LANCLK66
27
AGPCLK
2629
ICHPCLK
7
8
SIOPCLK
9
1394PCLK
12
SATAPCLK
13
PCICLK0
14
PCICLK1
15
PCICLK2
16
PCICLK3
19
PCICLK4
20
PCICLK5
21
SIO48
22
USB48
23
SEL0
1
SEL1
2
4
5
34
45
R70 475
46
Iref = 2.32mA
7 8
5 6
3 4
1 2
FP_RST# 30
18PC63
18PC66
CPU_CLK
CPU_CLK#
MCH_CLK
MCH_CLK#
SATA_100
SATA_100#
ICH_PCLK
MS1_PCLK
SIO_PCLKMS1PCLK
FWH_PCLK
1394_PCLK
SATA_PCLK
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
VCC3
2N3904S
Q1
CPU_CLK 4
CPU_CLK# 4
MCH_CLK 7
MCH_CLK# 7
SATA_100 16
SATA_100# 16
MCH_66 9
ICH_66 16
LAN_CLK66 13
AGP_CLK 12
ICH_PCLK 15
MS1_PCLK 18
SIO_PCLK 25
FWH_PCLK 25
1394_PCLK 22
SATA_PCLK 20
PCI_CLK0 17
PCI_CLK1 17
PCI_CLK2 17
PCI_CLK3 18
PCI_CLK4 18
PCI_CLK5 18
SIO_48 25
USB_48 16
ICH_14 16
AC_14 19
R65 10K
R69 220
R28 33
R29 33
R30 33
R31 33
R36 33
R37 33
R41 33
R43 33
R44 33
R46 33
R47 33
R48 33
R49 33
R50 33
R51 33
R52 33
RN1
33
R53 33
R54 33
R55 33
R58 33
R61 33
R62 33
Y1
14.318M
CG_PWRGD# VCC3V
R68 X_1K
VCCP
FS_4 FS_3 FS_2
00
0
0 0
0
ICHPCLK
R38 1K
MS1PCLK
R42 1K
USB48
R45 1K
VCC3V
R56
1K
SEL0 SEL1
R59 10K
BSEL04
BSEL0_SPG7
R63
2KST
R66
2.49KST
BSEL0
1
101
FS_B
BSEL1
R57
1K
R60 10K
R64
2KST
R67
2.49KST
CPU
133.3
166.7
BSEL1 4
BSEL1_SPG 7
CPU_CLK
R32 49.9RST
CPU_CLK#
R33 49.9RST
MCH_CLK
R34 49.9RST
MCH_CLK#
R35 49.9RST
SATA_100
R39 49.9RST
SATA_100#
R40 49.9RST
MCH66
ICH66
AGPCLK
USB48
SIO48
X_10PC54
X_10PC55
X_10PC56
X_10PC58
X_10PC59
EMC HF filter capacitors, located close to PLL
ICH_PCLK
MS1_PCLK
SIO_PCLK
FWH_PCLK
1394_PCLK
SATA_PCLK
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
CN14
7 8
5 6
3 4
1 2
X_8P4C-10P
CN15
7 8
5 6
3 4
1 2
X_8P4C-10P
CN16
7 8
5 6
3 4
1 2
X_8P4C-10P
B B
SMBCLK_ISO
SMBDATA_ISO
R71 4.7K
R72 4.7K
VCC3
SMBus Isolation
A A
PWROK_SMB29
5
4
+12V
R74
1K
C444
X_104P
R527 4.7K
R528 4.7K
SMBCLK
Q2 NDS7002AS
SMBCLK_ISO
SMBDATA
Q4 NDS7002AS
SMBDATA_ISO
3
SMBCLK 10,11,13,16,17,25
SMBCLK_ISO 29
SMBDATA 10,11,13,16,17,25
SMBDATA_ISO 29
Micro Star Restricted Secret
Title
Clock Synthesizer
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
MS-6728
1
Last Revision Date:
Thursday, November 21, 2002
Sheet
6 33
Rev
0A
of
5
VCCA_FSB
VCC_AGP
C68 104P
A31
B4
HA#[3..31]4
D D
HADSTB#04
HADSTB#14
C C
HBR#04
HBPRI#4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HBNR#4
HLOCK#4
HADS#4
HREQ#[0..4]4
HITM#4
HDEFER#4
HTRDY#4
HDBSY#4
HDRDY#4
HRS#[0..2]4
MCH_CLK6
MCH_CLK#6
B B
CPURST#4
PCIRST#113,18,20,22,25,29
PROCHOT#4
BSEL0_SPG6
BSEL1_SPG6
R77 20RST
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HIT#4
HRS#0
HRS#1
HRS#2
MS5_POK
ICH_SYNC#
HRCOMP
HSWING
GTLREF4
220p_X7R
U2A
D26
HA3#
D30
HA4#
L23
HA5#
E29
HA6#
B32
HA7#
K23
HA8#
C30
HA9#
C31
HA10#
J25
HA11#
B31
HA12#
E30
HA13#
B33
HA14#
J24
HA15#
F25
HA16#
D34
HA17#
C32
HA18#
F28
HA19#
C34
HA20#
J27
HA21#
G27
HA22#
F29
HA23#
E28
HA24#
H27
HA25#
K24
HA26#
E32
HA27#
F31
HA28#
G30
HA29#
J26
HA30#
G26
HA31#
B30
HAD_STB0#
D28
HAD_STB1#
B24
BREQ0#
B26
BPRI#
B28
BNR#
E25
HLOCK#
F27
ADS#
B29
HREQ0#
J23
HREQ1#
L22
HREQ2#
C29
HREQ3#
J21
HREQ4#
K21
HIT#
E23
HITM#
L21
DEFER#
D24
HTRDY#
E27
DBSY#
G24
DRDY#
G22
RS0#
C27
RS1#
B27
RS2#
B7
HCLKP
C7
HCLKN
AE14
PWROK
E8
CPURST#
AK4
RSTIN#
AJ8
ICH_SYNC#
L20
PROCHOT#
L13
BSEL0
L12
BSEL1
E24
HDRCOMP
C25
HDSWING
F23
C70
HDVREF
J6J7J8J9K6K7K8K9L6L7L9
VCC
VCCA_FSB
VCCA_FSB
VSS
VSS
VSS
VSS
VSS
C12
C14
C16
C18
C10
C8
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
C20
C22
C24
C26
VCC
VCC
VCC
VSS
VSS
VSS
C28D1D11
D9
4
N11N9P10
P11
R11
T16
T17
T18
T19
U16
U17
U20
V16
V18
V20
W16
N10
M10
M11M8M9
L10
L11
VCC
VCC
VCC
VCC
VSS
VSS
D13
D15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D17
VSS
D19
D21
D23
D25
D27
D29
D31
D33
T20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D35
F3F5F8
E3
F1
W19
W20
Y16
Y17
Y18
Y19
Y20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F18
F20
F14
F16E1F10
F12
VSS
VSS
VSS
VSS
VSS
G31
G35
F22
H5
F24
F26
G28
3
A3
A33
A35B2B25
B34C1C23
C35
E26
M31
AF13
AF23
AJ12
R25
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H12
H14
H16H2H20
H18
H8
H9
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H22
H24
VSS
H26
H30
H33
J10
J12
J14
J16
2
VTT
D5D6D7E6E7
F7
AN1
AP2
AR3
AR33
AR35
A7A9A11
A13
A16
A20
A23
A25
A27
A29
A32
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J18
J20
J22
J28
J32
J35
K11
K12
K14
K16
K18
VSS
K33
K20
K22
K25
K27
K29
L24
L25
A4A5A6B5B6C5C6
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M3M6M26
M27
L26
M28
L35
L31
VTT
VSS
VTT
VSS
M30
VTT
VSS
M33N1N4
VTT
VSS
VTT_FSB1
VTT_FSB2
A15
A21
VTT
VTT
VTT_FSB
VTT_FSB
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
VSS
Intel Springdale-N
{Priority}
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
C67 0.47u
C69 0.47u
HD#0
B23
HD#1
E22
HD#2
B21
HD#3
D20
HD#4
B22
HD#5
D22
HD#6
B20
HD#7
C21
HD#8
E18
HD#9
E20
HD#10
B16
HD#11
D16
HD#12
B18
HD#13
B17
HD#14
E16
HD#15
D18
HD#16
G20
HD#17
F17
HD#18
E19
HD#19
F19
HD#20
J17
HD#21
L18
HD#22
G16
HD#23
G18
HD#24
F21
HD#25
F15
HD#26
E15
HD#27
E21
HD#28
J19
HD#29
G14
HD#30
E17
HD#31
K17
HD#32
J15
HD#33
L16
HD#34
J13
HD#35
F13
HD#36
F11
HD#37
E13
HD#38
K15
HD#39
G12
HD#40
G10
HD#41
L15
HD#42
E11
HD#43
K13
HD#44
J11
HD#45
H10
HD#46
G8
HD#47
E9
HD#48
B13
HD#49
E14
HD#50
B14
HD#51
B12
HD#52
B15
HD#53
D14
HD#54
C13
HD#55
B11
HD#56
D10
HD#57
C11
HD#58
E10
HD#59
B10
HD#60
C9
HD#61
B9
HD#62
D8
HD#63
B8
HDBI#0
C17
HDBI#1
L17
HDBI#2
L14
HDBI#3
C15
B19
C19
L19
K19
G9
F9
D12
E12
HD#[0..63] 4
HDBI#[0..3] 4
HDSTBP#0 4
HDSTBN#0 4
HDSTBP#1 4
HDSTBN#1 4
HDSTBP#2 4
HDSTBN#2 4
HDSTBP#3 4
HDSTBN#3 4
1
VCCP
A A
HSWING
C72
X_0.01u_X7R
C73
0.01u_X7R
{VOLTAGE}
1/4*Vccp
5
R81
301RST
R82
100RST
I=30mA ICH_SYNC# MS5_POK ICH_PWROK
10
C71
0.1u_X7R
L3 0.82uH-30mA
EC2
+
10U/16V/S
FSBVCCA_FSB
R78 0
VCC_AGP
0 0
1
1 1 1
MS5_POK29
0
ICH_SYNC#
MS5_POK
0
0
0
VCC3
R84 X_220
4
3
R79
Q5 X_2N3904S
Q6 X_2N3904S
R85 0
X_220
R80
X_1K
ICH_PWROK 16
Micro Star Restricted Secret
Title
Intel Springdale - CPU
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
MS-6728
1
Last Revision Date:
Thursday, November 21, 2002
Sheet
7 33
Rev
0A
of
VCC3
5
4
3
2
1
MDQ_A[0..63]10 MCKE_A[0..3] 10
MCKE_A1
MDQ_A4
MDQ_A9
MDQ_A3
MDQ_A6
MDQ_A2
AM12
AN13
SDQ_A1
SDQ_A2
SDQ_A3
VCC_DDR
VCC_DDR
VCC_DDR
AA35
R35
MDQ_A5
AM10
AL10
SDQ_A4
SDQ_A5
VCC_DDR
VCC_DDR
AR15
AR21
MDQ_A7
AL12
AP13
SDQ_A6
SDQ_A7
VCC_DDR
VCC_DDR
AL7
AL6
MDQ_A8
AP14
AM14
SDQ_A8
SDQ_A9
VCC_DDR
VCC_DDR
AM1
AM2
MDQ_A12
MDQ_A11
MDQ_A10
AL18
AP19
AL14
SDQ_A10
SDQ_A11
VCC_DDR
VCC_DDR
AN8
AP3
AP4
MDQ_A13
MDQ_A14
AN15
AP18
SDQ_A12
SDQ_A13
SDQ_A14
VCC_DDR
VCC_DDR
VCC_DDR
AP5
AP6
MDQ_A15
MDQ_A17
MDQ_A16
AM18
AP22
AM22
SDQ_A15
SDQ_A16
VCC_DDR
VCC_DDR
AR4
AR5
AP7
MDQ_A18
MDQ_A20
MDQ_A19
AL24
AN27
SDQ_A17
SDQ_A18
SDQ_A19
VCC_DDR
VCC_DDR
VCC_DDR
AR7
AR31
MDQ_A22
MDQ_A21
AP21
AL22
AP25
SDQ_A20
SDQ_A21
SDQ_B0
AJ10
AE15
MDQ_A24
MDQ_A23
AP27
AP28
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_B1
SDQ_B2
SDQ_B3
AL11
AE16
MDQ_A25
MDQ_A27
MDQ_A26
AP29
AP33
AM33
SDQ_A25
SDQ_A26
SDQ_B4
SDQ_B5
AL8
AF12
AK11
MDQ_A28
MDQ_A29
AM28
AN29
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_B6
SDQ_B7
SDQ_B8
AG12
AE17
MDQ_A31
MDQ_A30
MDQ_A32
AM31
AN34
AH32
SDQ_A30
SDQ_A31
SDQ_B9
SDQ_B10
AL13
AK17
AL17
MDQ_A33
MDQ_A34
AG34
AF32
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_B11
SDQ_B12
SDQ_B13
AK13
AJ14
MDQ_A35
MDQ_A36
MDQ_A37
AD32
AH31
AG33
SDQ_A35
SDQ_A36
SDQ_B14
SDQ_B15
AJ16
AJ18
AE19
MDQ_A38
MDQ_A39
AE34
AD34
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_B16
SDQ_B17
SDQ_B18
AE20
AG23
MDQ_A40
MDQ_A42
MDQ_A41
AC34
AB31
V32
SDQ_A40
SDQ_A41
SDQ_B19
SDQ_B20
AK23
AL19
AK21
MDQ_A44
MDQ_A43
V31
AD31
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_B21
SDQ_B22
SDQ_B23
AJ24
AE22
MDQ_A45
MDQ_A46
MDQ_A47
AB32
U34
U33
SDQ_A45
SDQ_A46
SDQ_B24
SDQ_B25
AK25
AH26
AG27
MDQ_A48
MDQ_A49
T34
T32
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_B26
SDQ_B27
SDQ_B28
AF27
AJ26
MDQ_A51
MDQ_A50
MDQ_A52
K34
K32
T31
SDQ_A50
SDQ_A51
SDQ_B29
SDQ_B30
AJ27
AD25
AF28
MDQ_A54
MDQ_A53
P34
L34
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_B31
SDQ_B32
SDQ_B33
AE30
AC27
MDQ_A56
MDQ_A57
MDQ_A55
L33
J33
H34
SDQ_A55
SDQ_A56
SDQ_B34
SDQ_B35
AC30
Y29
AE31
MDQ_A58
MDQ_A59
E33
F33
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_B36
SDQ_B37
SDQ_B38
AB29
AA26
MDQ_A60
MDQ_A1
MDQ_A0
AP10
U2B
D D
MCS_A#010
MCS_A#110
MCS_A#210
MCS_A#310
MRAS_A#10
MCAS_A#10
MWE_A#10
MA_A[0..12]10
MAB_A[1..5]10
C C
MBA_A010
MBA_A110
MDQM_A[0..7]10
MDQS_A[0..7]10
MCLK_A010
MCLK_A#010
MCLK_A110
MCLK_A#110
MCLK_A210
B B
MCLK_A#210
MCLK_A310
MCLK_A#310
MCLK_A410
MCLK_A#410
MCLK_A510
MCLK_A#510
103PC77
103PC80
103PC81
104PC83
C84 105P
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AC33
SRAS_A#
Y34
SCAS_A#
AB34
SWE_A#
MA_A0
AJ34
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21
AL34
AM34
AP32
AP31
AM26
AE33
AH34
AP12
AP16
AM24
AP30
AF31
W33
M34
AN11
AP15
AP23
AM30
AF34
M32
AK32
AK31
AP17
AN17
AK33
AK34
AM16
AL16
AK9
AN9
H32
V34
H31
N33
N34
P31
P32
AL9
E34
SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12
SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5
SBA_A0
SBA_A1
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SMDCLK_A0
SMDCLK_A0#
SMDCLK_A1
SMDCLK_A1#
SMDCLK_A2
SMDCLK_A2#
SMDCLK_A3
SMDCLK_A3#
SMDCLK_A4
SMDCLK_A4#
SMDCLK_A5
SMDCLK_A5#
SMXRCOMP
SMXCOMPVOH
SMXCOMPVOL
SMVREF_A
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11 MA_B12
MA_A12
MAB_A1
MAB_A2
MAB_A3
MAB_A4
MAB_A5
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
XRCOMP
XCOMPH
XCOMPL
XVREF
AP11
SDQ_A0
E35
MDQ_A61
K31
J34
SDQ_A60
SDQ_A61
SDQ_B39
SDQ_B40
AA27
AA30
MDQ_A62
MDQ_A63
G34
F34
SDQ_A62
SDQ_A63
SDQ_B41
SDQ_B42
W30
U27
T25
MCKE_A0
AL20
AN19
SCKE_A0
SCKE_A1
SDQ_B43
SDQ_B44
SDQ_B45
AA31
V29
MCKE_A2
AM20
U25
C86 474P
C87 224P
C90 224P
5
C91 104P
C92 X_105P
R88 42.2RST
R91 42.2RST
R95 42.2RST
R98 42.2RST
A A
VCC_DDR_C2
VCC_DDR_C3
values still need verification
VCC_DDR VCC_DDR
AA35AA33
VCC_DDR
MDQ_B[0..63]11
C93 X_105P
R89 30.1KST
R92 10KST
C95 105P
R96 10KST
R99 30.1KST
MDQ_B0
MDQ_B10
R33
YCOMPHXCOMPHYRCOMP VCC_DDR_C3
VCC_DDR
4
R34
MDQ_B11
MDQ_B12
MDQ_B14
MDQ_B13
MDQ_B15
R90 30.1KST
R93 10KST
R97 10KST
R100 30.1KST
MDQ_B17
MDQ_B16
MDQ_B18
MDQ_B19
MDQ_B21
MDQ_B20
MDQ_B22
MDQ_B23
MDQ_B24
VCC_DDR_C2YCOMPLXCOMPLXRCOMP
R35
MDQ_B27
MDQ_B26
MDQ_B25
MDQ_B29
MDQ_B28
MDQ_B30
MDQ_B32
MDQ_B31
MDQ_B33
MDQ_B34
MDQ_B35
3
MDQ_B36
MDQ_B38
MDQ_B39
MDQ_B37
VCCA_DDR
MDQ_B42
MDQ_B41
MDQ_B40
C94
104P
MDQ_B43
MDQ_B44
MDQ_B45
+
MDQ_B46
MDQ_B9
MDQ_B8
MDQ_B4
MDQ_B5
MDQ_B3
MDQ_B6
MDQ_B7
MDQ_B1
MDQ_B2
MCKE_A3
AP20
SCKE_A2
SCKE_A3
SDQ_B46
SDQ_B47
SDQ_B48
R27
P29
MDQ_B48
MDQ_B47
EC4
10U/16V/S
AC26
AB25
AC25
VCCA_DDR
VCCA_DDR
VCCA_DDR
SDQ_B49
SDQ_B50
SDQ_B51
R30
K28
L30
MDQ_B49
MDQ_B50
MDQ_B51
L5
1uH-1206-1A
{Prority}
VCCA_DDR
AN4
AL35
VCCA_DDR
SDQ_B52
SDQ_B53
R31
R26
P25
MDQ_B53
MDQ_B52
MDQ_B54
AM3
AN5
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B54
SDQ_B55
SDQ_B56
L32
K30
MDQ_B56
MDQ_B55
104PC75
AM5
AM6
AM7
VCC_DDR
VCC_DDR
SDQ_B57
SDQ_B58
H29
F32
G33
MDQ_B59
MDQ_B58
MDQ_B57
VCC_DDR
AM8
AN2
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B59
SDQ_B60
SDQ_B61
N25
M25
MDQ_B60
MDQ_B61
VCC_AGP
AN6
AN7
VCC_DDR
VCC_DDR
SDQ_B62
SDQ_B63
J29
G32
MDQ_B63
MDQ_B62
P3P6P8
N35
N32
VSS
VSS
SCKE_B0
SCKE_B1
AK19
AF19
AG19
MCKE_B0
MCKE_B1
MCKE_B2
SCS_B0#
VSS
VSS
VSS
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12
SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5
SBA_B0
SBA_B1
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMYRCOMP
SMYCOMPVOH
SMYCOMPVOL
SMVREF_B
SCKE_B2
SCKE_B3
Intel Springdale-N
AE18
{Priority}
MCKE_B3
2
Its current is 5.1A.
U26
T29
V25
W25
W26
W31
W27
AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20
AE27
AD26
AL29
AL27
AE23
Y25
AA25
AG11
AG15
AE21
AJ28
AC31
U31
M29
J31
AF15
AG13
AG21
AH27
AD29
U30
L27
J30
AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30
AA33
R34
R33
AP9
MCKE_B[0..3] 11
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MAB_B1
MAB_B2
MAB_B3
MAB_B4
MAB_B5
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
YRCOMP
YCOMPH
YCOMPL
YVREF
MCS_B#0 11
MCS_B#1 11
MCS_B#2 11
MCS_B#3 11
MRAS_B# 11
MCAS_B# 11
MWE_B# 11
MA_B[0..12] 11
MAB_B[1..5] 11
MBA_B0 11
MBA_B1 11
MDQM_B[0..7] 11
MDQS_B[0..7] 11
MCLK_B0 11
MCLK_B#0 11
MCLK_B1 11
MCLK_B#1 11
MCLK_B2 11
MCLK_B#2 11
MCLK_B3 11
MCLK_B#3 11
MCLK_B4 11
MCLK_B#4 11
MCLK_B5 11
MCLK_B#5 11
103PC76
103PC78
103PC79
104PC82
C85 X_105P
R86 150RST
R87 150RST
C88 105P
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
VCC_DDR
Micro Star Restricted Secret
Intel Springdale - Memory
MS-6728
Last Revision Date:
Thursday, November 21, 2002
Sheet
1
8 33
of
Rev
0A
5
P26
P27
P28
P30
P33R1R4
VSS
VSS
AE13
VSS
VSS
AE25
R32T1T3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE26
AE32
AE35
AF3
AF6
VSS
AD30
AD33
VSS
VSS
VSS
AE1
AE4
AD28
800mV
HL_SWING 16
350mV
HL_VREF 16
P9
VSS
VSS
VSS
VSS
AE10
AE11
AE12
GAD[0..31]12
D D
VCC_AGP
VCC_AGP
GC_BE#[0..3]12
ST[0..2]12
SBA[0..7]12
R103 43.2RST
AD_STB012
AD_STB#012
AD_STB112
AD_STB#112
GREQ#12
GGNT#12
GFRAME#12
GIRDY#12
GTRDY#12
GDEVSEL#12
GSTOP#12
MCH_666
SB_STB12
SB_STB#12
DBI_LO12
103PC103
GSWING12
103PC104
AGP_REF12
R107 226RST
R109 147RST
R111 113RST
C C
B B
A A
GAD0
GAD1
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3
ST0
ST1
ST2
RBF#
RBF#12
WBF#
WBF#12
GPAR12
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
PIPE#12
GRCOMP
GSWING
C105 104P
C122 104P
5
U2C
AE6
GAD0/DVOB_HSYNC
AC11
GAD1/DVOB_VSYNC
AD5
GAD2/DVOB_D1
AE5
GAD3/DVOB_D0
AA10
GAD4/DVOB_D3
AC9
GAD5/DVOB_D2
AB11
GAD6/DVOB_D5
AB7
GAD7/DVOB_D4
AA9
GAD8/DVOB_D6
AA6
GAD9/DVOB_D9
AA5
GAD10/DVOB_D8
W10
GAD11/DVOB_D11
AA11
GAD12/DVOB_D10
W6
GAD13/DVOBC_CLKINT
W9
GAD14/DVOB_FLDSTL
V7
GAD15/MDDC_DATA
AA2
GAD16/DVOC_VSYNC
Y4
GAD17/DVOC_HSYNC
Y2
GAD18/DVOC_BLANK#
W2
GAD19/DVOC_D0
Y5
GAD20/DVOC_D1
V2
GAD21/DVOC_D2
W3
GAD22/DVOC_D3
U3
GAD23/DVOC_D4
T2
GAD24/DVOC_D7
T4
GAD25/DVOC_D6
T5
GAD26/DVOC_D9
R2
GAD27/DVOC_D8
P2
GAD28/DVOC_D11
P5
GAD29/DVOC_D10
P4
GAD30/DVOBC_INTR#
M2
GAD31/DVOC_FLDSTL
Y7
GCBE0/DVOB_D7
W5
GCBE1/DVOB_BLANK#
AA3
GCBE2
U2
GCBE3/DVOC_D5
AC6
GADSTBF0/DVOB_CLK
AC5
GADSTBS0/DVOB_CLK#
V4
GADSTBF1/DVOC_CLK
V5
GADSTBS1/DVOC_CLK#
N6
GREQ
M7
GGNT
N3
GST0
N5
GST1
N2
GST2
R10
GRBF
R9
GWBF
U6
GFRAME/MDVI_DATA
V11
GIRDY/MI2CCLK
AB5
GTRDY/MDVI_CLK
AB4
GDEVSEL/MI2CDATA
W11
GSTOP/MDDC_CLK
AB2
GPAR/ADD_DETECT
H4
GCLKIN
R6
GSBA0#/ADD_ID0
P7
GSBA1#/ADD_ID1
R3
GSBA2#/ADD_ID2
R5
GSBA3#/ADD_ID3
U9
GSBA4#/ADD_ID4
U10
GSBA5#/ADD_ID5
U5
GSBA6#/ADD_ID6
T7
GSBA7#/ADD_ID7
U11
GSBSTBF
T11
GSBSTBS
M4
DBI_HI
M5
DBI_LO
AC2
GRCOMP/DVOBC_RCOMP
AC3
GVSWING
AD2
GVREF
H_SWING=(0.8*VCC_AGP)+-2%
HL_SWING
HL_VREF
H_SWING=(0.233*VCC_AGP)+-2%
4
V6
U4
U18
U19
T6T8T9
T10
T26
T27
T28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF16
AF18
AF20
AF22
AF24
AF14
AF25
4
AF11
AF9
U32V3V8V9V10
T30
T33
T35
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF33
AG4
AG8
AG14
AG16
AG18
AG20
AG22
VCCP
Close CPU side of GMCH Close AG1 and Y1 of GMCH Close E35, R35, AA35, AL35, AR31, AR21 and AR15 of GMCH
C106
104P
C114
104P
V27
V33
V30W4W17
VSS
VSS
VSS
VSS
VSS
VSS
AH12
AH14
C107
105P/0805
C115
105P/0805
W18
W32Y6Y8Y9Y26
VSS
VSS
VSS
VSS
VSS
VSS
AH16
AH18
AH20
AH22
Y3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ1
AH24
AH30
AH33
V17
V19
V26
V28
VSS
VSS
AG24
VSS
VSS
AG26
VSS
VSS
AG28
VSS
VSS
VSS
VSS
AG32
VCCP
AG35
VSS
VSS
VSS
VSS
VSS
VSS
AH10
AH3
AH6
3
Y28
Y30
Y33
Y35
Y27
AA1
AA4
AA32
AB10
AB26
AB27
AB28
AB3
Y10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK3
AJ4
AJ9
AJ32
AJ35
AB6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK16
AK18
AK20
AK8
AK10
AK12
AK14
AB30
AB8
AB9
VSS
VSS
VSS
VSS
AK22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM9
AK24
AK26
AK28
AL1
AL32
VSS
VSS
Springdale Decoupling Capacitors
All caps trace length is less than 100mils.
C108
104P
C116
X_104P
3
C109
X_104P
C117
104P
VCC_DDRVCC_DDR VCC_DDR VCC_DDRVCC_AGP
C97 104P
AC1
AC4
AB33
VSS
VSS
VSS
VSS
AM13
AM15
AM11
2
C96 104P
VCC_AGP
AC32
AC35
AD3
VSS
VSS
VSS
VSS
VSS
VSS
AM17
AM19
AM21
C110
104P
C118
104P
VSS
VSS
AD6
AM23
AD8
AD9
AD10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM25
AM27
AM29
AM35
AN10
L1L5Y1J1J2J3K2K3K4K5J4J5L4L2L3
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN20
AN22
AN24
AN26
AN28
AN30
AN32
C112
104P
C120
104P
VSS
AR9
2
AN12
AN14
AN16
C111
X_104P
C119
104P
AN18
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
AR11
AR13
AG1
Y11
VCCA_AGP
VCCA_AGP
HI_STRF
HI_STRS
HI_RCOMP
HI_SWING
HI_VREF
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
DDCA_CLK
DDCA_DATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED#
REFSET
VCC_DAC
VCC_DAC
VCCA_DPLL
VCCA_DAC
VSSA_DAC
EXTTS#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VSS
VSS
VSS
AR23
AR16
AR20
Intel Springdale-N
{Priority}
VTT
HI10
CI10
RED
VSS
VSS
VSS
VSS
HL0
AF5
HI0
HL1GAD2
AG3
HI1
HL2
AK2
HI2
HL3
AG5
HI3
HL4
AK5
HI4
HL5
AL3
HI5
HL6
AL2
HI6
HL7
AL4
HI7
HL8
AJ2
HI8
HL9
AH2
HI9
HL10
AJ3
AH5
AH4
HL_COMP
AD4
HL_SWING
AE3
HL_VREF
AE2
CI0
AK7
CI0
CI1
AH7
CI1
CI2
AD11
CI2
CI3
AF7
CI3
CI4
AD7
CI4
CI5
AC10
CI5
CI6
AF8
CI6
CI7
AG7
CI7
CI8
AE9
CI8
CI9
AH9
CI9
CI10
AG6
AJ6
AJ5
CI_RCOMP
AG2
AF2
AF4
G4
F2
H3
E2
G3
H7
G6
H6
G5
F4
E4
D2
G1
G2
R83 0
B3
R517 0
C2
D3
AP8
AG9
AG10
AN35
AP34
AR1
AR25
AR27
AR29
AR32
C113
104P
C121
104P
C98
104P
R101 52.3RST
R102 52.3RST
CI_SWING
CI_VREF
VCC_AGP
VCC_AGP
HL[0..10] 16
HI_RCOMP Calculation
R=[(1.5V-08V)/0.8V]*60ohm=52.5ohm
HL_STRF 16
HL_STRS 16
103PC99
103PC100
CI[0..10] 13
CI_STRF 13
CI_STRS 13
VCC_AGP
103PC101
103PC102
R104 226
R105 147
R106 113
Micro Star Restricted Secret
Title
Intel Springdale - AGP & LAN
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
VCC_AGP
1
MS-6728
1
CI_SWING
CI_VREF
Last Revision Date:
Thursday, November 21, 2002
Sheet
9 33
800mV
350mV
Rev
0A
of
5
4
3
2
1
DDR DIMM1 DDR DIMM2
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
157
158
71
163
154
65
63
5
14
25
36
56
67
78
86
47
97
107
119
129
149
159
169
177
140
44
45
49
51
134
135
142
144
21
111
92
91
181
182
183
16
17
137
138
76
75
82
184
7
38
46
70
85
108
120
148
168
81
89
93
100
116
124
132
139
145
152
160
176
DIMM1
SIGNALS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/NC
A13/NC
BA0
BA1
NC/BA2
CS0#
CS1#
NC/CS2#
NC/CS3#
RAS#
CAS#
WE#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQM0/DQS9
DQM1/DQS10
DQM2/DQS11
DQM3/DQS12
DQM4/DQS13
DQM5/DQS14
DQM6/DQS15
DQM7/DQS16
DQM8/DQS17
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
CKE0
CKE1
SCL
SDA
SA0
SA1
SA2
CK0/NC
CK0#/NC
CK1/CK0
CK1#/CK0#
CK2/NC
CK2#/NC
ID_VDD
SPD_VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DIMM-D184-BK
POWER
FETEN/NC
NC/RESET#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
MA_A[0..12]8
D D
MBA_A08
MBA_A18
MCS_A#08
MCS_A#18
MRAS_A#8
MCAS_A#8
MWE_A#8
MDQS_A[0..7]8
C C
B B
A A
MDQM_A[0..7]8
MCKE_A08
MCKE_A18
SMBCLK_ISO6
SMBDATA_ISO6
MCLK_A18
MCLK_A#18
MCLK_A08
MCLK_A#08
MCLK_A28
MCLK_A#28
MA_A0
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
MBA_A0
MBA_A1
MRAS_A#
MCAS_A#
MWE_A#
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
SMBCLK_ISO
SMBDATA_ISO SMBDATA_ISO
VCC_DDR
VCC_DDR
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MDQ_A0
2
DQ0
MDQ_A1
4
DQ1
MDQ_A2
6
DQ2
MDQ_A3
8
DQ3
MDQ_A4
94
DQ4
MDQ_A5
95
DQ5
MDQ_A6
98
DQ6
MDQ_A7
99
DQ7
MDQ_A8
12
DQ8
MDQ_A9
13
DQ9
MDQ_A10
19
MDQ_A11
20
MDQ_A12
105
MDQ_A13
106
MDQ_A14
109
MDQ_A15
110
MDQ_A16
23
MDQ_A17
24
MDQ_A18
28
MDQ_A19
31
MDQ_A20
114
MDQ_A21
117
MDQ_A22
121
MDQ_A23
123
MDQ_A24
33
MDQ_A25
35
MDQ_A26
39
MDQ_A27
40
MDQ_A28
126
MDQ_A29
127
MDQ_A30
131
MDQ_A31
133
MDQ_A32
53
MDQ_A33
55
MDQ_A34
57
MDQ_A35
60
MDQ_A36
146
MDQ_A37
147
MDQ_A38
150
MDQ_A39
151
MDQ_A40
61
MDQ_A41
64
MDQ_A42
68
MDQ_A43
69
MDQ_A44
153
MDQ_A45
155
MDQ_A46
161
MDQ_A47
162
MDQ_A48
72
MDQ_A49
73
MDQ_A50
79
MDQ_A51
80
MDQ_A52
165
MDQ_A53
166
MDQ_A54
170
MDQ_A55
171
MDQ_A56
83
MDQ_A57
84
MDQ_A58
87
MDQ_A59
88
MDQ_A60
174
MDQ_A61
175
MDQ_A62
178
MDQ_A63
179
9
NC
101
NC
102
NC
173
NC
1
90
WP
C123
103
104P
10
15
22
30
54
62
77
96
104
112
128
136
143
156
164
172
180
3
11
18
26
34
42
50
58
66
74
VCC_DDR
VCC_DDR
MDQ_A[0..63] 8
R127
75RST
R128
75RST
VCC_DDR
CB29
X_104P
CB33
104P
CB36
X_104P
CB39
104P
CB40
104P
CB41
X_104P
CB42
104P
CB43
104P
CB44
104P
MAB_A[1..5]8
MCS_A#28
MCS_A#38
MCKE_A28
MCKE_A38
MCLK_A48
MCLK_A#48
MCLK_A38
MCLK_A#38
MCLK_A58
MCLK_A#58
SMBCLK_ISO
VCC_DDR
VCC_DDR
VCC_DDR
MA_A0
MAB_A1
MAB_A2
MAB_A3
MAB_A4
MAB_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
MBA_A0
MBA_A1
MRAS_A#
MCAS_A#
MWE_A#
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
ADDR.=1010000B ADDR.=1010001B
5
4
DIMM2
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
157
158
71
163
154
65
63
5
14
25
36
56
67
78
86
47
97
107
119
129
149
159
169
177
140
44
45
49
51
134
135
142
144
21
111
92
91
181
182
183
16
17
137
138
76
75
82
184
7
38
46
70
85
108
120
148
168
81
89
93
100
116
124
132
139
145
152
160
176
DIMM-D184-BK
3
SIGNALS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/NC
A13/NC
BA0
BA1
NC/BA2
CS0#
CS1#
NC/CS2#
NC/CS3#
RAS#
CAS#
WE#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQM0/DQS9
DQM1/DQS10
DQM2/DQS11
DQM3/DQS12
DQM4/DQS13
DQM5/DQS14
DQM6/DQS15
DQM7/DQS16
DQM8/DQS17
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
CKE0
CKE1
SCL
SDA
SA0
SA1
SA2
CK0/NC
CK0#/NC
CK1/CK0
CK1#/CK0#
CK2/NC
CK2#/NC
ID_VDD
SPD_VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
POWER
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
FETEN/NC
NC/RESET#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MDQ_A0
2
MDQ_A1
4
MDQ_A2
6
MDQ_A3
8
MDQ_A4
94
MDQ_A5
95
MDQ_A6
98
MDQ_A7
99
MDQ_A8
12
MDQ_A9
13
MDQ_A10
19
MDQ_A11
20
MDQ_A12
105
MDQ_A13
106
MDQ_A14
109
MDQ_A15
110
MDQ_A16
23
MDQ_A17
24
MDQ_A18
28
MDQ_A19
31
MDQ_A20
114
MDQ_A21
117
MDQ_A22
121
MDQ_A23
123
MDQ_A24
33
MDQ_A25
35
MDQ_A26
39
MDQ_A27
40
MDQ_A28
126
MDQ_A29
127
MDQ_A30
131
MDQ_A31
133
MDQ_A32
53
MDQ_A33
55
MDQ_A34
57
MDQ_A35
60
MDQ_A36
146
MDQ_A37
147
MDQ_A38
150
MDQ_A39
151
MDQ_A40
61
MDQ_A41
64
MDQ_A42
68
MDQ_A43
69
MDQ_A44
153
MDQ_A45
155
MDQ_A46
161
MDQ_A47
162
MDQ_A48
72
MDQ_A49
73
MDQ_A50
79
MDQ_A51
80
MDQ_A52
165
MDQ_A53
166
MDQ_A54
170
MDQ_A55
171
MDQ_A56
83
MDQ_A57
84
MDQ_A58
87
MDQ_A59
88
MDQ_A60
174
MDQ_A61
175
MDQ_A62
178
MDQ_A63
179
9
NC
101
NC
102
NC
173
NC
DDR_VREF1DDR_VREF1
1
90
WP
C124
103
104P
10
15
22
30
54
62
77
96
104
112
128
136
143
156
164
172
180
3
11
18
26
34
42
50
58
66
74
VCC_DDR
VTT_DDR VTT_DDR VCC_DDR
2
DDR Terminational Resisitors
VTT_DDR
VTT_DDR
MDQ_A9
MDQ_A8
MDQ_A3
MDQ_A7
MDQ_A6
MDQ_A2
MDQM_A0
MDQS_A0
MDQM_A1
MDQ_A13
MDQS_A1
MDQ_A12
MDQS_A2
MDQ_A21
MDQ_A17
MDQ_A16
MDQ_A22
MDQ_A18
MDQM_A2
MDQM_A3
MDQS_A3
MDQ_A29
MDQ_A25
MDQ_A31
MDQ_A27
MDQ_A26
MDQ_A30
MDQ_A38
MDQM_A4
MDQ_A34
MDQS_A4
MDQ_A40
MDQ_A44
MDQ_A35
MDQ_A39
MDQ_A28
MDQ_A24
MDQ_A19
MDQ_A23
MDQ_A1
MDQ_A5
MDQ_A4
MDQ_A0
MDQ_A47
MDQ_A46
MDQ_A43
MDQ_A42
MDQ_A61
MDQ_A60
MDQ_A51
MDQ_A50
MDQ_A58
MDQ_A59
MDQ_A63
MDQ_A62
MDQ_A55
MDQ_A54
MDQS_A6
MDQM_A6
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
MDQS_A7
MDQM_A7
MDQ_A57
MDQ_A56
MDQ_A37
MDQ_A33
MDQ_A36
MDQ_A32
MDQ_A53
MDQ_A52
MDQ_A49
MDQ_A48
MDQ_A11
MDQ_A10
MDQ_A15
MDQ_A14
MDQS_A5
MDQM_A5
MDQ_A41
MDQ_A45
MDQ_A20
MA_A1
MAB_A1
MA_A2
MAB_A2
MA_A5
MAB_A5
MA_A8
MA_A7
MAB_A3
MA_A3
MAB_A4
MA_A4
MBA_A1
MA_A10
MA_A0
MCS_A#3
MCS_A#1
MCS_A#2
MCAS_A#
MCKE_A0
MCKE_A2
MCKE_A3
MCKE_A1
MA_A6
MA_A9
MA_A11
MA_A12
MBA_A0
MRAS_A#
MWE_A#
MCS_A#0
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R112 56
R113 56
R114 56
R115 56
R117 56
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R119 47
R120 47
R121 47
R122 47
R123 47
R124 47
R125 47
R126 47
RN2
56
RN4
56
RN6
56
RN8
56
RN13
47
RN15
47
RN17
47
RN19
47
RN21
47
RN23
47
DECOUPLING CAPACITORS
CB1
104P
CB3
X_104P
CB5
X_104P
CB8
104P
CB11
104P
CB14
X_104P
CB17
104P
CB20
X_104P
CB23
104P
CB26
104P
CB30
104P
CB34
X_104P
CB37
104P
Place these decoupling capacitors close to VTT_DDR termination resistors.
One decoupling capacitor for each R-pack.
CB2
104P
CB4
X_104P
CB6
104P
CB9
104P
CB12
104P
CB15
X_104P
CB18
104P
CB21
X_104P
CB24
104P
CB27
104P
CB31
104P
CB35
104P
CB38
104P
Micro Star Restricted Secret
Title
DDR DIMM 1,2
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
CB7
104P
CB10
104P
CB13
104P
CB16
104P
CB19
104P
CB22
104P
CB25
104P
CB28
X_104P
CB32
104P
MS-6728
VTT_DDR
RN3
56
RN5
56
RN7
56
RN9
56
RN10
56
RN11
56
RN12
56
RN14
56
RN16
56
RN18
56
RN20
56
RN22
56
RN24
56
RN25
56
RN26
56
Last Revision Date:
Tuesday, November 26, 2002
Sheet
1
10 33
of
Rev
0A
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