MOTOROLA SN74LS253ML2, SN74LS253N, SN74LS253D, SN74LS253DR2, SN74LS253M Datasheet

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS253/D

SN74LS253

Dual 4-Input Multiplexer
with 3-State Outputs

The LSTTL /MSI SN74LS253 is a Dual 4-Input Multiplexer with
3-state outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually switched to a
high impedance state with a HIGH on the respective Output Enable
(E

0

) inputs, allowing the outputs to interface directly with bus oriented
systems. It is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.

• Schottky Process for High Speed

• Multifunction Capability

• Non-Inverting 3-State Outputs

• Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –2.6 mA

I

OL

Output Current – Low 24 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS253N 16 Pin DIP 2000 Units/Box
SN74LS253D 16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC
N SUFFIX
CASE 648

16

1

16

1

SN74LS253

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2

CONNECTION DIAGRAM DIP (TOP VIEW)

Common Select Inputs

Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output

Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output

S

0

, S

1

Multiplexer A

E

0a

I0a – I

3a

Z

a

Multiplexer B

E

0b

I0b – I

3b

Z

b

0.5 U.L.

0.5 U.L.

0.5 U.L.
65 U.L.

0.5 U.L.

0.5 U.L.
65 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.
15 U.L.

0.25 U.L.

0.25 U.L.
15 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES

LOGIC SYMBOL

VCC = PIN 16
GND = PIN 8

165431011121315

14

2

S

0

S

1

E0aI0aI1aI2aI3aI0bI1bI2bI3bE

0b

Z

a

Z

b

79

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

14 13 12 11 10 9

123456

7

16 15

8

V

CC

E

0a

E0bS0I3bI

2b

I

0b

I

1b

Z

b

S1I

3aI2aI1aI0aZa

GND

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3

LOGIC DIAGRAM

E

0b

I

3b

I

2b

I

1b

I

0b

S

0

S

1

I

3a

I

2a

I

1a

I

0a

E

0a

Z

b

Z

a

14 126

7

3 4 5

9

1113 101215

VCC = PIN 16
GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
selected by common select inputs (S

0

, S1). The 4-input
multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.

The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:

If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.

Za = E0a ⋅(I0a ⋅S1 ⋅S0 + I

1a

⋅S1 ⋅S0 ⋅I2a ⋅S1 ⋅S0 + I3a ⋅ S1 ⋅S0)

Z

b

= E0b⋅ (I0b S1 S0 + I1b⋅ S1⋅ S0 I2b⋅ S1⋅ S0 + I3b⋅ S1⋅ S0)

TRUTH TABLE

SELECT

INPUTS

DATA INPUTS

OUTPUT
ENABLE

OUTPUT

S

0

S

1

I

0

I

1

I

2

I

3

E

0

Z

X X X X X X H (Z)
L LLXX X L L
L LHXX X L H
H LXLX X L L
H LXHX X L H
L HXXL X L L
L HXXH X L H
H HXXX L L L
H H X X X H L H

H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S

0

and S1 are common to both sections.

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4

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

V

IL

Input LOW Voltage

0.8
V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

V

OH

Output HIGH Voltage 2.4 3.1 V VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

p

0.25 0.4 V IOL = 12 mA

VCC = VCC MIN,

VOLOutput LOW Voltage

0.35 0.5 V IOL = 24 mA

V

IN

=

V

IL

or

V

IH

per Truth Table

I

OZH

Output Off Current HIGH 20 µA VCC = MAX, V

OUT

= 2.7 V

I

OZL

Output Off Current LOW –20 µA VCC = MAX, V

OUT

= 0.4 V

p

20 µA VCC = MAX, VIN = 2.7 V

IIHInput HIGH Current

0.1 mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

I

OS

Short Circuit Current (Note 1) –30 –130 mA VCC = MAX

pp

12 mA VCC = MAX, VE = 0 V

ICCPower Supply Current

14

mA VCC = MAX, VE = 4.5 V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (T

A

= 25°C, VCC = 5.0 V) See SN74LS251 for Waveforms

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

t

PLH

t

PHL

Propagation Delay,
Data to Output

17
13

25
20

ns Figure 1

t

PLH

t

PHL

Propagation Delay,
Select to Output

30
21

45
32

ns Figure 1

CL = 45 pF,
R

L

= 667 Ω

t

PZH

t

PZL

Output Enable Time

15
15

28
23

ns Figures 4, 5

t

PHZ

t

PLZ

Output Disable Time

27
18

41
27

ns Figures 3, 5

CL = 5.0 pF,

R

L

= 667 Ω

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5

P ACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SN74LS253

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6

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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Notes

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8

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