MOTOROLA SN74LS253ML2, SN74LS253N, SN74LS253D, SN74LS253DR2, SN74LS253M Datasheet
...
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS253/D
SN74LS253
Dual 4-Input Multiplexer
with 3-State Outputs
The LSTTL /MSI SN74LS253 is a Dual 4-Input Multiplexer with
3-state outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually switched to a
high impedance state with a HIGH on the respective Output Enable
(E
0
) inputs, allowing the outputs to interface directly with bus oriented
systems. It is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
• Schottky Process for High Speed
• Multifunction Capability
• Non-Inverting 3-State Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –2.6 mA
I
OL
Output Current – Low 24 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS253N 16 Pin DIP 2000 Units/Box
SN74LS253D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS253
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Common Select Inputs
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
S
0
, S
1
Multiplexer A
E
0a
I0a – I
3a
Z
a
Multiplexer B
E
0b
I0b – I
3b
Z
b
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
165431011121315
14
2
S
0
S
1
E0aI0aI1aI2aI3aI0bI1bI2bI3bE
0b
Z
a
Z
b
79
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
14 13 12 11 10 9
123456
7
16 15
8
V
CC
E
0a
E0bS0I3bI
2b
I
0b
I
1b
Z
b
S1I
3aI2aI1aI0aZa
GND
SN74LS253
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3
LOGIC DIAGRAM
E
0b
I
3b
I
2b
I
1b
I
0b
S
0
S
1
I
3a
I
2a
I
1a
I
0a
E
0a
Z
b
Z
a
14 126
7
3 4 5
9
1113 101215
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
selected by common select inputs (S
0
, S1). The 4-input
multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:
If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
Za = E0a ⋅(I0a ⋅S1 ⋅S0 + I
1a
⋅S1 ⋅S0 ⋅I2a ⋅S1 ⋅S0 + I3a ⋅ S1 ⋅S0)
Z
b
= E0b⋅ (I0b S1 S0 + I1b⋅ S1⋅ S0 I2b⋅ S1⋅ S0 + I3b⋅ S1⋅ S0)
TRUTH TABLE
SELECT
INPUTS
DATA INPUTS
OUTPUT
ENABLE
OUTPUT
S
0
S
1
I
0
I
1
I
2
I
3
E
0
Z
X X X X X X H (Z)
L LLXX X L L
L LHXX X L H
H LXLX X L L
H LXHX X L H
L HXXL X L L
L HXXH X L H
H HXXX L L L
H H X X X H L H
H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S
0
and S1 are common to both sections.
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