MOTOROLA SN74LS166D, SN74LS166M, SN74LS166MEL, SN74LS166ML1, SN74LS166MR1 Datasheet
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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS166/D
SN74LS166
8-Bit Shift Registers
The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 74LS standard
load. By utilizing input clamping diodes, switching transients are
minimized and system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and
has a complexity of 77 equivalent gates with gated clock inputs and an
overriding clear input. The shift/load input establishes the parallel-in
or serial-in mode. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock
pulse. Synchronous loading occurs on the next clock pulse when this is
low and the parallel data inputs are enabled. Serial data flow is
inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow
the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on
the clock inhibit input should only be done when the clock input is
high. A buffered direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero.
• Synchronous Load
• Direct Overriding Clear
• Parallel to Serial Conversion
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS166N 16 Pin DIP 2000 Units/Box
SN74LS166D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS166
http://onsemi.com
2
14 13 12 11 10 9
123456
7
16 15
8
V
CC
SERIAL
INPUT
SHIFT/
LOAD
HQ
H
GEF CLEAR
A B C D CLOCK
INHIBIT
CLOCK GND
PARALLEL PARALLEL INPUTS
INPUT OUTPUT
PARALLEL INPUTS
SHIFT/
LOAD
SERIAL INPUT
CLOCK
INHIBIT
HQHGFE
ABC D
CK
CLEAR
FUNCTION TABLE
INPUTS
INTERNAL
SHIFT/ CLOCK
PARALLEL
OUTPUTS
OUTPUT
Q
CLEAR
LOAD INHIBIT
CLOCK
SERIAL
A . . . H Q
A
Q
B
Q
H
L X X X X X L L L
H X L L X X Q
A0
Q
B0
Q
H0
H L L ↑ X a . . . h a b h
H H L ↑ H X H Q
An
Q
Gn
H H L ↑ L X L Q
An
Q
Gn
H X H ↑ X X Q
A0
Q
B0
Q
H0
SN74LS166
http://onsemi.com
3
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
PARALLEL
INPUTS
A
B
C
D
CLOCK INIHIBIT
CLOCK
SHIFT/LOAD
H
OUTPUT Q
H
G
F
E
CLEAR
SERIAL INPUT
H
H
H
H
H
L
L
L
HH H H H
LL
L
CLEAR
SERIAL SHIFT
LOAD
INHIBIT
SERIAL SHIFT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A
B
C
D
H
G
F
E
(9)
(1)
(15)
(2)
(3)
(4)
(5)
(10)
(11)
(12)
(14)
(7)
(6)
CLOCK INHIBIT
CLOCK
(13)
RCKS
Q
A
RCKS
Q
B
RCKS
Q
C
RCKS
Q
D
RCKS
Q
E
RCKS
Q
F
RCKS
Q
G
RCKS
Q
H
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