Motorola MCM63P636ZP250R, MCM63P636ZP250, MCM63P636ZP225, MCM63P636TQ200R, MCM63P636ZP200 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63P636/D

Advance Information

64K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM

The MCM63P636 is a 2M–bit synchronous fast static RAM designed to provide
burstable, high performance, secondary cache for advanced microprocessors.
It is organized as 64K words of 36 bits each. This device integrates input regis­ters, an output register, a 2–bit address counter, and a high speed SRAM onto
a single monolithic circuit for reduced parts count in cache data RAM applica­tions. Synchronous design allows for precise cycle control with the use of an ex­ternal clock (K) and external strobe clock (SK).

Addresses (SA), data inputs (DQx), and all control signals are clock (K)
controlled through positive–edge–triggered noninverting registers. Data strobes
STRBA, STRBA
positive–edge–triggered non–inverting registers. Strobe clock, 180 degrees out
of phase with clock (K), is only used with the data strobes such that they are
centered with data output on read cycles.

Burst sequences are initiated with ADS
addresses are generated internally by MCM63P636.

Write cycles are internally self–timed and are initiated with address and control
logic by the rising edge of the clock (K) input. This feature eliminates complex
off–chip write pulse generation and provides increased timing flexibility for
incoming signals. Special logic enables the memory to accept data on the rising
edge of clock (K) a cycle after address and control signals.

For read cycles, the SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the
second rising edge of clock (K) for a read latency of three cycles. Data strobes
rise and fall with SRAM output to help external devices receiving the data to
latch the data.

The MCM63P636 operates from a 3.3 V core power supply , a 2.0 V input power
supply, and a 2.0 V I/O power supply . These power supplies are designed so that
power sequencing is not required.

• MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)

MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)
MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)

• 3.3 V ± 200 mV VDD Supply , 2.0 V V

• Internally Self–Timed Late Write Cycle

• Three–Cycle Single–Read Latency

• Strobe Clock Input and Data Strobe Output Pins

• On–Chip Output Enable Control

• On–Chip Burst Advance Control

• Four–Tick Burst

• Power–On Reset Pin

• Low Power Stop Clock Operation

• Boundary Scan (PBGA Only)

• JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages

, STRBB, and STRBB are strobe clock (SK) controlled through

input pin, and subsequent burst

DDI

and V

DDQ

Supply

MCM63P636

ZP PACKAGE

PBGA

CASE 1107–01

TQ PACKAGE

TQFP

CASE 983A–01

This document contains information on a new product. Specifications and information herein are subject to change without notice.

3/16/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM63P636

1

PBGA

PIN ASSIGNMENT

6543217

89
A
B
C

D
E

F
G

H
J

K
L
M
N
P

R
T
U

V

V

SS

DQa DQa SA SE3
V

SS

DQa DQa V
V

SS

DQa

VSSV

DQa
V

SS

DQa DQa STRBA VDDNC
V

SS

DQa DQa V
V

SS

DQa DQa DQa SA

V

SS

DQa
V

SS

SA SE2 NC

DDQ

V

DDQ

V

DDQ

DQa V

DDQVDD

DQa STRBA

V

DDQ

V

DDQ

V

DDQ

V

DDQ
DQa SA SA0 SA

DDQ

SE1

NC

V

NU/V

SS

SS

DQa V

V

DD
DDIVDD

V

SS

V

DD
DDI

V

DD

V

SS

TDIV

ADS

DD

V

V

SS

SK VSSVDDV

V

SS

V

V

DD

NU/V

V

SS

V

V

SS

V

SA

DD

SA

V

SS

SA1SA

SA

TMS TRST

TCK

W

SS
K

SS

SS

SA

NU/V

SS

DD

RESET

DD

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

SA

SA

STRBB

STRBB

SA
SA

V

SS

DQb

V

DD

V

DDI

V

SS

V

DD

V

DDI

V

DD

DQb

V

SS

NC

TDO

V

DDQ

DQb

V

DDQ

DQb

V

DDQ

DQb

DDQVSS

DQb

V

DDQ

DQb

V

DDQ

DQb

V

DDQ

V

DDQ

DQb

V

DDQ

V

SS

DQb

V

SS

DQb
V

SS

DQb

DQb
V

SS

DQb
V

SS

DQb
V

SS

DQbDQb
V

SS

DQb
V

SS

153–BUMP PBGA

TOP VIEW

MCM63P636
2

MOTOROLA FAST SRAM

TQFP

PIN ASSIGNMENT

DQa
DQa
DQa

V

DDQ

V

SS

DQa
DQa
DQa
DQa
V

SS

V

DDQ

DQa
DQa

STRBA

V

DD

STRBA

V

SS
DQa
DQa

V

DDQ

V

SS
DQa
DQa

DQa
DQa
V

SS

V

DDQ

DQa
DQa
DQa

SASASE1

1
2
3
4
5
6
7

8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26
27
28
29
30

31 32 33

SS

SK

SE3

DD

VSSV

DDI

SE2

V

NU/VSSNU/V

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

37 3834 35 36 42 4339 40 41 45 4644

DD

DDI

NC

ADS

RESET

NU/V

SA

SA

DQb

80
79

DQb

78

DQb

77

V
76
75
74
73
72
71

70

69
68

67
66
65

64
63
62
61
60
59
58
57
56
55
54
53
52
51

50494847

DDQ

V

SS

DQb

DQb

DQb

DQb

V

SS

V

DDQ

DQb

DQb

V

SS
STRBB
V

DD
STRBB

DQb
DQb
V

DDQ
V

SS
DQb

DQb
DQb
DQb

V

SS
V

DDQ
DQb

DQb
DQb

V

K

W

SASASA

NC

SA

SA1

SA0

DDI

SS

NCVNC

DD

V

V

DDI

V

SASASA

SA

SA

SA

NC

MOTOROLA FAST SRAM

MCM63P636

3

PBGA PIN DESCRIPTIONS

Pin Locations Symbol

5D ADS Input Synchronous Address Status: Active low, used to initiate read or write

(a) 1B, 2B, 1D, 2D, 3D, 1F, 2F, 1H, 2H,

1K, 2K, 1M, 2M, 1P, 2P, 3P, 1T, 2T

(b) 8B, 9B, 7D, 8D, 9D, 8F, 9F, 8H, 9H,

8K, 9K, 8M, 9M, 7P, 8P, 9P, 8T, 9T

5F K Input Clock: This signal registers the address, data in, and all control signals.
6C RESET Input Asynchronous Power–On Reset: Active low at power up, resets internal

3A, 7A, 3B, 7B, 5M, 5N,

4P, 5P, 6P, 4R, 6R, 3T, 4T, 6T

5R, 5T SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

4A SE1 Input Synchronous Chip Enable: Active low to enable chip.
5A SE2 Input Synchronous Chip Enable: Active high to enable chip.
4B SE3 Input Synchronous Chip Enable: Active low to enable chip.
5G SK Input Data Strobe Clock: 180 degrees out–of–phase with K. Used only with

3K STRBA Output Data Strobe: Used in reference to DQa I/Os.
3H STRBA Output Data Strobe: Used in reference to DQa I/Os.
7K STRBB Output Data Strobe: Used in reference to DQb I/Os.
7H STRBB Output Data Strobe: Used in reference to DQb I/Os.
5U TCK Input Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK

3U TDI Input Boundary Scan Pin, T est Data In.
7U TDO Output Boundary Scan Pin, Test Data Out.
4U TMS Input Boundary Scan Pin, Test Mode Select.
6U TRST Input Boundary Scan Pin, Asynchronous T est Reset. If boundary scan is not

5C W Input Synchronous Write.

4D, 6D, 3E, 7E, 4F, 6F, 3G, 7G,

4H, 6H, 4K, 6K, 3L, 7L, 4M, 6M, 3N, 7N

3F, 7F, 3M, 7M V

2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G,

2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U

1A, 9A, 1C, 3C, 7C, 9C, 1E, 4E, 5E,
6E, 9E, 1G, 4G, 6G, 9G, 5H, 1J, 3J,

4J, 6J, 7J, 9J, 1L, 4L, 5L, 6L, 9L, 1N,

4N, 6N, 9N, 1R, 3R, 7R, 9R, 1U, 9U

6A, 5B, 5K, 7T NC — No Connection: There is no connection to the chip.

6B NU/V

4C, 5J NU/V

Type Description

state machines latch in external addresses, or deselect chip.

DQx I/O Synchronous Data I/O: “x” refers to the word being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

V

V

V

DD

DDI

DDQ

SS

Supply Core Power Supply.

Supply Input Power Supply.
Supply I/O Power Supply.

Supply Ground.

DD

SS

(I/Os a and b).

state machines.

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

data strobes.

must be tied to VDD or VSS.

used, TRST

— Not Usable: There is an internal connection to the chip. This pin may be

left unconnected or tied to VDD.

— Not Usable: There is an internal connection to the chip. This pin may be

left unconnected or tied to VSS.

must be tied to VSS.

MCM63P636
4

MOTOROLA FAST SRAM

TQFP PIN DESCRIPTIONS

Pin Locations Symbol

85 ADS Input Synchronous Address Status: Active low, used to initiate read or write

(a) 1, 2, 3, 6, 7, 8, 9, 12, 13, 18,

19, 22, 23, 24, 25, 28, 29, 30

(b) 51, 52, 53, 56, 57, 58, 59, 62, 63,

68, 69, 72, 73, 74, 75, 78, 79, 80

89 K Input Clock: This signal registers the address, data in, and all control signals.
84 RESET Input Asynchronous Power–On Reset: Active low at power up, resets internal

32, 33, 34, 35, 44, 45, 46,

47, 48, 49, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
97 SE2 Input Synchronous Chip Enable: Active high to enable chip.
92 SE3 Input Synchronous Chip Enable: Active low to enable chip.
93 SK Input Data Strobe Clock: 180 degrees out–of–phase with K. Used only with

16 STRBA Output Data Strobe: Used in reference to DQa I/Os.
14 STRBA Output Data Strobe: Used in reference to DQa I/Os.
64 STRBB Output Data Strobe: Used in reference to DQb I/Os.
66 STRBB Output Data Strobe: Used in reference to DQb I/Os.

88 W Input Synchronous Write.
15, 41, 65, 91 V
38, 43, 87, 94 V

4, 11, 20, 27, 54, 61, 70, 77 V

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

31, 39, 42, 50, 86 NC — No Connection: There is no connection to the chip.

83 NU/V

95, 96 NU/V

Type Description

state machines latch in external addresses, or deselect chip.

DQx I/O Synchronous Data I/O: “x” refers to the word being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

DD

DDI

DDQ

V

SS

Supply Core Power Supply.
Supply Input Power Supply.
Supply I/O Power Supply.
Supply Ground.

DD

SS

(I/Os a and b).

state machines.

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

data strobes.

— Not Usable: There is an internal connection to the chip. This pin may be

left unconnected or tied to VDD.

— Not Usable: There is an internal connection to the chip. This pin may be

left unconnected or tied to VSS.

MOTOROLA FAST SRAM

MCM63P636

5

TRUTH TABLE (See Notes 1 and 2)

K

L – H False 0 X Deselect D High–Z —
L – H True 0 0 Load Address, Begin Write BW Data In —
L – H True 0 1 Load Address, Begin Read BR — Data Out
L – H X 1 0 Continue Write CW Data In —
L – H X 1 1 Continue Read

NOTES:

1. X = don’t care, 1 = logic high, 0 = logic low.

2. E = true if SE1

E ADS W Next Cycle (n) Input Command Code DQ (n + 1) DQ (n+2)

Mask Write

and SE3 = 0, and SE2 = 1.

CR

MW

—

High–Z

Data Out

BURST ADDRESS TABLE

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X1 1 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

D, CW, CR – MW

BR

DESELECT

—

NEW

READ*

CR

BURST

READ 1*

CR

BURST

READ 2*

CR

BURST

READ 3*

BR

D, CW, MW

BW

BW

D, CW, MW

BW

NEW

WRITE*

CW

BURST

WRITE 1*

CW

BURST

WRITE 2*

CW

BURST

WRITE 3*

BR

MW

MW

MW

MASKED
WRITE 1*

MW

MASKED
WRITE 2*

MW

MASKED
WRITE 3*

BR

BW

D, CW, MW

MCM63P636
6

*Command code inputs not shown from this state are not valid.

Figure 1. Functional State Diagram

MOTOROLA FAST SRAM

D, CW, CR – MW

INTERMEDIATE

HIGH–Z1,

INTERMEDIA TE

HIGH–Z1,

DATA–OUT/

Q(1)VALID1,

DATA–OUT/

Q(2)VALID1,

4

CR

4

CR

CR

BR

2

3

HIGH–Z

4

BW

DATA–IN (1)/

HIGH–Z1,

DATA–IN (2)/

HIGH–Z1,

DATA–IN (3)/

HIGH–Z1,

DATA–IN (4)/

HIGH–Z1,

4

CW

4

CW

4

CW

4

MW

MW

MW

MASK (2)/

HIGH–Z1,

MW

MASK (3)/

HIGH–Z1,

MW

MASK (4)/

HIGH–Z1,

MW

4

4

4

CR

DATA–OUT/

Q(3)VALID1,

BR

CR

DATA–OUT/

Q(4)VALID1,

NOTES:

1. Command code inputs not shown from this state are not valid.

2. STRBA and STRBB transition from logic 1 to 0. STRBA

3. STRBA and STRBB transition from logic 0 to 1. STRBA

4. Data strobes are driven to High–Z.

CR

2

3

DATA–OUT/

Q(4)VALID1,

D, CW, CR

3

BR

Figure 2. Data I/O State Diagram

CW, MW

HIGH–Z1,

and STRBB transition from logic 0 to 1.
and STRBB transition from logic 1 to 0.

4

CW, MW

HIGH–Z1,

4

MW

MOTOROLA FAST SRAM

MCM63P636

7

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit Notes

Power Supply Voltage V
I/O Supply Voltage V
Input Supply Voltage V
Voltage Relative to VSS for Any Pin

Except V
Input Voltage (Three–State I/O) V

Output Current (per I/O) I
Package Power Dissipation P
Temperature Under Bias T
Storage Temperature T

NOTES:

DD

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.

3. V

= V

DDI

4. Max Vin and VIT are not to exceed Max VDD.

5. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.

DDQ

.

DD

DDQ

DDI

V

out

bias

stg

VSS – 0.5 to + 4.0 V

VSS – 0.5 to 2.5 V 2, 3
VSS – 0.5 to 2.5 V 2, 3

in

IT

D

VSS – 0.5 to

V

DDI

VSS – 0.5 to

V

DDQ

± 20 mA

2.75 W 5

– 10 to 85 °C

– 55 to 125 °C

+ 0.5

V 2, 4

V 2, 4

+ 0.5

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

PACKAGE THERMAL CHARACTERISTICS — PBGA

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) R
Junction to Board (Bottom) R
Junction to Case (Top) R

θJA
θJB
θJC

25 °C/W 1, 2
12 °C/W 3
10 °C/W 4

PACKAGE THERMAL CHARACTERISTICS — TQFP

Rating Symbol Max Unit Notes

Junction to Ambient (@ 200 lfm) R
Junction to Board (Bottom) R
Junction to Case (Top) R

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

θJA
θJB
θJC

25 °C/W 1, 2
17 °C/W 3

9 °C/W 4

MCM63P636
8

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 200 mV, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltage Referenced to V

Parameter Symbol Min Typ Max Unit

Supply Voltage V
Input Supply Voltage V
I/O Supply Voltage V
Input Low Voltage (V
Input High Voltage (V
Input Leakage Current (0 V ≤ Vin ≤ VDD) I
Output Leakage Current (0 V ≤ Vin ≤ V
Output Low Voltage (IOL = 1 mA) V
Output High Voltage (IOL = – 1 mA) V

DDI

DDI

= V

= V

) V

DDQ

) V

DDQ

) I

DDQ

V

IH

V

SS

VSS – 0.25 V

VSS – 0.5 V

DD
DDI

DDQ

IL
IH

lkg(I)

lkg(O)

OL

OH

20% t

3.1 3.3 3.5 V

1.8 — 2.2 V

1.8 — 2.2 V

– 0.5 — 0.35 x V

0.65 x V

DDI

— — ± 1 µA
— — ± 1 µA

– 0.5 — 0.4 V

V

– 0.4 — V

DDQ

KHKH

— V

Figure 3. Undershoot Voltage

SS

= 0 V)

DDI

DDQ

DDI

+ 0.5 V

+ 0.5 V

V

SUPPLY CURRENTS

Parameter Symbol Min Max Unit Notes

AC Supply Current (Device Selected, All Outputs Open,
Freq = Max, VDD = Max)

Input and I/O Supply Current – Desktop (All 40 Outputs Toggling,
Freq = Max, V

Static Standby Supply Current (Device Deselected, Freq = Max,
VDD = Max, ADS
or ≥ (V

DDI

Outputs Disabled)
Idle Standby Supply Current (Device Deselected, Freq = 0,

VDD = Max, ADS
or ≥ (V

DDI

Outputs Disabled)
Idle Input Standby Supply Current (Device Deselected, Freq = 0,

VDD = Max, ADS
or ≥ (V

DDI

Outputs Disabled)

NOTES:

1. Device is selected and deselected as defined by the T ruth Table.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. Data states are all zero.

4. Includes supply current for VDD only.

5. Includes supply currents for V

= Max, V

DDI

≥ (V

≥ (V

≥ (V

DDI

DDI

DDI

– 0.2 V), SA and DQx Inputs Static ≤ (VSS + 0.2 V),

– 0.2 V), SA and DQx Inputs Static ≤ (VSS + 0.2 V),

– 0.2 V), SA and DQx Inputs Static ≤ (VSS + 0.2 V),

= Max, V

DDQ

– 0.2 V), W Static ≤ (VSS + 0.2 V)

– 0.2 V), W Static ≤ (VSS + 0.2 V)

– 0.2 V), W Static ≤ (VSS + 0.2 V)

DDI

DDI

and V

= V

DDQ

, Cdt = 24 pF)

DDQ

only.

I

DDA

I

DDA

I

DDA

I

DDQ

I

DDQ

I

DDQ

I

SB1

I

SB1

I

SB1

– 250
– 225
– 200

– 250
– 225
– 200

– 250
– 225
– 200

I

SB2A

I

SB2B

— TBD mA 1, 2,

— 311

280
249

— 63

57
50

— TBD mA 1, 3, 4

— TBD mA 1, 3, 5

mA 2, 5

mA 1, 2, 4

3, 4

MOTOROLA FAST SRAM

MCM63P636

9